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Publication numberUS5146110 A
Publication typeGrant
Application numberUS 07/736,577
Publication dateSep 8, 1992
Filing dateJul 26, 1991
Priority dateMay 22, 1991
Fee statusPaid
Publication number07736577, 736577, US 5146110 A, US 5146110A, US-A-5146110, US5146110 A, US5146110A
InventorsTae-Jin Kim, Kyu-Chan Lee
Original AssigneeSamsung Electronics Co., Ltd.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor memory with substrate voltage generating circuit for removing unwanted substrate current during precharge cycle memory mode of operation
US 5146110 A
Abstract
A semiconductor memory device having a substrate voltage production circuit comprises a time delay circuit. The time delay circuit of the present invention has a simple construction and is provided to facilitate removal of an unwanted substrate current ISUB existing during a precharge cycle of memory operation. The substrate voltage production circuit requires no additional regulating signals for operation. Latch-up conditions commonly caused by such unwanted substrate currents are eliminated and stable semiconductor memory device operation is achieved.
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Claims(3)
What is claimed is:
1. A substrate voltage generating circuit in a semiconductor memory device having at least one clock period comprising a memory active cycle and a memory precharge cycle, said substrate voltage generating circuit comprising:
time delay circuit means having a plurality of inverters connected in series, a NOR gate and an inverter for generating a delay signal in response to an active cycle of said at least one clock period;
active mode substrate voltage generating means for generating an active voltage signal, in response to said delay signal, to remove a substrate current ISUB from a memory array portion, said delay signal generating said active voltage signal during at least a portion of a memory precharge cycle;
stand-by substrate voltage generating means for generating a stand-by signal to said memory array portion, said stand-by signal being active at least during a portion of the memory precharge cycle when said active voltage signal is disabled.
2. The substrate voltage generating circuit of claim 1, wherein a duration in delay of said signal is related to the number of said plurality of inverters.
3. The substrate voltage generating circuit of claim 1, wherein the active voltage signal is enabled when said stand-by signal is enabled so as to simultaneously enabled for a duration of each clock period.
Description
BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device having a substrate voltage production circuit which includes a time delay circuit for removing substrate current ISUB during both precharge cycle time and active cycle time of a clock period.

2. Background Information

Generally, a substrate current ISUB is generated during normal operation of a semiconductor memory device.

If the substrate current ISUB is not effectively removed by a substrate voltage production circuit, the semiconductor memory device is likely to latch up under normal operating conditions and an erroneous operation may occur.

Accordingly, removing of the substrate current ISUB is a main focus in semiconductor memory design where stable operation and fast speed is critical.

In the past, in connection with DRAM technology, a substrate current ISUB exists at two select specified time orders.

As shown in FIG. 3, a substrate current of a first time order is generated when a sense amplifier (S/A) 3 develops data to be stored in memory cell MC comprising transistor Mφ and capacitor C1 (active cycle).

After an external chip selection signal is disabled (precharge cycle) and an equalizing signal φ EQ on bit lines B/L, B/L is enabled, transistors M1, M2 and M3 equalize bit lines B/L, B/L completely. As much as 1/2 Vcc (Vcc is an operating power source voltage) develops across the bit lines to generate a substrate current at a second time order. The substrate voltage production circuit for removing unwanted substrate current ISUB is in stand-by mode when a capacitance of supply source voltage is small (i.e., precharge cycle) and in active mode when the capacitance of supply source voltage is large (i.e., active cycle).

Conventionally, the stand-by mode is always operational, however, the active mode of the substrate voltage production circuit is operational only during the active cycle of semiconductor memory access.

Hence, because the cycle generating the substrate current of a first time order is the active cycle of memory operation, both substrate voltage production circuit stand-by mode and active mode are operational.

Thus, the unwanted substrate current ISUB is effectively removed by the substrate voltage production circuit.

However, during the precharge cycle when the substrate current ISUB is also known to be increasingly generated the substrate voltage production circuit is not-operational with respect to the active mode.

As discussed above, unremoved substrate current during the precharge cycle can lead to the problem of latch up and erroneous memory operation.

SUMMARY OF THE INVENTION

Accordingly, the present invention was made so as to solve the above-mentioned problem.

An object of the present invention is to provide a semiconductor memory device with stable operation. The present invention includes a time delay circuit to decrease the possibility of latch-up in a semiconductor memory chip by removing a substrate current ISUB .

A substrate voltage production circuit normally in the active mode of operation is made operative during at least a portion of a precharge cycle under the control of the time delay circuit.

To achieve the above object, a semiconductor memory device is provided with substrate voltage production circuit which comprises a time delay circuit DP including a plurality of inverters connected in series, a NOR gate and an inverter, a VBB generator circuit 2 for stand-by mode of operation.

The time delay circuit part DP inputs an external chip selection signal and utilizes an active master signal φRM. φRM is delayed a predetermined duration of time in a given cycle such that a substrate current ISUB can be removed by allowing the operation of the VBB Generator circuit 1 for active mode of operation to operate during a precharge cycle.

BRIEF DESCRIPTION OF THE DRAWINGS

The above object and feature of the present invention will be apparent from the following description of the preferred embodiment with reference to the accompanying drawings.

FIG. 1 is a diagram showing an embodiment of a substrate voltage production circuit according to the present invention.

FIG. 2 is a timing chart showing operation of the present invention in connection with the substrate voltage production circuit of FIG. 1.

FIG. 3 is a diagram showing a portion of a DRAM memory cell array.

DETAILED DESCRIPTION OF THE INVENTION

A detailed description will be given regarding a constitution, function and effect of the present invention with reference to the attached figures.

FIG. 1 shows a substrate voltage production circuit with a time delay circuit in connection with the present invention. FIG. 2 is a timing diagram showing an operation of the substrate voltage production circuit according to the present invention.

As shown in FIGS. 1 and 2, an active master signal φRM is generated by in response to an external chip selection signal. As signal φRM passes through the time delay circuit DP which is constructed with a plurality of inverters connected in series, a NOR gate and an inverter, active master signal φRM (at a point A in FIG. 1) has a waveform characteristic that is delayed a predetermined duration of time (see node A shown in FIG. 2). Similarly, signal φRM at point B in FIG. 1 forms a delayed waveform shown as node B in FIG. 2.

The number of inverters determines how long the active master signal φRM delay duration will last. Since the substrate current ISUB is effectively removed by VBB Generator Circuit 1 active mode, the delay extends its operation into the next cycle of the memory access period.

A description of the operation of the present invention will be given hereinafter.

If an external chip selection signal is enabled active "low", VBB Generator Circuit 1 for active mode gates the active master signal φRM which is similarly enabled by the output stage of the plurality of inverters and NOR gate of the DP circuit.

The substrate voltage production circuit can be operated by the active master signal φRM directly gated to the NOR gate.

After the active cycle of memory operation has elapsed, the active master signal φRM becomes disabled. However, the delayed waveform shown by node A of FIG. 2 and driven by time delay circuit DP continuous to drive VBB Generator Circuit 1 for active mode well into the next cycle (precharge cycle).

The VBB Generator Circuit 2 stand-by mode continues to run under oscillator control and provides precharge VBB for DRAM memory access operation.

Therefore, a substrate voltage production circuit having a time delay circuit in accordance with the present invention has a simple construction which can easily remove a substrate current ISUB during precharge cycle without creating a need for additional regulating signals.

As a result, latch-up problems due to unwanted substrate currents are obviated providing a semiconductor memory device having stable operation.

The present invention is not limited to the above embodiment, and variations and modifications may be made without departing from the scope of the present invention.

Patent Citations
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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US5341340 *Mar 29, 1993Aug 23, 1994Mitsubishi Denki Kabushiki KaishaSemiconductor memory device and operating method
US5376840 *Nov 27, 1992Dec 27, 1994Nec CorporationSubstrate bias voltage generator having current ability based on external and internal power voltages
US5404325 *Jun 10, 1993Apr 4, 1995Nec CorporationDynamic random access memory device with precharging unit preventing counter electrodes of storage capacitors from voltage fluctuation
US5461591 *Dec 2, 1993Oct 24, 1995Goldstar Electron Co., Ltd.Voltage generator for semiconductor memory device
US5557231 *Aug 15, 1994Sep 17, 1996Mitsubishi Denki Kabushiki KaishaSemiconductor device with improved substrate bias voltage generating circuit
US6232797 *Aug 20, 1999May 15, 2001Samsung Electronics Co., Ltd.Integrated circuit devices having data buffer control circuitry therein that accounts for clock irregularities
US6307412 *Jun 1, 1999Oct 23, 2001Samsung Electronics Co., Ltd.Clock monitor circuit and synchronous semiconductor memory device utilizing the circuit
US6333873 *Sep 29, 1997Dec 25, 2001Mitsubishi Denki Kabushiki KaishaSemiconductor memory device with an internal voltage generating circuit
US6731149 *Dec 6, 2001May 4, 2004Kabushiki Kaisha ToshibaSynchronizing circuit for generating a signal synchronizing with a clock signal
Classifications
U.S. Classification327/537, 365/189.09, 326/95
International ClassificationG05F3/20, G11C5/14
Cooperative ClassificationG05F3/205, G11C5/146
European ClassificationG11C5/14P1, G05F3/20S
Legal Events
DateCodeEventDescription
Jul 26, 1991ASAssignment
Owner name: SAMSUNG ELECTRONICS CO., LTD.,, KOREA, REPUBLIC OF
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:KIM, TAE-JIN;LEE, KYU-CHAN;REEL/FRAME:005793/0539
Effective date: 19910708
Nov 15, 1995FPAYFee payment
Year of fee payment: 4
Feb 28, 2000FPAYFee payment
Year of fee payment: 8
Sep 26, 2003FPAYFee payment
Year of fee payment: 12