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Publication numberUS5148263 A
Publication typeGrant
Application numberUS 07/684,151
Publication dateSep 15, 1992
Filing dateApr 12, 1991
Priority dateDec 16, 1988
Fee statusPaid
Also published asEP0378809A2, EP0378809A3
Publication number07684151, 684151, US 5148263 A, US 5148263A, US-A-5148263, US5148263 A, US5148263A
InventorsTsuneo Hamai
Original AssigneeKabushiki Kaisha Toshiba
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor device having a multi-layer interconnect structure
US 5148263 A
Abstract
A semiconductor device has a multi-layer structure comprising three or more interconnect layers formed over a substrate, one of these interconnect layers being a first power supply line and another metal interconnect layer being a second power supply line, the first and second power supply lines being arranged in a multi-level fashion such that one is superposed relative to the other in a plan view. That is, the power supply lines are arranged as a multi-layer metal interconnect layer array such that the first and second power supply lines are superposed in a multi-level fashion in a plan view.
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Claims(3)
What is claimed is:
1. A semiconductor device having a multi-layer metal interconnect structure comprising:
at least three metal interconnect layers formed over a substrate;
a first metal interconnect layer constituting a first power supply line, wherein said first power supply line comprises a plurality of interconnect layers; and
a second metal interconnect layer vertically aligned with and separated from the first metal interconnect layer, and constituting a second power supply line.
the first and second power supply lines each being a closed trunk line for applying voltages to said device.
2. A semiconductor device having a multi-layer metal interconnect structure comprising:
at least three metal interconnect layers formed over a substrate;
a first metal interconnect layer constituting a first power supply line; and
a second metal interconnect layer vertically aligned with and separated from the first metal interconnect layer, and constituting a second power supply line, wherein said second power supply line comprises a plurality of interconnect layers,
the first and second power supply lines each being a closed trunk line for applying voltages to said device.
3. A semiconductor device having a multi-layer metal interconnect structure comprising:
at least three metal interconnect layers formed over a substrate;
a first metal interconnect layer constituting a first power supply line; and
a second metal interconnect layer vertically aligned with and separated from the first metal interconnect layer, and constituting a second power supply line,
the first and second power supply lines each being a closed trunk line for applying voltages to said device, and wherein said first and second power supply lines each comprise a plurality of interconnect layers.
Description

This application is a continuation of application Ser. No. 07/448,360, filed Dec. 11, 1989, now abandoned.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device having a multi-layer interconnect metal structure made up of three or more layers and, in particular, to the layout of main power supply lines for a semiconductor device of multi-layer interconnect metal structure.

2. Description of the Related Art

FIG. 1 is a plan view showing a conventional multilayer interconnect pattern Reference numeral 1 denotes an IC chip whose power supplies VDD and GND are connected to a power supply pad 2 and ground pad 3, respectively, and are also connected to closed-loop patterns (power supply line patterns) 6 and 7, respectively, via a second metal layer (Al) 4 and first metal layer (Al) 5. The closed-loop patterns 6 and 7 are formed of the same material as that of the second metal layer (left-inclined hatched area in FIG. 1) in which case due consideration is paid to input/output signal lines 9, 10, and 11 coming from a logic block 8. The input/output signal lines 9, 10, and 11 coming from the logic block 8 are formed of the same material as the first metal layer (interconnect pattern without a hatched area) and provide a multi-level crossing relative to the power supply line patterns 6 and 7. Signal lines 9, 10, and 11 are connected to an input pad 12, output pad 13, and logic block 14, respectively.

In the conventional semiconductor device, elements, such as transistors, are not formed at a pattern area between an interconnect pad and a logic block, or at a pattern area between a logic block and another logic block, this being because the pattern areas are used as interconnect areas for power supply lines and signal lines. On the other hand, the pattern width of the power supply lines 6 and 7 needs be broadened due to a need for more current flow in which case the size of the chip 1 is increased, for example, due to an increase in the number of transistors in the chip 1 and hence an increase in dissipation current in the chip 1. Such an increase in the size of the chip 1 results in an increase in the size of the interconnect area between the pad and the logic block and between the logic blocks. This prevents an increase in the integration density of transistors and hence a reduction in the chip size. That is, even if the integration density of the transistors is to be increased, there is no significant decrease in the area taken up by the power supply lines; rather, an increase in the number of transistors results in an increase in the width of the power supply lines. Consequently, no substantial reduction in the chip size is possible.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention is to solve the aforementioned drawbacks by providing a semiconductor device in which the area taken up by two or more types of power supply lines within a semiconductor chip is reduced.

According to the present invention, a semiconductor device of a multi-layer structure is provided wherein the element area required is reduced and a power supply line noise is reduced by a capacitor component between the power supply lines.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of an interconnect pattern of a conventional semiconductor device;

FIG. 2 is a plan view of an interconnect pattern of a semiconductor device according to an embodiment of the present invention; and

FIG. 3 is a schematic view, as taken in line III--III in FIG. 2, of the embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

A semiconductor device according to the embodiment of the present invention will now be explained below, with reference to the accompanying drawings.

FIG. 2 is a plan view of an interconnect pattern of a semiconductor device according to the embodiment of the present invention. Identical reference numerals are employed in FIG. 2 to designate parts or components corresponding to those shown in FIG. 1.

As is shown in FIG. 2, closed-loop power supply line patterns 21 and 22 over a chip 1 are of such a type that a second metal layer (for example, Al) as indicated by a left-inclined hatched area and third metal layer (for example, Al) as indicated by right-inclined hatched area are independently and three-dimensionally formed in a superposed fashion in a plan view. A power supply VDD is connected to a power supply pad 2 and connected by, for example, a second metal layer 4 to the closed-loop power supply line pattern 21. A power supply GND is connected to the power supply pad 3 and connected by, for example, a third metal layer 5' to the closed-loop power supply line pattern 22. Input/output signal lines 9 to 11 coming from a logic block 8 are formed of a first metal layer as indicated by a non-hatched area and provided, as a multi-level crossing, relative to the power supply lines 21 and 22. The input/output signal lines 9, 10, and 11 are connected to an input pad 12, output pad 13, and logic block 14, respectively.

FIG. 3 is a cross-sectional view of the power supply line interconnect pattern area shown in FIG. 2. An input/output signal line 9 is formed as the first metal layer, this being the lowermost layer, the power supply line pattern (VDD power supply) 21 is formed as the second metal layer, one level higher than that of the first metal layer, and the power supply line pattern 22 (GND power supply) is formed as the third metal layer, or the topmost layer, over the second metal layer. Formed thus, the respective layers are not electrically connected to each other, since they are insulated from each other even if being connected in a multi-level fashion.

The VDD power supply line 7 and GND power supply line 6, which are formed in parallel fashion with one of these power supply lines spaced from the other in a plan view in the conventional semiconductor device, can be superposed in a three-dimensional array, thus reducing the size of the pattern area as viewed from a plan view. As an added advantage, it is possible to reduce the amount of power supply noise caused, for example, by the simultaneous switching of the greater number of transistors contained in the chip, because a capacitor C of parallel flat sheet configuration, is created between the VDD and the GND.

The present invention, when applied not only to a main power supply between the logic block and the pad but also to a main line between the logic blocks, obtains the same advantage as set forth above. Although the embodiment of the present invention has been explained in connection with the three-layer metal interconnect structure, the same advantage can be obtained if the structure has three or more layers. In this case, a plurality of metal interconnect layers may be employed for a single power supply. Furthermore, the metal interconnect layers 21 and 22 and signal interconnect layers 9 to 11 may be arranged one over another in a proper multi-level fashion.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US4893170 *Apr 11, 1984Jan 9, 1990Mitsubishi Denki Kabushiki KaishaSemiconductor device with multi-level wiring in a gate array
EP0259631A2 *Aug 11, 1987Mar 16, 1988Fujitsu LimitedSemiconductor device having power supply lines
EP0307722A1 *Aug 31, 1988Mar 22, 1989Kabushiki Kaisha ToshibaSemiconductor device having improved multilayered wirings
JPS6146050A * Title not available
JPS61218155A * Title not available
Non-Patent Citations
Reference
1"Semiconductor Integrated Circuit Device ", Patent Abstracts of Japan, vol. 10, No. 205 (E-420) (2261) Jul. 17, 1986, & JP-A-61 046050 (NEC IC Microcomput Syst Ltd) Mar. 6, 1986.
2 *PATENT ABSTRACTS OF JAPAN vol. 11, no. 59 (E-482)(2506) 24 February 1987, & JP-A-61 218 155 (HITACHI) 27 September 1986,
3Patent Abstracts of Japan, vol. 11 No. 59 (E-482) (2506) Feb. 24, 1987, & JP-A-61 218155, Sep. 27, 1986.
4 *Semiconductor Integrated Circuit Device , Patent Abstracts of Japan, vol. 10, No. 205 (E 420) (2261) Jul. 17, 1986, & JP A 61 046050 (NEC IC Microcomput Syst Ltd) Mar. 6, 1986.
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Classifications
U.S. Classification257/758, 257/E23.144, 257/207, 257/E23.153
International ClassificationH01L23/52, H01L23/522, H01L21/822, H01L23/528, H01L27/04, H01L21/3205
Cooperative ClassificationH01L23/5222, H01L2924/0002, H01L23/5286
European ClassificationH01L23/522C, H01L23/528P
Legal Events
DateCodeEventDescription
Sep 26, 2003FPAYFee payment
Year of fee payment: 12
Mar 6, 2000FPAYFee payment
Year of fee payment: 8
Mar 4, 1996FPAYFee payment
Year of fee payment: 4
Nov 16, 1993CCCertificate of correction