|Publication number||US5166556 A|
|Application number||US 07/644,231|
|Publication date||Nov 24, 1992|
|Filing date||Jan 22, 1991|
|Priority date||Jan 22, 1991|
|Also published as||EP0501120A2, EP0501120A3|
|Publication number||07644231, 644231, US 5166556 A, US 5166556A, US-A-5166556, US5166556 A, US5166556A|
|Inventors||Fu-Chieh Hsu, Pei-Lin Pai|
|Original Assignee||Myson Technology, Inc., Knights Technology, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (32), Non-Patent Citations (4), Referenced by (214), Classifications (13), Legal Events (8)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The invention relates generally to semiconductors and more specifically to the "antifuse" memory cell and interconnect structures used in programmable read only memories (PROMs) and application specific integrated circuits (ASICs).
2. Description of the Prior Art
Many different types of semiconductor devices use memory cells to store programs, data, and other important information. Two basic kinds of memory cells are the random access memory (RAM) and the read only memory (ROM). The memory cells in RAM may be read and written many times, but the storage is not permanent, and data will be erased when power is cutoff. The memory cells in ROM retain their data regardless of whether power is on or off, but once a memory cell is programmed, it generally cannot be reprogrammed. ROMs and ASICs can have data impressed into them by mask processing, laser, electron beam, focused ion beam (FIB), and/or electrical programming. (For laser and FIB programming, see, R. Iscoff, "Characterizing Quickturn ASICs: It's Done with Mirrors," Semiconductor International, August 1990, pp.68-73.) ROMs that can be electrically programmed, albeit only once, are called programmable read only memories (PROMs). Memory cells within some PROMs use fuse links that are literally blown open during programming. An opposite type of memory cell using "antifuse" technology, establishes a connection from an open state during programming. In large programmable or configurable systems and circuits, antifuse is much more efficient than fuse because typically only a fraction of antifuses need to be programmed for similar functions implemented with fuses. The prior art method of programming antifuses is almost always electrical programming. Raffel, et al. U.S. Pat. No. 4,585,490, issued Apr. 29, 1986, discloses using thin oxides as a metal diffusion barrier and silicon as a programming layer in a laser programmed device. However, the chemical reaction is simple aluminum alloying which does not have good reliability nor resistance to electromigration.
Polysilicon structures are conventional, and are used in fuse type PROM fabrication. One such structure is described in Preedy U.S. Pat. No. 4,420,820 issued Dec. 13, 1983. A polysilicon layer is formed with laterally spaced surface regions which differ in impurity concentration and which form two back-to-back series diodes functioning as a programmable diode and isolating diode. Because of the different impurity concentrations, one of the diodes will breakdown before the other.
Prior art antifuse methods include the use of dielectrics made of oxide, oxide/nitride/oxide sandwiched between silicon or polysilicon. These structures are characterized by high "ON" resistance (≧1000Ω) and high electrical programming voltages (≧15V). These two characteristics, respectively, make for low performance and difficulty in scaling to submicron processes. This structure, however, does not provide very low leakage current in the "off" state, due to its low bulk conductivity. Amorphized doped silicon by ion implantation has been used in the prior art to create PROM memory cells, and, for example, is described in Stacey, et al. U.S. Pat. No. 4,569,120, issued on Feb. 11, 1986. These structures have not exhibited good control of ON resistance and have limited scalability. Deposited amorphous-silicon on silicon has high parasitic (junction) capacitance, high series resistance and is difficult to remove inside normal contacts without damaging the underlying silicon. (Amorphous silicon is silicon without discernable crystalline grains, as opposed to polycrystalline silicon which has pronounced crystalline grain structures.) An amorphous semiconductor layer for use in a PROM is described in Lim, et al. U.S. Pat. No. 4,569,121 issued on Feb. 11, 1986. The present inventors have observed the best prior art antifuse performance comes from a sandwich layer of titanium-tungsten (TiW)/amorphous-silicon/TiW. Gordon, et al. U.S. Pat. No. 4,914,055, issued on Apr. 3, 1990 describes a TiW-Si-TiW structure that is planar and provides more uniform electric fields across an antifuse structure during programming. (The bottom TiW is not etched or damaged prior to Si deposition.) Hollingsworth U.S. Pat. No. 4,748,490, issued May 31, 1988, describes a deep polysilicon emitter antifuse memory cell having a titanium tungsten (TiW) alloy refractory conductive layer. ("Refractory" means very high melting temperature metal, compared to aluminum, gold, and silver.) There, the antifuse layer is alternatively fabricated from undoped polycrystalline silicon or amorphous silicon. A bipolar transistor that remains after programming is used to provide faster switching of the circuit. However, high temperatures must be used to deposit the amorphous layers, described above, and as such, the prior art techniques require very complicated processes to construct an antifuse element. At least four additional masks and nine more processing steps are typically necessary. Furthermore, the above prior art antifuse structures are not always compatible with standard submicron CMOS/BiCMOS metal processes. Another major disadvantage of amorphous-silicon based antifuse is that the leakage current is generally much higher than oxide or nitride based antifuse due to bulk conductivity differences.
Lower programming and operating currents in memory cells translate directly to smaller programming current devices, size and depth of the cell, and ultimately to the size and current capabilities of devices peripheral to the memory cell array. For example, Hollingsworth, supra, states that a bipolar coupling element provided with a 3100Å thick polysilicon antifuse will require only a 3.12 milliamp programming current. But, still lower programming voltages and currents, e.g., under ten volts and one milliamp, are desirable for the above reasons. Prior art programming voltages and currents for fuse, antifuse, and electrically-programmable read only memory (EPROM) memory cells, each exceed ten volts or one milliamp, or both.
A prior art memory cell comprises a bipolar transistor, a read line, a program line, and a fuse link. The fuse link is literally blown open by a mini-explosion that scatters debris all around the immediate vicinity. A buffer area is required to allow for such material loss without losing circuit functionality. This buffer zone tends to require large areas of chip real estate and devices using the memory cell are not as dense as they otherwise might be. Because such a large programming current is required to blow the fuse link, the transistor must be a bipolar type. MOS transistors are not practical. Large programming currents also mean that minimum sized transistors cannot be used. Thereby further reducing functional device density.
Orbach describes a prior art programmable gate array device in U.S. Pat. No. 4,924,287, issued May 8, 1990. The device comprises laser programmable gate array logic cells where the programmable element is conventional fuselink and the resultant logic function is very limited and cannot implement MPGA functions on a direct gate-to-gate basis.
It is therefore an object of the present invention to provide a silicon containing dielectric based antifuse structure for both electrical and laser programming.
It is a further object of the present invention to provide an antifuse that can be inserted between metals, metal to silicon, and metal to polysilicon.
It is a further object of the present invention to provide an antifuse element that uses a low temperature process under 450° C. and is therefore compatible with standard submicron CMOS/BiCMOS metal processes.
It is a further object of the present invention to provide an antifuse element that has a high OFF resistance above 100M ohm and is adjustable.
It is a further object of the present invention to provide an antifuse element that has a low ON resistance under 100 ohms with electrical programming and under ten ohms with laser programming.
It is a further object of the present invention to provide an antifuse element that has a low ON resistance under 100 ohms with electrical programming voltage scalable from 3V to 40V to suit various applications.
It is a further object of the present invention to provide an antifuse logic cell that allows direct gate-to-gate compatibility with standard mask-programmable gate array (MPGA) implementations.
It is a further objective of the present invention to provide an antifuse-based logic cell that allows one mask conversion to a mask-programmable gate array (MPGA).
Briefly, an integrated circuit of the present invention comprises antifuse elements which have been fabricated by depositing at under 450° C. an antifuse layer approximately 30 nanometers to 400 nanometers between layers of titanium (Ti), said antifuse layer comprising a stoichiometric or off-stoichiometric amorphous layer of silicon nitride (SiNx, where 0<×<1.4), or silicon-oxide (SiOx, where 0<×≦2), or silicon oxynitride (SiOx Ny, where 0<×<2 and 0<y<1.4), such that a heating of the said antifuse layer in excess of 500° C. by electrical or energy beam means will cause a chemical reduction reaction between the titanium and silicon-dioxide layers that yields more Ti5 Si3, TiSi, and/or TiSi2 than is yielded TiO, Ti2 O3, Ti3 O5, and/or TiO2, and such that there results a conductive compound between said titanium layers which constitutes a short circuit.
An advantage of the present invention is that it produces a memory cell and a programmable interconnect device that is fast and occupies a very small area of chip real estate.
Another advantage of the present invention is that it is compatible with standard submicron CMOS/BiCMOS metal processes.
Another advantage of the present invention is that it produces read transistors within memory cells that have high current drive that exceeds 300 microamps and has lower parasitics on the product term lines, resulting in higher device speeds.
Another advantage of the present invention is that it uses lower programming voltages and currents, and frees up space for more memory cells and more programmable interconnections on a given size chip.
Another advantage of the present invention is that fully processed wafers may be laser programmed, both before and after passivation.
Another advantage of the present invention is that a fully assembled die in a package with a windowed lid or without lid may be programmed with a laser or ion beam. Quick turnaround inventory is made practical thereby.
Another advantage of the present invention is that it allows very small metal-oxide semiconductor (MOS) programmable logic device (PLD) and PROM cell sizes.
Another advantage of the present invention is that no real estate is wasted in allowing for a buffer zone around the antifuse element for the damage caused by blasting fuses open during programming.
Another advantage of the present invention is that it allows an antifuse element to be inserted directly into a speed critical path.
Another advantage of the present invention is that very dense interconnect grids with high flexibility, high channel utilization and routing efficiency allow high gate count ASICs.
Another advantage of the present invention is that the lower fusing reaction temperatures required allow laser programming of devices without open windows on a device under test and without cracking any passivation layer.
Another advantage of the present invention is that it provides a programmable logic cell that allows direct gate-to-gate compatibility with standard mask-programmable gate array implementations.
These and many other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.
FIG. 1 is a schematic diagram of a basic antifuse cell with select transistor;
FIG. 2 is a cross-sectional view of an antifuse memory cell of the present invention;
FIG. 3 is a phase diagram of reactions between oxygen, silicon, and titanium;
FIG. 4 is a schematic diagram of a laser programmable gate array basic cell;
FIG. 5 is a schematic diagram of the laser programmable gate array basic cell of FIG. 4 with test transistors;
FIG. 6 is a schematic diagram of the laser programmable gate array basic cell of FIG. 4 with memory transistors;
FIG. 7 is a schematic diagram of a laser programmable gate array architecture; and
FIG. 8 is a schematic diagram of an alternative laser programmable gate array basic cell.
FIG. 1 is an antifuse memory cell, referred to by the general reference numeral 10, comprising an antifuse element 12, a read transistor 14, a program/read product term signal line 16, and an input term signal line 18. The input term signal line 18 will control the product term signal line 16 through transistor 14 if antifuse 12 has been programmed (to short circuit). In the exemplary embodiment of FIG. 1, memory cell 10 is programmed by placing ten volts on product term line 16 and five to ten volts on input term signal line 18. Transistor 14 turns on, placing a maximum voltage (10V) across antifuse element 12. This voltage will breakdown the dielectric in antifuse element 12 and cause a permanent short to appear. Read transistor 14 can thereafter control the product term signal line 16. The chip real estate needed to fabricate memory cell 10 is typically 30 μm2. This compares very favorably to the 130 μm2 required for the prior art two-transistor EPROM memory cell.
Memory cell 10 forms the basic memory unit of a memory array built in a matrix format. Matrices, like these, are very commonly used in ROMs and PROMs. Such an arrangement is conventional. See
Hamdy, et al. U.S. Pat. No. 4,899,205, issued Feb. 6, 1990, for a general background discussion of antifuse memory cells arranged in matrices (see FIG. 5a). (The antifuse element itself which is disclosed by Hamdy, et al., requires very high programming voltages and currents and is very different than that disclosed here.)
The present invention employs silicon containing dielectric, such as silicon dioxide or silicon nitride, layers deposited or plasma-enhanced chemical vapor deposited (PECVD) at a relatively low temperature (typically under 400° C., and without exception under 500° C.) which are deposited as antifuse material that is sandwiched between two titanium (Ti) or other refractory metal or metal silicide combinations. Conventional wisdom teaches away from depositing at under 500° C., one reason being to get uniform coverage (high step coverage ratios). But many advantages can be realized by keeping a relatively low processing temperature. And there are further significant advantages that result directly from non-uniform antifuse layer coverage (low step coverage ratios). For example, if the antifuse layer is deposited at less than 450° C., aluminum film may be deposited before an antifuse layer is deposited. Refractory metal or silicide serves as a diffusion barrier layer to prevent reaction between the amorphous layer and the metal layers during normal processing temperatures (under 450° C.). The choice of refractory metal is important because it has to be stable through normal processing temperatures (about 450° C.), but promote fusing at elevated temperatures (550°-650° C.). Preferably titanium, tantalum, titanium-tungsten, or other element/alloy is used as the refractory metal. Such materials enhance the fusing reaction during programming. At least one refractory metal layer is in contact with the dielectric layer(s), and can be above or below the antifuse layer.
FIG. 2 show a semiconductor device, referred to by the general reference numeral 20, after fabrication. Device 20, for example, could comprise memory cell 10, or any other similar device. Device 20 comprises a dielectric 22, a first conductor having a first (optional) metal layer 24 and a first refractory metal or metal silicide layer 26, a contact hole (via) opening 28 (alternatively called a "fuse via" by those skilled in the art), an antifuse layer 30, a second conductor having a second refractory metal or metal silicide layer 32 and a second (optional) metal layer 34. Using a preferred method of the present invention, device 20 is fabricated according to the following steps:
(1) using conventional processing up to the point after contact openings are made
(2) depositing a first metal layer 24 (if needed);
(3) depositing a layer 26 of titanium, or other refractory metal or metal silicide, thicker than 50 nanometers;
(4) masking and etching first metal;
(5) depositing dielectric 22 (and any necessary planarization steps);
(6) etching metal via contact openings 28;
(7) depositing 30 nanometers to 400 nanometers of an off-stoichiometric amorphous silicon-based dielectric layer at under 450° C. to form antifuse layer (the range is from approximately 0% excess silicon to 98% excess silicon in the dielectric layer);
(8) masking and etching antifuse layer 30;
(9) depositing a layer 32 of more than 50 nanometers of titanium or other refractory metal or metal silicide;
(10) depositing second metal layer 34 (if needed); and
(11) masking and etching the second metal layer 34 with conventional processing thereafter.
Steps 3, 7, 8, and 9 are improvements to otherwise conventional processing. Steps 8 and 9 may be swapped for one another. Only one masking and four process steps are needed to construct device 20 and its antifuse structure. Because the process is low temperature, under 450° C., the antifuse structure can be inserted between second and third layer metals. It can also be inserted between polysilicon/doped-silicon and first metal, as long as the polysilicon and/or doped-silicon has a silicide or refractory metal top layer formed either before or after contact hole formation. The above process is based on the reduction reaction between the refractory metal and the silicon-containing dielectric layer. At an elevated temperature, e.g., greater than 500° C., the dielectric layer will decompose in the presence of the refractory metal to form conductive silicides and other dielectrics. An example of this reaction is demonstrated in FIG. 3, showing titanium, silicon, and oxygen (Ti, Si, and O) in a ternary phase diagram. Two elements can co-exist in stable conditions along the tie-lines between the two element sides of the triangle. If two elements without a tie-line are brought into contact, there will be a tendency for them to react with one another to form other phases along the tie-line connection. The lack of a tie-line connection is the basic foundation for the antifuse structure of the present invention. There is no tie-line between Ti and SiO2. As a result, a system containing Ti and SiO2 will form TiSix and some TiOy. The silicide provides a low-resistance path for electrical conduction. The rate of the reaction is determined by the kinetics. For most reactions, higher temperatures usually means higher reaction rates. Therefore, even thin films, e.g., SiO2 and Ti, deposited at, e.g., 400° C., and later annealed at 425° C. (as in normal integrated circuit processing) will have a minimum reaction between these two elements due to the initial reaction barrier. At an elevated temperature, e.g., 500° C. and higher, the reaction rate can increase several orders of magnitude and will be completed from within a few nanoseconds to under a second. The reaction can be enhanced by adding more silicon into the dielectric film. The silicon rich film can be easily deposited by changing the gas flow ratio in standard plasma-enhanced chemical vapor deposition (CVD) systems. The dielectric based antifuse has a higher breakdown field than silicon based antifuse. The breakdown voltage can also be adjusted by changing the thickness of the dielectric film and/or silicon content. The dielectric-based antifuse has a much lower leakage current than typical silicon-based antifuse due to the much higher resistance of the dielectric layer. The breakdown field versus leakage current versus parasitic can be tailored/optimized by choosing the proper composition of the antifuse layer. This is not possible in many pure silicon-dioxide and pure silicon applications. Alternatives that accomplish the same dielectric characteristics here may include layer combinations to form the antifuse layer such as, oxide/silicon/oxide, silicon/oxide, or oxide/silicon or other multiple layer combinations. Here the oxide may be silicon dioxide (pure or off-stoichiometric) or titanium oxide formed by either CVD deposition, PECVD, sputtering, plasma ashing, wet chemical oxidation, or low temperature plasma oxidation. The oxide can also be replaced by silicon nitride (pure or off-stoichiometrics). Here the silicon nitride (pure or off-stoichiometric) may be deposited by CVD, sputtering, or PECVD. Similar reduction reactions also exist for Tantalum. Low-temperature deposited or sputtered antifuse takes advantage of the lower step coverage of the deposited layer to further reduce parasitic capacitance with a given programming voltage. The programming spot (point of reaction) is constrained to a small area along the bottom corner of the contact via hole and requires less programming current or energy means. This is consistent with faster programming. The programming voltage is related to the thickness of the antifuse layer 30 inside the fuse via opening 28. The thinner the layer 30, the lower the programming voltage. The parasitic capacitance, on the other hand, is reduced when layer 30 is made thicker. By restricting the cross-sectional area of the fuse, much lower programming currents are realized and minimum sized transistors can also be realized. (The transistor has to support enough current during programming to ensure fusing.) In the case of memory cell 10, transistor 14 can be made very small.
Controlling step coverage in the fabrication of memory cells is very important in controlling the magnitude of programming voltages needed to guarantee programming. (Step coverage is defined as the ratio between the thickness of a material deposited on a flat surface as compared to the thickness of that material deposited in vias or other contact openings.) Having a good step coverage (approaching 100%) is conventionally believed to promote consistently lower programming voltages and smaller memory cell geometries. One way used in the prior art to achieve good step coverage is higher deposition temperatures. Actually, as has been discovered by the present inventors, it is important in antifuse fabrication not to have a uniform film. However, the minimum thickness must occur and be tightly controlled in the bottom inside corners of the vias, as is discussed below. A problem posed by good step coverage (resulting in a uniform film), in the prior art, is that the programming current, programming voltage, and parasitic capacitance are all proportional to the thinnest spot on the film, which, in a uniform film, is everywhere. By allowing low step coverage ratios (coverage inside a via being thinner than outside the via), programming current, programming voltage, and parasitic capacitance vary independently. Of course, low programming current, low programming voltage, and low parasitic capacitance are normally conflicting goals balanced in a compromise controlled by how thick an antifuse layer is deposited.
An alternative method comprises adding an anti-reflection material over the top metal surface to allow more efficient absorption of a programming laser light beam. Anti-reflection materials include refractory metals and/or their silicides, amorphous silicon, and any other material less reflective than aluminum.
Another alternative method comprises heating up the substrate during programming from either the front side or backside of the substrate, the required programming energy can be reduced because the device is already near the reaction temperature.
Laser Programming--The prior art generally uses a laser beam to blow open special fuses or simple metal interconnects. Special windows have to be opened up in the dielectrics on the top and surrounding the fuse to allow a "blast area" and debris removal. Clearance between the fuse and active elements is required to avoid damage. For general background, laser programming of a read only memory is described by Redfern, et al., in U.S. Pat. No. 4,238,839, issued Dec. 9, 1980; and see, Boudou, et al. U.S. Pat. No. 4,893,167, issued Jan. 9, 1990; together with, Boudou, et al. U.S. Pat. No. 4,916,809, issued Apr. 17, 1990. Essentially, laser beam is such that antifuse elements are heated to spot temperatures greater than 550° C. More importantly, programming spots must reach a sufficient temperature to cause a fusing reaction between the antifuse layer and one of tungsten, titanium, or titanium-tungsten alloy in the refractory barrier layer. The antifuse element disclosed by Hamdy, et al., (supra) cannot be programmed by a laser because the fusing reaction does not solely rely on heat, the electrical programming current is a critical element. In contrast, memory cell 10 can be programmed both electrically and by a beam, such as a laser. The fusing reaction in the present invention relies principally on heat. Compared to conventional laser programming, which requires local temperatures of 900° C., or higher, the present invention requires spot temperatures of only 500°-800° C. and in all cases no higher than 900° C. This permits passivated devices to be programmed without danger of cracking the passivation due to deep internal thermal stresses. (The total volume change while programming an antifuse of the present invention is less than 100Å in any one direction, and is therefore easily absorbed.) The method described by Boudou, et al., supra, burns a hole through the passivation layer to fuse two conductors comprising TiW alloy film on aluminum.
The present invention presents an antifuse structure that can be programmed through an energy beam by locally heating up the programming elements (such as antifuses described above or other materials that exhibit a chemical reaction when heated above 500° C. to create a fusing connection. In the case of laser programming, the programming can be carried out either before or after topside passivation. No window opening is required. The wavelength, spot size and energy density are chosen such that the antifuse temperature will heat up to higher than 550° C. to trigger the fusing reaction between refractory metal/alloy and amorphous programming layers. Without substantially damaging the surrounding dielectrics. Pre-fabricated antifuse elements can be programmed while the device is in wafer form before or after topside passivation, in die form, in unlidded package form, or in a package with a windowed lid.
FIG. 4 shows a preferred embodiment of a basic cell having direct gate-to-gate functional compatibility with standard masked programmable gate array (MPGA) implantations. The basic cell comprises four MOS transistors M1-M4, two power lines Vcc and GND, two inputs A and B, and up to three outputs X, Y, and Z. (X is the primary output, Y is the secondary output, and Z is the tertiary output). Up to sixteen antifuses L1-L16 allow the basic cell to be programmed in a variety of configurations. Output Z can have several variations that yield equivalent functionalities: either L15 or L16 can be hardwired (direct short), or L15 and L16 can be placed between output Z and the left side drain of transistor M1 and output Z and the right side drain of transistor M4, respectively. Table I lists the connections needed to implement various MPGA basic functions for one basic cell. Table II applies to two basic cells. Direct one-to-one correspondence to MPGA implementations are demonstrated in all these functions. Not shown, but having an identical implementation as an MPGA are EXCLUSIVE-NOR, EXCLUSIVE-OR, PASSGATE, LATCHES, and FLIP-FLOPS.
TABLE I______________________________________Output Shorted Antifuses______________________________________1 X = A * B L1,L3,L7,L9,L42 X = A + B L1,L8,L10,L4,L63 X = (A = B) L1,L3,L7,L8,L4,L64 X = B L2,L9,L10,L11,L12,L5 Y = A5 MUX:X = OUT L7,L8,L11,L13,L15,L16 A = S1, B = S2 Y = IN1 Z = IN2______________________________________
TABLE II______________________________________Output CELL 1 CELL 2______________________________________1 X2 = (A1 * B1 * A2 * B2) L1,L3,L7,L4, L1,L3,L7,L9, X2 = X1, Y2 = Y1 L13 L122 X2 = (A1 + B1 + A2 + B2) L1,L8,L4,L6, L8,L10,L4,L6 X2 = X1, Y2 = Y1 L14 L113 AOI L1,L3,L7, L11,L14,L7, X2 = (A1 * B1 + A2 * B2) L13,L4 L9,L4 Y2 = X1, X2 = Y1______________________________________
FIG. 5 illustrates an enhanced version of the basic cell of FIG. 4. It consists of the basic cell plus two additional transistors M5 and M6. (One and three additional transistors are also other possible alternatives.). The transistors make it possible to observe the outputs (X, Y, or Z) of each basic cell during testing after cell programming. The direction of DSEL and Dx and Dy can be reversed.
FIG. 6 shows an alternative embodiment of the basic cell of FIG. 4 having two additional data transfer transistors M7 and M8. (More or less transistors are also possible.) Transistors M7 and M8 allow memory implementations (single-port RAM, dual-port RAM or ROM). When the basic cell is not configured as a memory element, both word-line (WL) and bit-lines (BL and BL) are used as normal interconnect tracks. The directions of WL and BL can be reversed. It is also possible to combine both testing and memory transistors with the basic cell to form other useful embodiments.
FIG. 7 diagrams one way the basic cells (e.g., FIG. 4) can be arranged in an array compatible with laser programming. (The directions, horizontal and vertical are arbitrarily assigned.) Face-to-face rows have input/output lines that share the same set of horizontal tracks for improved routing accessibility and efficiency. Primary output lines X extend to neighboring rows (at least accessible by four rows of basic cells), also for improved routing accessibility and efficiency. Segmented and offset tracks (not shown) in both the horizontal and vertical directions improve utilization and routing efficiency. These segments are connected end-to-end through an antifuse at each breakpoint. The breakpoint at parallel tracks are offset by multiples of the basic cell's dimensions. In a typical configurable/programmable IC with pre-fabricated laser-programmable antifuse elements, the wafers are first fully processed. The user specifies the desired function/logic through netlist, schematics, or logic diagram input. The laser programming system then converts the input into a set of appropriate interconnects that implement the desired functions. The interconnect routing is then converted into a set of antifuse locations to be connected, and the laser is driven to the X-Y locations for programming.
FIG. 8 is an alternative embodiment of the basic cell of FIG. 4. Input (A-B) and output (C-H) lines connected at various points to the four MOS transistors M1-M4 are orthogonal (in their physical layout on a programmable gate array implementation) to transfer lines X, Y, and Z. Antifuses L1-L16 can be programmed such that complex logic combinations can be realized, and such that higher complexity logic functions can be had by utilizing the transfer lines and input.
Preferably, the antifuse elements above comprise elements that have been fabricated by depositing, at under 500° C., an antifuse layer that is approximately 30 nanometers to 400 nanometers thick and lies between layers of titanium, said antifuse layer has a stoichiometric or off-stoichiometric amorphous silicon-based dielectric layer, the elements such that a heating of the said antifuse layer in excess of 500° C. by electrical or energy beam means will cause a chemical reduction reaction between the titanium and silicon-dioxide layers that yields more Ti5 Si3, TiSi, and/or TiSi2 than is yielded TiO, Ti2 O3, Ti3 O5, and/or TiO2, and such that there results a conductive compound between said titanium layers which substantially constitutes a short circuit.
Although the present invention has been described in terms of the presently preferred embodiments, it is to be understood that the disclosure is not to be interpreted as limiting. Various alterations and modifications will no doubt become apparent to those skilled in the art after having read the above disclosure. Accordingly, it is intended that the appended claims be interpreted as covering all alterations and modifications as fall within the true spirit and scope of the invention.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4238839 *||Apr 19, 1979||Dec 9, 1980||National Semiconductor Corporation||Laser programmable read only memory|
|US4399372 *||Dec 8, 1980||Aug 16, 1983||Nippon Telegraph And Telephone Public Corporation||Integrated circuit having spare parts activated by a high-to-low adjustable resistance device|
|US4420820 *||Mar 30, 1983||Dec 13, 1983||Signetics Corporation||Programmable read-only memory|
|US4455495 *||Oct 1, 1980||Jun 19, 1984||Hitachi, Ltd.||Programmable semiconductor integrated circuitry including a programming semiconductor element|
|US4507756 *||Mar 23, 1982||Mar 26, 1985||Texas Instruments Incorporated||Avalanche fuse element as programmable device|
|US4507757 *||Mar 23, 1982||Mar 26, 1985||Texas Instruments Incorporated||Avalanche fuse element in programmable memory|
|US4565712 *||May 23, 1984||Jan 21, 1986||Tokyo Shibaura Denki Kabushiki Kaisha||Method of making a semiconductor read only memory|
|US4569120 *||Mar 7, 1983||Feb 11, 1986||Signetics Corporation||Method of fabricating a programmable read-only memory cell incorporating an antifuse utilizing ion implantation|
|US4569121 *||Mar 7, 1983||Feb 11, 1986||Signetics Corporation||Method of fabricating a programmable read-only memory cell incorporating an antifuse utilizing deposition of amorphous semiconductor layer|
|US4585490 *||Oct 3, 1984||Apr 29, 1986||Massachusetts Institute Of Technology||Method of making a conductive path in multi-layer metal structures by low power laser beam|
|US4590589 *||Dec 21, 1982||May 20, 1986||Zoran Corporation||Electrically programmable read only memory|
|US4678889 *||Nov 6, 1985||Jul 7, 1987||Nec Corporation||Method of laser trimming in semiconductor wafer|
|US4721868 *||Sep 23, 1986||Jan 26, 1988||Advanced Micro Devices, Inc.||IC input circuitry programmable for realizing multiple functions from a single input|
|US4748490 *||Apr 13, 1988||May 31, 1988||Texas Instruments Incorporated||Deep polysilicon emitter antifuse memory cell|
|US4786904 *||Dec 15, 1986||Nov 22, 1988||Zoran Corporation||Electronically programmable gate array having programmable interconnect lines|
|US4792835 *||Dec 5, 1986||Dec 20, 1988||Texas Instruments Incorporated||MOS programmable memories using a metal fuse link and process for making the same|
|US4796074 *||Apr 27, 1987||Jan 3, 1989||Instant Circuit Corporation||Method of fabricating a high density masked programmable read-only memory|
|US4823181 *||May 9, 1986||Apr 18, 1989||Actel Corporation||Programmable low impedance anti-fuse element|
|US4839864 *||Mar 2, 1988||Jun 13, 1989||Mitsubishi Denki Kabushiki Kaisha||Semiconductor memory device comprising programmable redundancy circuit|
|US4847732 *||Jun 8, 1988||Jul 11, 1989||Mosaic Systems, Inc.||Wafer and method of making same|
|US4876220 *||Nov 13, 1987||Oct 24, 1989||Actel Corporation||Method of making programmable low impedance interconnect diode element|
|US4881114 *||May 16, 1986||Nov 14, 1989||Actel Corporation||Selectively formable vertical diode circuit element|
|US4882611 *||Jul 21, 1988||Nov 21, 1989||Zoran Corporation||Double layer voltage-programmable device and method of manufacturing same|
|US4893167 *||Mar 2, 1989||Jan 9, 1990||Pull S.A.||Method for programmable laser connection of two superimposed conductors of the interconnect system of an integrated circuit|
|US4897836 *||Oct 20, 1987||Jan 30, 1990||Gazelle Microcircuits, Inc.||Programmable connection path circuit|
|US4899205 *||Dec 28, 1987||Feb 6, 1990||Actel Corporation||Electrically-programmable low-impedance anti-fuse element|
|US4910418 *||Dec 29, 1988||Mar 20, 1990||Gazelle Microcircuits, Inc.||Semiconductor fuse programmable array structure|
|US4914055 *||Aug 24, 1989||Apr 3, 1990||Advanced Micro Devices, Inc.||Semiconductor antifuse structure and method|
|US4916809 *||Aug 17, 1988||Apr 17, 1990||Bull S.A.||Method for programmable laser connection of two superimposed conductors of the interconnect system of an integrated circuit|
|US4924287 *||Dec 18, 1989||May 8, 1990||Avner Pdahtzur||Personalizable CMOS gate array device and technique|
|US4937475 *||Sep 19, 1988||Jun 26, 1990||Massachusetts Institute Of Technology||Laser programmable integrated circuit|
|US5099149 *||Dec 19, 1990||Mar 24, 1992||At&T Bell Laboratories||Programmable integrated circuit|
|1||Gullette et al, "Laser Personalization of NMOS Digital Topologies", 1983 IEEE Int'l Symposium on Circuits and Systems, Newport Beach, Calif. May 2-4, 1983, pp. 1249-1252.|
|2||*||Gullette et al, Laser Personalization of NMOS Digital Topologies , 1983 IEEE Int l Symposium on Circuits and Systems, Newport Beach, Calif. May 2 4, 1983, pp. 1249 1252.|
|3||Ron Iscoff, "Characterizing Quickturn ASICs: . . . ", Semiconductor International, Aug. 1990, pp. 68-73.|
|4||*||Ron Iscoff, Characterizing Quickturn ASICs: . . . , Semiconductor International , Aug. 1990, pp. 68 73.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US5235221 *||Apr 8, 1992||Aug 10, 1993||Micron Technology, Inc.||Field programmable logic array with speed optimized architecture|
|US5248632 *||Sep 29, 1992||Sep 28, 1993||Texas Instruments Incorporated||Method of forming an antifuse|
|US5270251 *||Feb 25, 1993||Dec 14, 1993||Massachusetts Institute Of Technology||Incoherent radiation regulated voltage programmable link|
|US5287017 *||May 15, 1992||Feb 15, 1994||Micron Technology, Inc.||Programmable logic device macrocell with two OR array inputs|
|US5293133 *||Aug 27, 1992||Mar 8, 1994||Quicklogic Corporation||Method of determining an electrical characteristic of an antifuse and apparatus therefor|
|US5298803 *||Jul 15, 1992||Mar 29, 1994||Micron Semiconductor, Inc.||Programmable logic device having low power microcells with selectable registered and combinatorial output signals|
|US5300456 *||Jun 17, 1993||Apr 5, 1994||Texas Instruments Incorporated||Metal-to-metal antifuse structure|
|US5300830 *||May 15, 1992||Apr 5, 1994||Micron Semiconductor, Inc.||Programmable logic device macrocell with an exclusive feedback and exclusive external input lines for registered and combinatorial modes using a dedicated product term for control|
|US5308795 *||Nov 4, 1992||May 3, 1994||Actel Corporation||Above via metal-to-metal antifuse|
|US5313119 *||Oct 28, 1991||May 17, 1994||Crosspoint Solutions, Inc.||Field programmable gate array|
|US5323033 *||Aug 4, 1992||Jun 21, 1994||Hitachi, Ltd.||Single chip IC device having gate array or memory with gate array and provided with redundancy capability|
|US5327024 *||Jul 2, 1992||Jul 5, 1994||Quicklogic Corporation||Field programmable antifuse device and programming method therefor|
|US5331227 *||Dec 13, 1993||Jul 19, 1994||Micron Semiconductor, Inc.||Programmable logic device macrocell with an exclusive feedback line and an exclusive external input line|
|US5369054 *||Jul 7, 1993||Nov 29, 1994||Actel Corporation||Circuits for ESD protection of metal-to-metal antifuses during processing|
|US5373169 *||Dec 17, 1992||Dec 13, 1994||Actel Corporation||Low-temperature process metal-to-metal antifuse employing silicon link|
|US5374832 *||Aug 25, 1993||Dec 20, 1994||Texas Instruments Incorporated||Antifuse having TiW oxide film between two metal layers|
|US5384500 *||Dec 22, 1993||Jan 24, 1995||Micron Semiconductor, Inc.||Programmable logic device macrocell with an exclusive feedback and an exclusive external input line for a combinatorial mode and accommodating two separate programmable or planes|
|US5394032 *||Feb 10, 1993||Feb 28, 1995||Robert Bosch Gmbh||Programming details of a programmable circuit|
|US5394103 *||Feb 24, 1994||Feb 28, 1995||Crosspoint Solutions, Inc.||Field programmable gate array|
|US5395797 *||Nov 12, 1993||Mar 7, 1995||Texas Instruments Incorporated||Antifuse structure and method of fabrication|
|US5403778 *||Jan 6, 1994||Apr 4, 1995||Texas Instruments Incorporated||Limited metal reaction for contact cleaning and improved metal-to-metal antifuse contact cleaning method|
|US5412593 *||Jan 12, 1994||May 2, 1995||Texas Instruments Incorporated||Fuse and antifuse reprogrammable link for integrated circuits|
|US5434448 *||Sep 16, 1994||Jul 18, 1995||Sgs-Thomson Microelectronics, Inc.||Programmable contact structure|
|US5447880 *||Apr 5, 1994||Sep 5, 1995||At&T Global Information Solutions Company||Method for forming an amorphous silicon programmable element|
|US5449947 *||Jul 7, 1993||Sep 12, 1995||Actel Corporation||Read-disturb tolerant metal-to-metal antifuse and fabrication method|
|US5464790 *||Jul 28, 1994||Nov 7, 1995||Actel Corporation||Method of fabricating an antifuse element having an etch-stop dielectric layer|
|US5465055 *||Oct 19, 1994||Nov 7, 1995||Crosspoint Solutions, Inc.||RAM-logic tile for field programmable gate arrays|
|US5466617 *||Jun 15, 1994||Nov 14, 1995||U.S. Philips Corporation||Manufacturing electronic devices comprising TFTs and MIMs|
|US5469077 *||Jun 22, 1994||Nov 21, 1995||Quicklogic Corporation||Field programmable antifuse device and programming method therefor|
|US5472901 *||Dec 2, 1994||Dec 5, 1995||Lsi Logic Corporation||Process for formation of vias (or contact openings) and fuses in the same insulation layer with minimal additional steps|
|US5482884 *||Aug 9, 1994||Jan 9, 1996||Actel Corporation||Low-temperature process metal-to-metal antifuse employing silicon link|
|US5485031 *||Nov 22, 1993||Jan 16, 1996||Actel Corporation||Antifuse structure suitable for VLSI application|
|US5493144 *||Jun 10, 1994||Feb 20, 1996||Sgs-Thomson Microelectronics, Inc.||Field progammable device with contact openings|
|US5495181 *||Dec 1, 1994||Feb 27, 1996||Quicklogic Corporation||Integrated circuit facilitating simultaneous programming of multiple antifuses|
|US5498895 *||Aug 12, 1994||Mar 12, 1996||Actel Corporation||Process ESD protection devices for use with antifuses|
|US5502000 *||May 8, 1995||Mar 26, 1996||Xilinx, Inc.||Method of forming a antifuse structure with increased breakdown at edges|
|US5506518 *||Sep 20, 1994||Apr 9, 1996||Xilinx, Inc.||Antifuse-based programmable logic circuit|
|US5508220 *||Jun 1, 1993||Apr 16, 1996||Actel Corporation||Method of forming antifuses having minimum areas|
|US5510646 *||Jun 10, 1993||Apr 23, 1996||Actel Corporation||Metal-to-metal antifuse with improved diffusion barrier layer|
|US5519248 *||Jul 19, 1994||May 21, 1996||Actel Corporation||Circuits for ESD protection of metal-to-metal antifuses during processing|
|US5521423 *||Apr 15, 1994||May 28, 1996||Kawasaki Steel Corporation||Dielectric structure for anti-fuse programming element|
|US5525830 *||Oct 12, 1994||Jun 11, 1996||Actel Corporation||Metal-to-metal antifuse including etch stop layer|
|US5537108 *||Oct 7, 1994||Jul 16, 1996||Prolinx Labs Corporation||Method and structure for programming fuses|
|US5541441 *||Oct 6, 1994||Jul 30, 1996||Actel Corporation||Metal to metal antifuse|
|US5543656 *||Oct 24, 1994||Aug 6, 1996||Actel Corporation||Metal to metal antifuse|
|US5544070 *||Aug 27, 1992||Aug 6, 1996||Quicklogic Corporation||Programmed programmable device and method for programming antifuses of a programmable device|
|US5550400 *||Jul 5, 1994||Aug 27, 1996||Kabushiki Kaisha Toshiba||Semiconductor device equipped with antifuse elements and a method for manufacturing an FPGA|
|US5550404 *||Aug 10, 1994||Aug 27, 1996||Actel Corporation||Electrically programmable antifuse having stair aperture|
|US5552627 *||Apr 22, 1994||Sep 3, 1996||Actel Corporation||Electrically programmable antifuse incorporating dielectric and amorphous silicon interlayers|
|US5552720 *||Dec 1, 1994||Sep 3, 1996||Quicklogic Corporation||Method for simultaneous programming of multiple antifuses|
|US5565702 *||Dec 5, 1994||Oct 15, 1996||Kawasaki Steel Corporation||Antifuse element, semiconductor device having antifuse elements, and method for manufacturing the same|
|US5572050 *||Dec 6, 1994||Nov 5, 1996||Massachusetts Institute Of Technology||Fuse-triggered antifuse|
|US5572061 *||Aug 12, 1994||Nov 5, 1996||Actel Corporation||ESD protection device for antifuses with top polysilicon electrode|
|US5572062 *||Mar 31, 1994||Nov 5, 1996||Crosspoint Solutions, Inc.||Antifuse with silicon spacers|
|US5572409 *||Oct 7, 1994||Nov 5, 1996||Prolinx Labs Corporation||Apparatus including a programmable socket adapter for coupling an electronic component to a component socket on a printed circuit board|
|US5576576 *||Jan 24, 1995||Nov 19, 1996||Actel Corporation||Above via metal-to-metal antifuse|
|US5578836 *||Nov 14, 1994||Nov 26, 1996||Actel Corporation||Electrically programmable antifuse element|
|US5585602 *||Jan 9, 1995||Dec 17, 1996||Massachusetts Institute Of Technology||Structure for providing conductive paths|
|US5592016 *||Apr 14, 1995||Jan 7, 1997||Actel Corporation||Antifuse with improved antifuse material|
|US5593920 *||Apr 12, 1994||Jan 14, 1997||Sgs-Thomson Microelectronics, Inc.||Method for forming contact structures in integrated circuits|
|US5600262 *||Oct 11, 1995||Feb 4, 1997||Quicklogic Corporation||Integrated circuit facilitating simultaneous programming of multiple antifuses|
|US5610534 *||May 18, 1995||Mar 11, 1997||Actel Corporation||Logic module for a programmable logic device|
|US5614756 *||Aug 1, 1994||Mar 25, 1997||Actel Corporation||Metal-to-metal antifuse with conductive|
|US5619063 *||Dec 12, 1995||Apr 8, 1997||Actel Corporation||Edgeless, self-aligned, differential oxidation enhanced and difusion-controlled minimum-geometry antifuse and method of fabrication|
|US5625220 *||Aug 8, 1994||Apr 29, 1997||Texas Instruments Incorporated||Sublithographic antifuse|
|US5629227 *||Apr 18, 1995||May 13, 1997||Actel Corporation||Process of making ESD protection devices for use with antifuses|
|US5629636 *||Aug 1, 1995||May 13, 1997||Crosspoint Solutions, Inc.||Ram-logic tile for field programmable gate arrays|
|US5633189 *||Apr 18, 1995||May 27, 1997||Actel Corporation||Method of making metal to metal antifuse|
|US5639684 *||Jun 7, 1995||Jun 17, 1997||Texas Instruments Incorporated||Method of making a low capacitance antifuse having a pillar located between the first and second metal layers|
|US5641703 *||Apr 28, 1995||Jun 24, 1997||Massachusetts Institute Of Technology||Voltage programmable links for integrated circuits|
|US5641985 *||Dec 5, 1994||Jun 24, 1997||Kawasaki Steel Corporation||Antifuse element and semiconductor device having antifuse elements|
|US5656534 *||Feb 27, 1996||Aug 12, 1997||Actel Corporation||Method for forming an ESD protection device for antifuses with top polysilicon electrode|
|US5658819 *||Nov 1, 1995||Aug 19, 1997||United Technologies Corporation||Antifuse structure and process for manufacturing the same|
|US5663091 *||May 9, 1996||Sep 2, 1997||Actel Corporation||Method for fabricating an electrically programmable antifuse|
|US5663590 *||Jul 31, 1996||Sep 2, 1997||Lsi Logic Corporation||Product of process for formation of vias (or contact openings) and fuses in the same insulation layer with minimal additional steps|
|US5663591 *||Feb 14, 1995||Sep 2, 1997||Crosspoint Solutions, Inc.||Antifuse with double via, spacer-defined contact|
|US5670818 *||Aug 16, 1994||Sep 23, 1997||Actel Corporation||Electrically programmable antifuse|
|US5693556 *||Dec 29, 1995||Dec 2, 1997||Cypress Semiconductor Corp.||Method of making an antifuse metal post structure|
|US5726482||Oct 7, 1994||Mar 10, 1998||Prolinx Labs Corporation||Device-under-test card for a burn-in board|
|US5741720 *||Oct 4, 1995||Apr 21, 1998||Actel Corporation||Method of programming an improved metal-to-metal via-type antifuse|
|US5753528 *||Nov 7, 1995||May 19, 1998||Actel Corporation||Method of fabricating metal-to-metal antifuse with improved diffusion barrier layer|
|US5759876 *||Nov 1, 1995||Jun 2, 1998||United Technologies Corporation||Method of making an antifuse structure using a metal cap layer|
|US5763299 *||Mar 12, 1996||Jun 9, 1998||Actel Corporation||Reduced leakage antifuse fabrication method|
|US5763898 *||Oct 3, 1996||Jun 9, 1998||Actel Corporation||Above via metal-to-metal antifuses incorporating a tungsten via plug|
|US5767575||Oct 17, 1995||Jun 16, 1998||Prolinx Labs Corporation||Ball grid array structure and method for packaging an integrated circuit chip|
|US5770885 *||Apr 11, 1996||Jun 23, 1998||Actel Corporation||Electrically programmable antifuse incorporating dielectric and amorphous silicon interlayers|
|US5780323 *||Nov 12, 1996||Jul 14, 1998||Actel Corporation||Fabrication method for metal-to-metal antifuses incorporating a tungsten via plug|
|US5789764 *||Nov 7, 1996||Aug 4, 1998||Actel Corporation||Antifuse with improved antifuse material|
|US5804500 *||Jun 4, 1996||Sep 8, 1998||Actel Corporation||Fabrication process for raised tungsten plug antifuse|
|US5808351||Oct 7, 1994||Sep 15, 1998||Prolinx Labs Corporation||Programmable/reprogramable structure using fuses and antifuses|
|US5813881 *||Oct 7, 1994||Sep 29, 1998||Prolinx Labs Corporation||Programmable cable and cable adapter using fuses and antifuses|
|US5825072 *||Feb 14, 1996||Oct 20, 1998||Actel Corporation||Circuits for ESD Protection of metal to-metal antifuses during processing|
|US5834824||Mar 14, 1995||Nov 10, 1998||Prolinx Labs Corporation||Use of conductive particles in a nonconductive body as an integrated circuit antifuse|
|US5840627 *||Mar 24, 1997||Nov 24, 1998||Clear Logic, Inc.||Method of customizing integrated circuits using standard masks and targeting energy beams for single resist development|
|US5844297 *||Sep 26, 1995||Dec 1, 1998||Symbios, Inc.||Antifuse device for use on a field programmable interconnect chip|
|US5856233 *||May 3, 1995||Jan 5, 1999||Stmicroelectronics, Inc.||Method of forming a field programmable device|
|US5856234 *||Jul 11, 1995||Jan 5, 1999||Actel Corporation||Method of fabricating an antifuse|
|US5859562 *||Dec 24, 1996||Jan 12, 1999||Actel Corporation||Programming circuit for antifuses using bipolar and SCR devices|
|US5861325 *||Mar 10, 1994||Jan 19, 1999||Massachusetts Institute Of Technology||Technique for producing interconnecting conductive links|
|US5866938 *||Aug 15, 1996||Feb 2, 1999||Kabushiki Kaisha Toshiba||Semiconductor device equipped with antifuse elements and a method for manufacturing an FPGA|
|US5872338||Apr 10, 1996||Feb 16, 1999||Prolinx Labs Corporation||Multilayer board having insulating isolation rings|
|US5885749 *||Jun 20, 1997||Mar 23, 1999||Clear Logic, Inc.||Method of customizing integrated circuits by selective secondary deposition of layer interconnect material|
|US5906042||Oct 4, 1995||May 25, 1999||Prolinx Labs Corporation||Method and structure to interconnect traces of two conductive layers in a printed circuit board|
|US5906043||Jun 30, 1997||May 25, 1999||Prolinx Labs Corporation||Programmable/reprogrammable structure using fuses and antifuses|
|US5913137 *||Oct 1, 1996||Jun 15, 1999||Actel Corporation||Process ESD protection devices for use with antifuses|
|US5917229||Jul 29, 1996||Jun 29, 1999||Prolinx Labs Corporation||Programmable/reprogrammable printed circuit board using fuse and/or antifuse as interconnect|
|US5920109 *||Dec 23, 1996||Jul 6, 1999||Actel Corporation||Raised tungsten plug antifuse and fabrication processes|
|US5920110 *||Apr 30, 1998||Jul 6, 1999||Lsi Logic Corporation||Antifuse device for use on a field programmable interconnect chip|
|US5920771 *||Mar 17, 1997||Jul 6, 1999||Gennum Corporation||Method of making antifuse based on silicided single polysilicon bipolar transistor|
|US5920789 *||Mar 9, 1995||Jul 6, 1999||Massachusetts Institute Of Technology||Technique for producing interconnecting conductive links|
|US5936297 *||Mar 24, 1997||Aug 10, 1999||Lg Semicon Co., Ltd.||Programmable semiconductor element having an antifuse structure|
|US5940727 *||Oct 11, 1994||Aug 17, 1999||Massachusetts Institute Of Technology||Technique for producing interconnecting conductive links|
|US5953577 *||Sep 29, 1998||Sep 14, 1999||Clear Logic, Inc.||Customization of integrated circuits|
|US5962815||Jan 18, 1995||Oct 5, 1999||Prolinx Labs Corporation||Antifuse interconnect between two conducting layers of a printed circuit board|
|US5962910 *||Jul 17, 1997||Oct 5, 1999||Actel Corporation||Metal-to-metal via-type antifuse|
|US5985518 *||Mar 24, 1997||Nov 16, 1999||Clear Logic, Inc.||Method of customizing integrated circuits using standard masks and targeting energy beams|
|US5986322 *||Jun 6, 1995||Nov 16, 1999||Mccollum; John L.||Reduced leakage antifuse structure|
|US5987744||Jul 1, 1997||Nov 23, 1999||Prolinx Labs Corporation||Method for supporting one or more electronic components|
|US5989783 *||Mar 12, 1998||Nov 23, 1999||Clear Logic, Inc.||Method of customizing integrated circuits by depositing two resist layers to selectively pattern layer interconnect material|
|US6001693 *||Sep 1, 1995||Dec 14, 1999||Yeouchung; Yen||Method of making a metal to metal antifuse|
|US6034427||Jan 28, 1998||Mar 7, 2000||Prolinx Labs Corporation||Ball grid array structure and method for packaging an integrated circuit chip|
|US6051511 *||Jul 31, 1997||Apr 18, 2000||Micron Technology, Inc.||Method and apparatus for reducing isolation stress in integrated circuits|
|US6060330 *||Apr 25, 1997||May 9, 2000||Clear Logic, Inc.||Method of customizing integrated circuits by selective secondary deposition of interconnect material|
|US6111302 *||Aug 30, 1995||Aug 29, 2000||Actel Corporation||Antifuse structure suitable for VLSI application|
|US6124193 *||Apr 17, 1998||Sep 26, 2000||Actel Corporation||Raised tungsten plug antifuse and fabrication processes|
|US6150705 *||Dec 13, 1995||Nov 21, 2000||Actel Corporation||Dielectric-polysilicon-dielectric-polysilicon-dielectric antifuse for field programmable logic application|
|US6159836 *||May 8, 1995||Dec 12, 2000||Stmicroelectronics, Inc.||Method for forming programmable contact structure|
|US6160420||Nov 12, 1996||Dec 12, 2000||Actel Corporation||Programmable interconnect architecture|
|US6171512||Jun 7, 1995||Jan 9, 2001||Canon Kabushiki Kaisha||Etching solution for etching porous silicon, etching method using the etching solution and method of preparing semiconductor member using the etching solution|
|US6177714||Feb 13, 1998||Jan 23, 2001||Nec Corporation||Semiconductor device having a fuse of the laser make-link programming type|
|US6191486||Apr 2, 1999||Feb 20, 2001||Massachusetts Institute Of Technology||Technique for producing interconnecting conductive links|
|US6219819 *||Jun 26, 1998||Apr 17, 2001||Xilinx, Inc.||Method for verifying timing in a hard-wired IC device modeled from an FPGA|
|US6396120 *||Mar 17, 2000||May 28, 2002||International Business Machines Corporation||Silicon anti-fuse structures, bulk and silicon on insulator fabrication methods and application|
|US6492206||Dec 12, 2000||Dec 10, 2002||Actel Corporation||Antifuse with improved radiation SEDR|
|US6541363 *||Oct 31, 1998||Apr 1, 2003||Guobiao Zhang||Antifuse manufacturing process|
|US6541868||Dec 8, 2000||Apr 1, 2003||Massachusetts Institute Of Technology||Interconnecting conductive links|
|US6544897 *||Oct 26, 2001||Apr 8, 2003||Seiko Instruments Inc.||Method for forming a vertical edge submicron through-hole and a thin film sample with this kind of through-hole|
|US6602798||Mar 2, 2000||Aug 5, 2003||Micron Technology, Inc.||Method and apparatus for reducing isolation stress in integrated circuits|
|US6625788||Dec 19, 2000||Sep 23, 2003||Xilinx, Inc.||Method for verifying timing in a hard-wired IC device modeled from an FPGA|
|US6633506||Jan 29, 2001||Oct 14, 2003||Micron Technology, Inc.||Antifuse detection circuit|
|US6703690||Jul 2, 2002||Mar 9, 2004||Micron Technology, Inc.||Apparatus for reducing isolation stress in integrated circuits|
|US6853049 *||Mar 13, 2002||Feb 8, 2005||Matrix Semiconductor, Inc.||Silicide-silicon oxide-semiconductor antifuse device and method of making|
|US7109071||Dec 8, 2003||Sep 19, 2006||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor device and manufacturing method thereof|
|US7329565||Nov 12, 2004||Feb 12, 2008||Sanddisk 3D Llc||Silicide-silicon oxide-semiconductor antifuse device and method of making|
|US7368318||Sep 16, 2005||May 6, 2008||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor device and method for manufacturing the same, and electric appliance|
|US7408193||Sep 8, 2006||Aug 5, 2008||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor device and manufacturing method thereof|
|US7422935||Sep 16, 2005||Sep 9, 2008||Semiconductor Energy Laboratory Co., Ltd.||Method for manufacturing semiconductor device, and semiconductor device and electronic device|
|US7456426 *||Oct 8, 2004||Nov 25, 2008||International Business Machines Corporation||Fin-type antifuse|
|US7485511||May 25, 2006||Feb 3, 2009||Semiconductor Energy Laboratory Co., Ltd.||Integrated circuit device and method for manufacturing integrated circuit device|
|US7642555||Jan 5, 2010||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor device|
|US7655509||Sep 13, 2007||Feb 2, 2010||Sandisk 3D Llc||Silicide-silicon oxide-semiconductor antifuse device and method of making|
|US7691684||Apr 6, 2010||International Business Machines Corporation||Fin-type antifuse|
|US7727857||Oct 27, 2006||Jun 1, 2010||Semiconductor Energy Laboratory Co., Ltd||Manufacturing method of semiconductor device|
|US7728332||Aug 27, 2008||Jun 1, 2010||Semiconductor Energy Laboratory Co., Ltd||Method for manufacturing semiconductor device, and semiconductor device and electronic device|
|US7736964||Nov 16, 2005||Jun 15, 2010||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor device, and method for manufacturing the same|
|US7816685||Oct 19, 2010||Semiconductor Energy Laboratory Co., Ltd.||Integrated circuit device and method for manufacturing integrated circuit device|
|US7863188||Jul 14, 2006||Jan 4, 2011||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor device and manufacturing method thereof|
|US7915095||Jan 13, 2010||Mar 29, 2011||Sandisk 3D Llc||Silicide-silicon oxide-semiconductor antifuse device and method of making|
|US7977669||Feb 7, 2006||Jul 12, 2011||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor memory device having a liquid-repellent layer|
|US8030736||Oct 4, 2011||International Business Machines Corporation||Fin anti-fuse with reduced programming voltage|
|US8120034||Oct 12, 2010||Feb 21, 2012||Semiconductor Energy Laboratory Co., Ltd.||Integrated circuit device and method for manufacturing integrated circuit device|
|US8168512||May 1, 2012||Semiconductor Energy Laboratory Co., Ltd.||Manufacturing method of semiconductor device|
|US8242486||Feb 7, 2006||Aug 14, 2012||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor device with liquid repellant layer|
|US8362485||Dec 1, 2011||Jan 29, 2013||Semiconductor Energy Laboratory Co., Ltd.||Integrated circuit device and method for manufacturing integrated circuit device|
|US8370800||Jun 3, 2008||Feb 5, 2013||International Business Machines Corporation||Determining application distribution based on application state tracking information|
|US8381205 *||Jun 3, 2008||Feb 19, 2013||International Business Machines Corporation||Co-resident software performance tracking|
|US8429585 *||Apr 23, 2013||Raminda Udaya Madurawe||Three dimensional integrated circuits|
|US8546210||Jun 4, 2010||Oct 1, 2013||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor device and method for manufacturing the same|
|US8557699||Dec 17, 2010||Oct 15, 2013||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor device and manufacturing method thereof|
|US8643162||Nov 19, 2007||Feb 4, 2014||Raminda Udaya Madurawe||Pads and pin-outs in three dimensional integrated circuits|
|US8735885 *||Dec 3, 2008||May 27, 2014||Semiconductor Energy Laboratory Co., Ltd.||Antifuse memory device|
|US8829664||Jul 12, 2010||Sep 9, 2014||Raminda Udaya Madurawe||Three dimensional integrated circuits|
|US8856699||Sep 10, 2012||Oct 7, 2014||Raminda Udaya Madurawe||Three dimensional integrated circuits|
|US9059098||Oct 10, 2013||Jun 16, 2015||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor device and manufacturing method thereof|
|US9070668||Jan 6, 2014||Jun 30, 2015||Yakimishu Co. Ltd. L.L.C.||Pads and pin-outs in three dimensional integrated circuits|
|US9087169||Jul 23, 2012||Jul 21, 2015||Raminda U. Madurawe||Automated metal pattern generation for integrated circuits|
|US9240790||Aug 13, 2014||Jan 19, 2016||Callahan Cellular L.L.C.||Three dimensional integrated circuits|
|US9397665||Aug 18, 2014||Jul 19, 2016||Callahan Cellular L.L.C.||Programmable structured arrays|
|US9406606 *||Jul 21, 2014||Aug 2, 2016||Micron Technology, Inc.||Semiconductor device having a reduced area and enhanced yield|
|US9437620||May 21, 2015||Sep 6, 2016||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor device and manufacturing method thereof|
|US20030173643 *||Mar 13, 2002||Sep 18, 2003||Matrix Semiconductor, Inc.||Silicide-silicon oxide-semiconductor antifuse device and method of making|
|US20050023525 *||Dec 8, 2003||Feb 3, 2005||Semiconductor Energy Laboratory Co. Ltd., A Japan Corporation||Semiconductor device and manufacturing method thereof|
|US20060068536 *||Sep 16, 2005||Mar 30, 2006||Semiconductor Energy Laboratory Co., Ltd.||Method for manufacturing semiconductor device, and semiconductor device and electronic device|
|US20060076643 *||Oct 8, 2004||Apr 13, 2006||Internationall Business Machines Corporation||Fin-type antifuse|
|US20060099738 *||Sep 16, 2005||May 11, 2006||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor device and method for manufacturing the same, and electric appliance|
|US20060110863 *||Nov 16, 2005||May 25, 2006||Yoshiaki Yamamoto||Semiconductor device, and method for manufacturing the same|
|US20060150137 *||Feb 27, 2006||Jul 6, 2006||Madurawe Raminda U||Three dimensional integrated circuits|
|US20060275960 *||May 25, 2006||Dec 7, 2006||Semiconductor Energy Laboratory Co., Ltd.||Integrated circuit device and method for manufacturing integrated circuit device|
|US20070018164 *||Sep 8, 2006||Jan 25, 2007||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor Device and Manufacturing Method Thereof|
|US20070023758 *||Jul 14, 2006||Feb 1, 2007||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor device and manufacturing method thereof|
|US20070105264 *||Oct 27, 2006||May 10, 2007||Semiconductor Energy Laboratory Co., Ltd.||Manufacturing method of semiconductor device|
|US20080087982 *||Feb 7, 2006||Apr 17, 2008||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor Device and Manufacturing Method Thereof|
|US20080099878 *||Feb 7, 2006||May 1, 2008||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor Device and Manufacturing Method of the Same|
|US20080283838 *||Apr 4, 2008||Nov 20, 2008||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor device and manufacturing method thereof|
|US20080286905 *||Jul 31, 2008||Nov 20, 2008||International Business Machines Corporation||Fin-Type Antifuse|
|US20090008715 *||Aug 27, 2008||Jan 8, 2009||Semiconductor Energy Laboratory Co., Ltd.||Method for manufacturing semiconductor device, and semiconductor device and electronic device|
|US20090140249 *||Dec 23, 2008||Jun 4, 2009||Semiconductor Energy Laboratory Co., Ltd.||Integrated circuit device and method for manufacturing integrated circuit device|
|US20090146189 *||Nov 19, 2007||Jun 11, 2009||Raminda Udaya Madurawe||Pads and pin-outs in three dimensional integrated circuits|
|US20090152549 *||Dec 3, 2008||Jun 18, 2009||Semiconductor Energy Laboratory Co., Ltd.||Memory device|
|US20090299698 *||Dec 3, 2009||Burke Michael R||Co-Resident Software Performance Tracking|
|US20090300602 *||Jun 3, 2008||Dec 3, 2009||Burke Michael R||Determining application distribution based on application state tracking information|
|US20100237354 *||Sep 23, 2010||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor device and method for manufacturing the same|
|US20110031582 *||Feb 10, 2011||International Business Machines Corporation||Fin anti-fuse with reduced programming voltage|
|US20110073861 *||Oct 12, 2010||Mar 31, 2011||Semiconductor Energy Laboratory Co., Ltd.||Integrated circuit device and method for manufacturing integrated circuit device|
|US20110084321 *||Dec 17, 2010||Apr 14, 2011||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor device and manufacturing method thereof|
|US20130311961 *||Jul 29, 2013||Nov 21, 2013||Raminda Madurawe||Timing exact design conversions from fpga to asic|
|US20150029776 *||Jul 21, 2014||Jan 29, 2015||Micron Technology, Inc.||Semiconductor device having a reduced area and enhanced yield|
|CN100442500C||Oct 8, 2005||Dec 10, 2008||国际商业机器公司||Fin-type antifuse|
|CN100546034C||Feb 7, 2006||Sep 30, 2009||株式会社半导体能源研究所||Semiconductor device and preparing method thereof|
|WO1995027313A1 *||Mar 22, 1995||Oct 12, 1995||Crosspoint Solutions, Inc.||Method of manufacturing an antifuse with silicon spacers and resulting antifuse|
|WO1995032523A1 *||May 24, 1995||Nov 30, 1995||Crosspoint Solutions, Inc.||A low capacitance, isotropically etched antifuse|
|WO2006085637A1 *||Feb 7, 2006||Aug 17, 2006||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor device and manufacturing method thereof|
|WO2011019562A2 *||Aug 4, 2010||Feb 17, 2011||International Business Machines Corporation||Fin anti-fuse with reduced programming voltage|
|WO2011019562A3 *||Aug 4, 2010||May 5, 2011||International Business Machines Corporation||Fin anti-fuse with reduced programming voltage|
|U.S. Classification||326/41, 257/530, 326/45, 257/E23.147, 257/50, 326/38|
|International Classification||H01L21/82, H01L27/10, H01L27/118, H01L23/525|
|Cooperative Classification||H01L23/5252, H01L2924/0002|
|Jan 23, 1991||AS||Assignment|
Owner name: MYSON TECHNOLOGY, INC., A CORP. OF CA, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:HSU, FU-CHIEH;PAI, PEI-LIN;REEL/FRAME:005598/0289
Effective date: 19910119
|Mar 11, 1991||AS||Assignment|
Owner name: MYSON TECHNOLOGY, INC., 20380 TOWN CENTER LANE, #1
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:HSU, FU-CHIEH;PAI, PEI-LIN;REEL/FRAME:005639/0105
Effective date: 19910119
|Jul 22, 1991||AS||Assignment|
Owner name: KNIGHTS TECHNOLOGY, INC. A CA CORPORATION, CALIF
Free format text: ASSIGNMENT OF 1/2 OF ASSIGNORS INTEREST;ASSIGNOR:MYSON TECHNOLOGY, INC., A CA CORPORATION;REEL/FRAME:005774/0573
Effective date: 19910717
|Jul 2, 1996||REMI||Maintenance fee reminder mailed|
|Nov 24, 1996||LAPS||Lapse for failure to pay maintenance fees|
|Feb 4, 1997||FP||Expired due to failure to pay maintenance fee|
Effective date: 19961127
|Oct 22, 2003||AS||Assignment|
Owner name: FEI COMPANY, OREGON
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KNIGHTS TECHNOLOGY INC.;REEL/FRAME:014066/0082
Effective date: 20030806
|Jul 1, 2004||AS||Assignment|
Owner name: ELECTROGLASS, INC., CALIFORNIA
Free format text: MERGER;ASSIGNOR:KNIGHTS TECHNOLOGY, INC.;REEL/FRAME:014805/0440
Effective date: 19981223
Owner name: FEI COMPANY, OREGON
Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE CONVEYING PARTY PREVIOUSLY RECORDED ON REEL 014066 FRAME 0082;ASSIGNOR:ELECTROGLASS, INC;REEL/FRAME:014805/0456
Effective date: 20030805