US5192706A - Method for semiconductor isolation - Google Patents
Method for semiconductor isolation Download PDFInfo
- Publication number
- US5192706A US5192706A US07/575,259 US57525990A US5192706A US 5192706 A US5192706 A US 5192706A US 57525990 A US57525990 A US 57525990A US 5192706 A US5192706 A US 5192706A
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- silicon
- trenches
- oxide
- layer
- trench
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/127—Process induced defects
Definitions
- This invention pertains in general to a semiconductor integrated circuit, and more particularly relates to an improved method of isolating active devices.
- LOCOS Local Oxidation of Silicon
- a patterned nitride on top of a thin oxide stack is used to cover what will be active areas of a silicon substrate.
- a relatively thick field oxide is grown only in the exposed regions.
- the LOCOS technique grows field oxide not only vertically in the exposed silicon regions, but also laterally underneath the edges of the nitride mask.
- This lateral oxide encroachment under the nitride known as "birds-beak,” can extend laterally to a distance of about half the field oxide thickness; thus, substantial real estate is wasted in this isolation technology.
- the field oxide thickness has to be scaled down appropriately in order to reduce the birds-beak, otherwise, the remaining active areas will be inadequate for forming active devices.
- the reduction in field oxide thickness degrades the circuit performance because of increased interconnect capacitance.
- the leakage current under the field oxide and between adjacent active areas increases rapidly with decreasing oxide thickness for a given voltage applied to a conductor passing over the field oxide, resulting in reduced isolation between adjacent active areas.
- Isolation between two adjacent components of the integrated circuit can also be achieved with the use of minimum surface area by etching a trench extending into the substrate between the two components and then refilling the trench with an insulator.
- Trench isolation uses much less surface area than does either diffused junction isolation or local oxide isolation.
- High quality integrated circuits require the semiconductor material along the edge of the trench to be of high integrity with a minimum of process induced defects.
- Reactive ion etching which is a preferred method for anisotropically etching trenches, has a tendency to produce a thin defect layer along the trench walls. Defects of this type degrade device performance by forming parasitic channels along the trench to active region junction which increase leakage currents.
- the insulating layer directly adjacent to the trench edges is desired to be a thermally grown silicon dioxide layer.
- the present invention provides a method for forming a semiconductor integrated circuit with trenches around selected areas on a semiconductor body, wherein an inorganic layer (e.g. noncrystalline silicon) is formed on the top surface of a semiconductor body.
- an inorganic layer e.g. noncrystalline silicon
- Wide and narrow trenches may be formed around selected areas, (possibly wide and narrow) on a semiconductor body, while the selected areas are masked by the inorganic layer. Silicon may then be removed from the walls of the trenches followed by growth of thin thermal oxide along trench edges, thus reducing the thin defect layer.
- Trenches are then filled with anisotropically deposited silicon material (e.g. oxide). Lastly, removing (e.g. etching) the inorganic layer lifts off the anisotropic layer deposited above the inorganic layer.
- the invention can use removing of silicon from the walls of the trenches and subsequent growth of thin thermal oxide along trench edges to minimize the defects along the trench edges and provide a good interface between the isolation region and the semiconductor body, thus reducing formation of parasitic channels along trench edges.
- the invention's use of anisotropic fill in the trenches allows for wide and narrow trenches to be simultaneously filled.
- the invention's preferable use of removing the inorganic, nonoxide and the use of anisotropic silicon oxide to fill the trenches produces a flat planar surface (flush with the surface of the semiconductor body) without any bird's beak and produces finer isolation regions.
- FIGS. 1 through 7 illustrate a preferred method for forming a semiconductor integrated circuit with wide and narrow isolation regions around selected areas on a semiconductor body according to this invention.
- FIGS. 8 through 10 illustrate a preferred method for forming a semiconductor integrated circuit with wide and narrow isolation regions around selected wide and narrow areas on a semiconductor body according to this invention.
- an integrated circuit semiconductor body 10 is prepared, which may have n-type and p-type wells formed (not shown). Within the wells, generally, active and passive devices (not shown) will be formed which may need to be isolated from the remainder of the circuitry on the semiconductor body 10.
- the semiconductor body 10 is thermally oxidized to form an oxide layer 12 of preferably 300 to 1000 Angstroms in thickness.
- a noncrystalline silicon layer 14 is deposited on the entire surface of the oxide layer 12 with a thickness of 2000 to 5000 Angstroms.
- a photoresist film is applied on the entire surface of the noncrystalline silicon layer 14.
- the photoresist layer is selectively removed to form a photoresist mask 16 having narrow and wide openings, wherein the width of narrow openings is approximately 0.5 micrometers and the width of wide openings is of the order twice or greater than the width of narrow openings.
- the exposed portions of the noncrystalline silicon layer 14 are then etched by an etch which is selective to silicon over oxide.
- the structure is then subjected to an etch process to remove the exposed oxide layer 12, so that openings 18 are formed over selected surfaces of the semiconductor body 10 (to form the intended isolation regions as shown in FIG. 2).
- the structure obtained is subjected to an anisotropic etching process to form trenches 24 to a depth preferably of 0.3 to 1.5 micrometers.
- the structure is then subjected to a wet silicon etch (if desired) to remove etch damage and is then oxidized at a high temperature, preferably above 800 degrees C.
- a wet silicon etch if desired
- the higher oxidized temperature allows for a much faster rate of growth and a more uniform oxidation of the trench edges (than if performed at lower temperatures).
- An optional stripping of the oxide film 26 and regrowing the oxide film 26 to further reduce defects along the trench edges can be performed at this step.
- the entire surface of the structure obtained is subjected to an anisotropically deposited oxide 28 to a preferable thickness which fills or slightly overfills the trenches with negligible introduction of defects along the trench walls.
- a short wet oxide etch is utilized to remove the portion of oxide film 26 which is on the lateral edge of the noncrystalline silicon 14.
- the structure is then subjected to an isotropic etch selective to oxide which laterally etches the noncrystalline silicon 14 and lifts off the anisotropic oxide 28 deposited on top of the noncrystalline silicon 14 and exposing the oxide 12 on top of the selected areas 12 of the semiconductor body as shown in FIG. 7.
- An inorganic, non-oxide, such as noncrystalline silicon can be removed, by etching or other means, without removal of the oxide 12 protecting the semiconductor body 10.
- FIG. 8 is similar to FIG. 5, but having a wide active region and narrow active regions.
- a photoresist masking layer 30 is formed exposing a wide region 32 of anisotropically deposited oxide 28 on top of the noncrystalline silicon 14 while narrow regions 34 remain covered. An etch then removes the wide region 32 of the anisotropic silicon oxide 28 and of the thermal oxide 26.
- the photoresist mask 30 is removed and the structure is then subjected to an isotropic etch which removes the noncrystalline silicon 14 and lifts off the anisotropic silicon oxide 28 deposited on top of the noncrystalline silicon 14 and exposing the oxide 12 on top of the selected areas 12 of the semiconductor body 10, as shown in FIG. 10.
- an integrated circuit is formed with wide and narrow trenches simultaneously filled with a single deposition, a flat planar surface, and a trench to active region interface which is thermally oxidized reducing interfacial defects and thus preventing parasitic channel formation along trench edges.
- silicon nitride may be used in replace of noncrystalline silicon, or a composite stack of noncrystalline silicon and oxide can be utilized instead of solely noncrystalline silicon.
- a patterned mask could be used with an etch to remove the undesired anisotropic oxide and noncrystalline silicon instead of the lateral isotropic etch.
Abstract
This is a method of forming a semiconductor integrated circuit with isolation regions, (possibly wide and narrow) comprising of a thin oxide film and deposited anisotropic oxide. It uses an inorganic layer (e.g. noncrystalline silicon) to mask what will be active areas and allows for the growth of a thermal oxide film in the trenches reducing the parasitic channel formation along the trenches. The use of anisotropic oxide to fill the trenches allows for wide and narrow trenches to be simultaneously filled to the desired depth. The removing of inorganic layer and the use of anisotropic oxide to fill the trenches produces a flat planar surface and finer isolation regions.
Description
This invention pertains in general to a semiconductor integrated circuit, and more particularly relates to an improved method of isolating active devices.
In integrated circuit technology, it is necessary to separate the active regions containing active devices from one another. In early bipolar integrated circuits, the active regions were generally electrically isolated from each other by PN junctions. However, with increasing demand for higher device densities, it has become necessary to reduce the isolation areas.
In VLSI integrated circuits using MOS technology, isolation of active regions has usually been accomplished by LOCOS (Local Oxidation of Silicon). To perform LOCOS, a patterned nitride on top of a thin oxide stack is used to cover what will be active areas of a silicon substrate. By exposing the uncovered regions of the silicon substrate to a high temperature oxidizing ambient, a relatively thick field oxide is grown only in the exposed regions.
However, the LOCOS technique grows field oxide not only vertically in the exposed silicon regions, but also laterally underneath the edges of the nitride mask. This lateral oxide encroachment under the nitride, known as "birds-beak," can extend laterally to a distance of about half the field oxide thickness; thus, substantial real estate is wasted in this isolation technology. With the standard LOCOS process, the field oxide thickness has to be scaled down appropriately in order to reduce the birds-beak, otherwise, the remaining active areas will be inadequate for forming active devices. The reduction in field oxide thickness, however, degrades the circuit performance because of increased interconnect capacitance. In addition, the leakage current under the field oxide and between adjacent active areas increases rapidly with decreasing oxide thickness for a given voltage applied to a conductor passing over the field oxide, resulting in reduced isolation between adjacent active areas.
Further problems are encountered when using LOCOS to form wide and narrow isolation regions simultaneously. In particular, since the growth of field oxide is vertical and lateral, the thickness of grown field oxide in narrow regions can be substantially less than in wide regions. Thus, to achieve a desired field oxide thickness in narrow regions, a much larger field oxide is grown in wide regions with concomitant much larger "birds-beak".
Isolation between two adjacent components of the integrated circuit can also be achieved with the use of minimum surface area by etching a trench extending into the substrate between the two components and then refilling the trench with an insulator. Trench isolation uses much less surface area than does either diffused junction isolation or local oxide isolation.
High quality integrated circuits require the semiconductor material along the edge of the trench to be of high integrity with a minimum of process induced defects. Reactive ion etching, which is a preferred method for anisotropically etching trenches, has a tendency to produce a thin defect layer along the trench walls. Defects of this type degrade device performance by forming parasitic channels along the trench to active region junction which increase leakage currents.
To reduce the formation of such a parasitic channel along the trench, the insulating layer directly adjacent to the trench edges is desired to be a thermally grown silicon dioxide layer.
Accordingly, it is an object of this invention to provide a more effective method of fabricating a semiconductor integrated circuit, which is capable of simultaneously fabricating narrow and wide isolation regions.
It is a further object of this invention to provide a method of fabricating a semiconductor integrated circuit, which is capable of providing a flat planar surface without any bird's beak on the semiconductor body, by utilizing relatively simple steps and minimizing the problems of trenches.
It is a still further object of this invention to provide a method of fabricating a semiconductor integrated circuit, which minimizes process induced defects along the walls of the trench, thus providing a good interface between the isolation region and the semiconductor body.
The present invention provides a method for forming a semiconductor integrated circuit with trenches around selected areas on a semiconductor body, wherein an inorganic layer (e.g. noncrystalline silicon) is formed on the top surface of a semiconductor body. Wide and narrow trenches may be formed around selected areas, (possibly wide and narrow) on a semiconductor body, while the selected areas are masked by the inorganic layer. Silicon may then be removed from the walls of the trenches followed by growth of thin thermal oxide along trench edges, thus reducing the thin defect layer. Trenches are then filled with anisotropically deposited silicon material (e.g. oxide). Lastly, removing (e.g. etching) the inorganic layer lifts off the anisotropic layer deposited above the inorganic layer.
The invention can use removing of silicon from the walls of the trenches and subsequent growth of thin thermal oxide along trench edges to minimize the defects along the trench edges and provide a good interface between the isolation region and the semiconductor body, thus reducing formation of parasitic channels along trench edges.
The invention's use of anisotropic fill in the trenches allows for wide and narrow trenches to be simultaneously filled.
The invention's preferable use of removing the inorganic, nonoxide and the use of anisotropic silicon oxide to fill the trenches produces a flat planar surface (flush with the surface of the semiconductor body) without any bird's beak and produces finer isolation regions.
FIGS. 1 through 7 illustrate a preferred method for forming a semiconductor integrated circuit with wide and narrow isolation regions around selected areas on a semiconductor body according to this invention.
FIGS. 8 through 10 illustrate a preferred method for forming a semiconductor integrated circuit with wide and narrow isolation regions around selected wide and narrow areas on a semiconductor body according to this invention.
Referring to FIG. 1, an integrated circuit semiconductor body 10 is prepared, which may have n-type and p-type wells formed (not shown). Within the wells, generally, active and passive devices (not shown) will be formed which may need to be isolated from the remainder of the circuitry on the semiconductor body 10. The semiconductor body 10 is thermally oxidized to form an oxide layer 12 of preferably 300 to 1000 Angstroms in thickness. A noncrystalline silicon layer 14 is deposited on the entire surface of the oxide layer 12 with a thickness of 2000 to 5000 Angstroms. A photoresist film is applied on the entire surface of the noncrystalline silicon layer 14. The photoresist layer is selectively removed to form a photoresist mask 16 having narrow and wide openings, wherein the width of narrow openings is approximately 0.5 micrometers and the width of wide openings is of the order twice or greater than the width of narrow openings. The exposed portions of the noncrystalline silicon layer 14 are then etched by an etch which is selective to silicon over oxide. The structure is then subjected to an etch process to remove the exposed oxide layer 12, so that openings 18 are formed over selected surfaces of the semiconductor body 10 (to form the intended isolation regions as shown in FIG. 2).
Referring to FIG. 3, the structure obtained is subjected to an anisotropic etching process to form trenches 24 to a depth preferably of 0.3 to 1.5 micrometers.
Referring to FIG. 4, after removing the photoresist mask 16, the structure is then subjected to a wet silicon etch (if desired) to remove etch damage and is then oxidized at a high temperature, preferably above 800 degrees C. This results in an oxide film 26, with a thickness of approximately 100 to 800 Angstroms, being formed on the entire surface of the structure including the sides and bottom of the trenches 24. The higher oxidized temperature allows for a much faster rate of growth and a more uniform oxidation of the trench edges (than if performed at lower temperatures). An optional stripping of the oxide film 26 and regrowing the oxide film 26 to further reduce defects along the trench edges can be performed at this step.
Referring to FIG. 5, the entire surface of the structure obtained is subjected to an anisotropically deposited oxide 28 to a preferable thickness which fills or slightly overfills the trenches with negligible introduction of defects along the trench walls.
Referring to FIG. 6, preferably a short wet oxide etch is utilized to remove the portion of oxide film 26 which is on the lateral edge of the noncrystalline silicon 14. The structure is then subjected to an isotropic etch selective to oxide which laterally etches the noncrystalline silicon 14 and lifts off the anisotropic oxide 28 deposited on top of the noncrystalline silicon 14 and exposing the oxide 12 on top of the selected areas 12 of the semiconductor body as shown in FIG. 7. An inorganic, non-oxide, such as noncrystalline silicon can be removed, by etching or other means, without removal of the oxide 12 protecting the semiconductor body 10.
A variation to the above steps is required when the noncrystalline silicon 14 above the active areas 20 is wide so that the isotropic lateral etch cannot adequately remove the noncrystalline silicon 14 in a practical etch time. FIG. 8 is similar to FIG. 5, but having a wide active region and narrow active regions. Before the structure is subjected to the isotropic etch, a photoresist masking layer 30 is formed exposing a wide region 32 of anisotropically deposited oxide 28 on top of the noncrystalline silicon 14 while narrow regions 34 remain covered. An etch then removes the wide region 32 of the anisotropic silicon oxide 28 and of the thermal oxide 26.
Referring to FIG. 9, the photoresist mask 30 is removed and the structure is then subjected to an isotropic etch which removes the noncrystalline silicon 14 and lifts off the anisotropic silicon oxide 28 deposited on top of the noncrystalline silicon 14 and exposing the oxide 12 on top of the selected areas 12 of the semiconductor body 10, as shown in FIG. 10.
The above-mentioned embodiment of this invention offers the advantages in that an integrated circuit is formed with wide and narrow trenches simultaneously filled with a single deposition, a flat planar surface, and a trench to active region interface which is thermally oxidized reducing interfacial defects and thus preventing parasitic channel formation along trench edges.
It should be noted that this invention is not limited to the aforementioned embodiment, but can be applied in various modifications. For instance, silicon nitride may be used in replace of noncrystalline silicon, or a composite stack of noncrystalline silicon and oxide can be utilized instead of solely noncrystalline silicon. Also, a patterned mask could be used with an etch to remove the undesired anisotropic oxide and noncrystalline silicon instead of the lateral isotropic etch.
The invention is not to be construed as limited to the particular forms described herein, since these are to be regarded as illustrative rather than restrictive. The invention is intended to cover all processes which do not depart from the spirit and scope of the invention.
Claims (8)
1. A method for isolating a selected area on an integrated circuit, comprising the steps of:
(a) forming an oxide layer on a top surface of a silicon semiconductor body;
(b) forming a non-crystalline silicon layer on top of said oxide layer;
(c) anisotropically forming trenches around selected areas in said semiconductor body;
(d) removing silicon from the trench walls to remove defects from said walls;
(e) filling said trenches and covering said non-crystalline silicon layer with anisotropically deposited silicon oxide;
(f) removing silicon oxide from vertical surfaces of said non-crystalline silicon; and
(g) removing said non-crystalline silicon layer, thereby removing said deposited silicon oxide layer deposited above said inorganic, non-oxide layer, whereby an integrated circuit is formed with essentially a planar surface and having trenches with walls which are essentially defect-free.
2. The method according to claim 1, wherein said oxide layer is silicon dioxide.
3. The method according to claim 2, wherein said silicon dioxide thickness is approximately 100 to 300 Angstroms.
4. The method according to claim 1, wherein said non-crystalline silicon layer thickness is approximately 2000 to 5000 Angstroms.
5. The method according to claim 1, wherein the depth of said trenches is 0.3 to 1.5 micrometer.
6. The method according to claim 1, wherein said silicon removed from the trench walls is removed by an etchant.
7. The method according to claim 1, wherein said silicon removed from the trench walls is removed by growing silicon oxide at a temperature of at least 800° C.
8. A method for isolating a selected area on an integrated circuit substrate, comprising the steps of:
(a) forming an amorphous silicon layer on top of said substrate;
(b) removing portions of said amorphous silicon layer and said substrate to form trenches around selected areas in said semiconductor body;
(c) anisotropically depositing trench-fill material; and
(d) removing said amorphous silicon layer thereby removing said deposited trench-fill material deposited above said amorphous silicon layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/575,259 US5192706A (en) | 1990-08-30 | 1990-08-30 | Method for semiconductor isolation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/575,259 US5192706A (en) | 1990-08-30 | 1990-08-30 | Method for semiconductor isolation |
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| US5192706A true US5192706A (en) | 1993-03-09 |
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| US07/575,259 Expired - Lifetime US5192706A (en) | 1990-08-30 | 1990-08-30 | Method for semiconductor isolation |
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5763932A (en) * | 1996-11-12 | 1998-06-09 | Micron Technology, Inc. | Isolation regions and methods of forming isolation regions |
| US5981355A (en) * | 1996-11-07 | 1999-11-09 | Lg Semicon Co., Ltd. | Method of forming isolating region |
| US5985734A (en) * | 1996-12-31 | 1999-11-16 | Hyundai Electronics Industries Co., Ltd. | Method for fabricating a semiconductor device |
| US6001706A (en) * | 1997-12-08 | 1999-12-14 | Chartered Semiconductor Manufacturing, Ltd. | Method for making improved shallow trench isolation for semiconductor integrated circuits |
| US6008107A (en) * | 1990-06-14 | 1999-12-28 | National Semiconductor Corporation | Method of planarizing integrated circuits with fully recessed isolation dielectric |
| US6054343A (en) * | 1998-01-26 | 2000-04-25 | Texas Instruments Incorporated | Nitride trench fill process for increasing shallow trench isolation (STI) robustness |
| US6103581A (en) * | 1998-11-27 | 2000-08-15 | Taiwan Semiconductor Manufacturing Company | Method for producing shallow trench isolation structure |
| US6107157A (en) * | 1998-02-27 | 2000-08-22 | Micron Technology, Inc. | Method and apparatus for trench isolation process with pad gate and trench edge spacer elimination |
| US6261914B1 (en) | 1999-07-27 | 2001-07-17 | International Business Machines Corporation | Process for improving local uniformity of chemical mechanical polishing using a self-aligned polish rate enhancement layer |
| KR100318461B1 (en) * | 1998-10-13 | 2002-02-19 | 박종섭 | Semiconductor device isolation method |
| US20020081852A1 (en) * | 2000-03-20 | 2002-06-27 | Sandhu Gurtej S. | Method to form etch and/or CMP stop layers |
| US20210193466A1 (en) * | 2019-12-18 | 2021-06-24 | Cornell University | Method for removing re-sputtered material from patterned sidewalls |
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Cited By (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6008107A (en) * | 1990-06-14 | 1999-12-28 | National Semiconductor Corporation | Method of planarizing integrated circuits with fully recessed isolation dielectric |
| US5981355A (en) * | 1996-11-07 | 1999-11-09 | Lg Semicon Co., Ltd. | Method of forming isolating region |
| US5763932A (en) * | 1996-11-12 | 1998-06-09 | Micron Technology, Inc. | Isolation regions and methods of forming isolation regions |
| US5834358A (en) * | 1996-11-12 | 1998-11-10 | Micron Technology, Inc. | Isolation regions and methods of forming isolation regions |
| US6066544A (en) * | 1996-11-12 | 2000-05-23 | Micron Technology, Inc. | Isolation regions and methods of forming isolation regions |
| US6093953A (en) * | 1996-11-12 | 2000-07-25 | Micron Technology, Inc. | Isolation regions and methods of forming isolation regions |
| US5985734A (en) * | 1996-12-31 | 1999-11-16 | Hyundai Electronics Industries Co., Ltd. | Method for fabricating a semiconductor device |
| US6001706A (en) * | 1997-12-08 | 1999-12-14 | Chartered Semiconductor Manufacturing, Ltd. | Method for making improved shallow trench isolation for semiconductor integrated circuits |
| US6054343A (en) * | 1998-01-26 | 2000-04-25 | Texas Instruments Incorporated | Nitride trench fill process for increasing shallow trench isolation (STI) robustness |
| US6107157A (en) * | 1998-02-27 | 2000-08-22 | Micron Technology, Inc. | Method and apparatus for trench isolation process with pad gate and trench edge spacer elimination |
| US6358801B1 (en) | 1998-02-27 | 2002-03-19 | Micron Technology, Inc. | Method and apparatus for trench isolation process with pad gate and trench edge spacer elimination |
| US6380599B1 (en) | 1998-02-27 | 2002-04-30 | Micron Technology, Inc. | Method and apparatus for trench isolation process with pad gate and trench edge spacer elimination |
| US6861726B2 (en) | 1998-02-27 | 2005-03-01 | Micron Technology, Inc. | Apparatus having trench isolation structure with reduced isolation pad height and edge spacer |
| KR100318461B1 (en) * | 1998-10-13 | 2002-02-19 | 박종섭 | Semiconductor device isolation method |
| US6103581A (en) * | 1998-11-27 | 2000-08-15 | Taiwan Semiconductor Manufacturing Company | Method for producing shallow trench isolation structure |
| US6261914B1 (en) | 1999-07-27 | 2001-07-17 | International Business Machines Corporation | Process for improving local uniformity of chemical mechanical polishing using a self-aligned polish rate enhancement layer |
| US20020081852A1 (en) * | 2000-03-20 | 2002-06-27 | Sandhu Gurtej S. | Method to form etch and/or CMP stop layers |
| US20060089002A1 (en) * | 2000-03-20 | 2006-04-27 | Micron Technology, Inc. | Method to form etch and/or CMP stop layers |
| US7052997B2 (en) * | 2000-03-20 | 2006-05-30 | Micron Technology, Inc. | Method to form etch and/or CMP stop layers |
| US20210193466A1 (en) * | 2019-12-18 | 2021-06-24 | Cornell University | Method for removing re-sputtered material from patterned sidewalls |
| US11615960B2 (en) * | 2019-12-18 | 2023-03-28 | Cornell University | Method for removing re-sputtered material from patterned sidewalls |
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