|Publication number||US5200880 A|
|Application number||US 07/808,600|
|Publication date||Apr 6, 1993|
|Filing date||Dec 17, 1991|
|Priority date||Dec 17, 1991|
|Also published as||EP0549261A1|
|Publication number||07808600, 808600, US 5200880 A, US 5200880A, US-A-5200880, US5200880 A, US5200880A|
|Original Assignee||Sgs-Thomson Microelectronics, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (4), Referenced by (1), Classifications (17), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates generally to integrated circuits, and more specifically to a method for forming interconnect lines in integrated circuits.
2. Description of the Prior Art
As integrated circuit devices become more complex, greater numbers of interconnect levels are required to connect the various sections of the device. Complex devices are being designed which have two or more levels of interconnect. These levels of interconnect are typically made of polycrystalline silicon or metal. When multiple layers of interconnect are used in this manner, difficulties are encountered in forming upper interconnect levels because of uneven topographical features caused by lower interconnect levels. Thus, topography of interconnect layers affects the ease of manufacturing of the integrated circuit device.
The uneven topographical features of multiple interconnect levels are caused by forming the various interconnect layers above each other, resulting in the creation of hills and valleys on the surface of the device. Those skilled in the art will recognize it is difficult to get upper interconnect layers to cross over the hills and fill in the valleys created by the underlying interconnect layers. These step coverage problems can result in voids and other defects in the interconnect signal lines themselves, and in the contact vias formed between interconnect signal lines.
In order to make forming upper interconnect levels easier, planarization of lower interconnect levels is routinely performed. Typically, a layer of material such as a reflow glass or spin on glass can be used as part of an interlevel dielectric layer. These materials, when applied properly, have an upper surface which is smoother and more nearly planar than the topography of the underlying surface. This allows the roughness caused by underlying interconnect layers to be smoothed out somewhat prior to the formation of the next layer of interconnect. This next layer of interconnect is then formed on top of the planarized interlevel dielectric layer. Even with this technique, step coverage problems exist since formation of the interconnect layer on the planarized dielectric layer generates uneven topographical features for the next dielectric layer, requiring further planarization. In addition, the planarization improves the flatness of the surface, but does not completely eliminate hills and valleys caused by underlying topographical features.
Therefore, it would be desirable to provide a method for forming interconnect lines which are free of voids and other defects, and which result in a more planar topography. It is also desirable that such a method does not significantly increase the complexity of the manufacturing process.
It is therefore an object of the present invention to provide a method for forming metal interconnect signal lines which result in a more planar topography.
It is another object of the present invention to provide such a method and structure which is compatible with standard process flows, and which add minimal additional complexity to the fabrication of a typical integrated circuit.
Therefore, according to the present invention, a thin conductive layer is formed over an underlying structure in an integrated circuit. The underlying structure can be either a semiconductor substrate or an interlevel interconnect signal line. An insulating layer is deposited over the device. The insulating layer is patterned and etched in order to expose a portion of the underlying conductive layer and to define an interconnect signal line. When the signal line locations are etched away, the thin conductive layer acts as an etch stop and protects the underlying structure. A metal refill process can be used to then form interconnects and contacts within the etched interconnect lines. This results in interconnect and contacts having upper surfaces which are substantially coplanar with the upper surface of the insulating layer in which they are formed.
The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself however, as well as a preferred mode of use, and further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
FIGS. 1-5 are sectional views illustrating a preferred method for forming interconnect in integrated circuits according to the present invention.
The process steps and structures described below do not form a complete process flow for manufacturing integrated circuits. The present invention can be practiced in conjunction with integrated circuit fabrication techniques currently used in the art, and only so much of the commonly practiced process steps are included as are necessary for an understanding of the present invention. The figures representing cross-sections of portions of an integrated circuit during fabrication are not drawn to scale, but instead are drawn so as to illustrate the important features of the invention.
Referring to FIG. 1, a contact and interconnect is to be formed over an underlying region 10 of an integrated circuit. The underlying region 10 is either a semiconductor substrate or an underlying interconnect signal line. An insulating layer 12, typically made of oxide, is deposited or grown over the device. Contact openings 14, 16 are created in the insulating layer 12 using methods known in the art.
FIG. 2 illustrates the device after the contact openings 14, 16 are filled with conductive material 18. Conductive material 18, may for example, be made of tungsten or aluminum. The conductive material 18 can be selectively deposited into the contact openings 14, 16 using selective deposition techniques known in the art, or the layer of conductive material 18 can be deposited over the device and then etched back such that the upper surface of the conductive material 18 lies planar with the upper surface of the insulating layer 12.
Referring to FIG. 3, a thin layer of metal 20 is deposited and patterned over the conductive material 18. The thin layer of metal 20 defines a pattern for interconnect which will be formed on the device. The width of the thin layer of metal 20 should be wider than the width of the prospective interconnect line. The larger width allows for some errors in mask registration. Metal layer 20 will typically have a thickness of between 300 and 1500 angstroms.
As shown in FIG. 4, a second layer of insulating material 22, typically made of oxide, is deposited over the device. The second insulating layer 22 is then patterned and etched to expose a portion of the thin layer of metal 20 and form interconnect molds 24, 26. One advantage of using the thin layer of metal 20, is that it acts as an etch stop and protects the underlying material 18 during formation of the interconnect molds 24, 26.
Referring to FIG. 5, interconnect molds 24, 26 are filled with a second conductive layer 28. The conductive layer 28 can be made of, for example, tungsten, aluminum, or copper. The conductive layer 28 can be formed by depositing a layer of conductive material over the device and etching portions of it away. Alternatively, selective deposition can be used to form conductive layer 28. Another advantage of using the thin layer of metal 20 is that it will act as a catalytic seed for selective deposition. Additionally, the thin layer of metal 20 will act as an adhesive layer for the conductive layer 28.
Although the present invention has been described with reference to forming one layer of interconnect, it is possible to use this process for multi-level metalization. For example, following the method described in reference to FIG. 5, another insulating layer can be deposited and patterned to create contact vias to the conductive layer 28. The vias can then be filled either by selective deposition or blanket deposition and etchback with a conductive material, as shown in FIG. 2. The process continues as described in reference to FIGS. 3-5. Thus, the presently described invention can be utilized in forming each layer of interconnect in an integrated circuit.
Those skilled in the art will recognize that the thin layer of metal 20 used in the presently claimed invention serves a variety of functions. First, it protects the underlying structure by acting as an etch stop during formation of the interconnect molds 24, 26. Second, the thin layer of metal 20 can act as a catalytic seed for the second conductive layer 28 if selective deposition is used to form the layer. Additionally, the thin layer of metal 20 acts as an adhesive layer during formation of the second conductive layer 28. Finally, the thin layer of metal 20 does not significantly impact manufacturing of the integrated circuit. It is easy to pattern and etch, and because it is thin, it does not significantly affect the planarity of the device.
In summary, the invention described above provides a method for planarizing interconnect signal lines. Furthermore, the method is compatible with standard processing techniques, and does not significantly increase the complexity in fabricating a typical integrated circuit.
While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4920072 *||Oct 31, 1988||Apr 24, 1990||Texas Instruments Incorporated||Method of forming metal interconnects|
|US5005067 *||Mar 7, 1988||Apr 2, 1991||Fuji Xerox Co., Ltd.||Semiconductor integrated circuit|
|US5110762 *||Jul 7, 1989||May 5, 1992||Kabushiki Kaisha Toshiba||Manufacturing a wiring formed inside a semiconductor device|
|US5112765 *||Jul 16, 1991||May 12, 1992||International Business Machines Corporation||Method of forming stacked tungsten gate PFET devices and structures resulting therefrom|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US5756397 *||Aug 30, 1996||May 26, 1998||Lg Semicon Co., Ltd.||Method of fabricating a wiring in a semiconductor device|
|U.S. Classification||361/311, 257/773, 257/765, 257/752, 438/648, 438/634, 257/E21.585, 438/658, 257/763, 257/E21.583|
|International Classification||H01L23/52, H01L21/768, H01L21/3205|
|Cooperative Classification||H01L21/76877, H01L21/7684|
|European Classification||H01L21/768C2, H01L21/768C4|
|Dec 17, 1991||AS||Assignment|
Owner name: SGS-THOMSON MICROELECTRONICS, INC., TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:HUANG, KUEI-WU;REEL/FRAME:005956/0318
Effective date: 19911212
|Sep 27, 1996||FPAY||Fee payment|
Year of fee payment: 4
|Sep 29, 2000||FPAY||Fee payment|
Year of fee payment: 8
|Sep 20, 2004||FPAY||Fee payment|
Year of fee payment: 12