|Publication number||US5203957 A|
|Application number||US 07/713,508|
|Publication date||Apr 20, 1993|
|Filing date||Jun 12, 1991|
|Priority date||Jun 12, 1991|
|Publication number||07713508, 713508, US 5203957 A, US 5203957A, US-A-5203957, US5203957 A, US5203957A|
|Inventors||Chue-San Yoo, Ting-Hwang Lin, Sui-Hei Kuo|
|Original Assignee||Taiwan Semiconductor Manufacturing Company|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (11), Referenced by (54), Classifications (15), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
(1) Field of the Invention
The invention relates to the manufacture of very highly dense integrated circuits and more particularly to the method of formation of tapered contact opening to device elements of the integrated circuits.
(2) Description of the Prior Art
Insulating multilayers are normally formed over the highly dense integrated circuits which are formed in and on a semiconductor substrate. These layers are thick in comparison to the feature size of one micrometer or less of the very dense integrated circuits which are now being manufactured. This thickness cannot be scaled down proportionately in the same way the feature size is scaled down. The layers are composed of silicon oxide, silicon nitride, glasses and the like insulators.
It is necessary to make tapered contact openings through this relatively thick insulating multilayer to the device elements formed in and on the semiconductor substrate. These openings are formed by isotropic etching, anisotropic etching or a combination of these two etching techniques and heating steps to cause smoothing by flow of the insulator layer. A great amount of work and effort has been expended to find the best technique to form ideal tapered openings to the device elements. The need for tapered openings is so that the subsequent step of depositing a metal layer, for example aluminum will properly fill the opening and make an ohmic contact to the various device elements of the integrated circuit. Examples of patents that have tried to solve this problem are R.K. Berglund et al U.S. Pat. No. 4,902,377 and B. Auda U.S. Pat. No. 4,814,041.
Argon sputter etching has been known as an etching technique for many years and had been used in the past where simpler semiconductor device were being made. This process is not used today in making contact openings, because it is known that the contact resistance and other contact properties would be adversely effected.
It has been recognized in the prior art that the high temperature heating that is generally used to flow the insulating layer, typically glass to smooth the sharp edges of contact opening can do damage to the integrated circuit device elements. For example, M.T. Bohr U.S. Pat. No. 4,372,034 describes a process wherein he uses a very deep isotropic etch through the glass insulating layer and then an anisotropic etch to pass through the thin silicon dioxide layer. He says that the high temperature heating step is not now required. However, this process can only be used in the past or where very simple and large size semiconductor devices are being made, because of the very large space taken up by the isotropic etch at each opening.
The high density integrated circuit devices wherein the feature sizes are less than about one micrometer or less have created very difficult problems involving the conservation of horizontal space. Also, there is the problem of the high temperature flow of the glass insulating layer for smoothing. The high temperature flow causes device problems, such as where a refractory silicide, for example titanium silicide is used in the conventional SALICIDE process. The major device problem caused in this instant is the high temperature increase in contact resistance due to silicide degradation. The longer cycle time of manufacture is another disadvantage of the high temperature flow step.
It is an object of this invention to overcome the disadvantages of the prior art in forming tapered contact openings by use of a combination of isotropic etching, anisotropic etching and an Argon sputter etching to form ideal tapered openings without use of a high temperature flow step and while conserving horizontal space.
It is another object of this invention, for nonsilicided devices to effectively use the Argon sputter etching step in combination with the isotropic etching and anisotropic etching without resulting in an unacceptable increase in the contact resistance by following the Argon sputter etching with a short time soft reactive ion etching step to reduce the contact resistance.
The method for making a contact opening for an integrated circuit having a feature size of about one micrometer or less is accomplished by first providing an integrated circuit structure having device elements within a semiconductor substrate and multilayer insulating layers thereover. A resist masking layer is formed over the multilayer insulating layer having openings therein in the areas where the contact openings are desired. Isotropic etching is done through a desired thickness portion of multilayer insulating layer. Anisotropic etching is now done through the remaining thickness of multilayer insulating layer to the semiconductor substrate to form the desired contact opening. The resist layer is removed. The structure is subjected to an Argon sputter etching ambient to smooth the sharp corners at the upper surface of multilayer layer and the point where the isotropic etching ended and the anisotropic etching began. It is preferred that soft reactive ion etching be done for a period of less than about 30 seconds after said Argon sputter etching to reduce the increased contact resistance caused by this Argon sputter etching.
This Argon contact openings tapering has proven to be easy to control and to implement. There are no contact critical dimension variation even applied to contacts of different depths.
The resultant tapered contact openings provide excellent metal step coverage without the high temperature flow step.
FIG. 1 is a schematic cross-sectional representation of the process of the present invention after the isotropic etching and anisotropic etching steps.
FIG. 2 is a schematic cross-sectional representation of the result of depositing metallurgy into the contact openings where neither Argon sputter etching nor high temperature flow is used.
FIG. 3 is a schematic cross-sectional representation of the result of depositing metallurgy in the contact opening where a high temperature flow step is used.
FIG. 4 is a schematic cross-sectional representation of the result of depositing metallurgy in the contact opening after the Argon sputter etching step of the present invention.
FIG. 5 shows contact resistance and thermowave counts versus post treatment time.
Referring to FIG.1 there is shown a product in a stage of manufacture after the contact windows or openings have been etched by an isotropic etchant and a anisotropic etchant. The product under manufacture can be either an N-channel MOSFET, a P-channel MOSFET, a CMOS FET, bipolar transistor or combinations thereof. However, the FIG. 1 through 4 process is intended to schematically show a NMOS portion of a CMOS FET process that makes a electrical contact to both P+ and N+ source/drain regions. The substrate 10 is monocrystalline silicon and has been doped by conventional techniques to either P or N as is appropriate for the desired N-channel or P-channel MOS FET structure. An example of such a conventional process is described in the book "VLSI TECHNOLOGY" Second Edition by S. M. Sze Published by McGraw-Hill Book Co., New York, N.Y. 1988 Pages 485-487.
Source/drain regions 12, gate dielectric 13 and gate electrode 14 are formed by conventional methods as described, for example by Sze cited above in the appropriate wells of substrate 10. Conventional sidewall insulator structures 17 have been formed upon the sides of the gate dielectric 13 and gate electrode 14 for insulating purposes.
The self aligned metal silicide layer is now to be formed on the polycrystalline silicon regions 14 and the exposed source/drain monocrystalline silicon regions 12. A thin layer of metal film is deposited upon the surface of the wafer. The metals that are useful in may invention include titanium, cobalt, tantalum, molybdenum, tungsten, palladium and platinum. The metal can be deposited by sputtering or evaporation methods. It is preferably deposited by sputtering. The operational thickness is between about 300 to 1500 Angstroms and the preferred thickness is between about 800 to 1000 Angstroms. The preferred metal for this metal silicide is titanium. Alternatively, the metal silicides can be formed with chemical vapor desposition.
The structure having the metal layer formed thereover the layers 14 and source/drain regions 12 is now placed within a chamber having an inert atmosphere such as nitrogen, argon or a vacuum. The structure is heated within this chamber to react the metal with the polycrystalline silicon layer regions and the monocrystalline silicon regions to form metal silicide layers or contacts 18. The metal is left unreacted where it covers the non-silicon regions. The heating conditions for the reaction are 600° to 800° C. in a conventional furnace for about 20 to 40 minutes or in rapid thermal anneal system for 60 to 200 seconds. The unreacted portions of the metal layer are then removed by exposing the structure to an etchant selective for the metal but not reactive to the metal silicide layer or contact 18. Typical etchants are solution of ammonium hydroxide, hydrogen peroxide and DI water. After cleanup the unreacted metal film or metal nitride on the oxide surface, a second anneal either by furnace or by rapid thermal anneal at 800° to 900° C. stabilizers the metal silicide films.
An insulating layered structure composed of a layer of silicon oxide 16 and a much thicker layer of borophosphosilicate glass, phosphosilicate glass or similar insulating layer 20. The operational thicknesses of the layers are between about 1000 to 2000 Angstroms for the oxide layer and between about 4000 to 10,000 or more Angstroms for the glasseous layer. These layers are typically deposited by chemical vapor deposition in low pressure or atmospheric pressure, or in a plasma enhance reactive chamber.
The contact windows or openings 25 are now formed through the insulating layered structure to the source/drain regions 12 having refractory silicide contact 18 thereon in the device regions.
A resist masking layer (not shown) is formed over the layer 18, exposed and developed. The openings in the resist masking layer are at the desired openings or contact windows. Isotropic etching is now done using 10H20:1HF ratio buffered HF water solution. The isotropic etching produces etching in both the vertical and the horizontal directions to produce pattern 26. The isotropic etching is continued to a thickness of between about 3500 to 4500 Angstroms of the layer 20.
Anisotropic etching is now done using plasma etcher and under the conditions Fluorine based chemistry. The anisotropic etching produces etching in only the vertical direction to produce pattern 28. The anisotropic etching continues until the remaining thickness of the multilayered insulating layer is removed and the contact window or opening 25 is produced and FIG. 1 completed.
It should be noted that there are sharp edges at the top of the layer 20 at the openings 25 and at the intersection of patterns 26 and 28. The sharp corners would degrade the metal step coverage, because due to the shadowing effect one would obtain different thicknesses of metal, that is on the vertical contact sidewall there would be less metal than on the horizontal surfaces.
Referring now to FIG. 2, there is shown the results of depositing metal layers 30, 32 over the openings with out further processing. The metal step coverage problem results in an unacceptable contact to the source/drain region 12.
For 0.7 micrometer contact size, with the conventional wet+dry etching, the resultant metal step coverage is 9.6%, whereas if a 2-minute Ar sputtering is applied, the metal step coverage is improved to 52.9%; a 1-minute Ar sputtering to 39.8%.
Referring now to FIG. 3, there is shown results of a high temperature flow treatment of 850° to 950° C. for 30 to 60 minutes. There is an increase in contact resistance during the high temperature flow process due to silicided degradation. Further, the long cycle time increases cost.
Referring now more particularly to FIG. 4 wherein the solution to the problems of the prior can best be understood. The FIG. 1 structure is subjected to an Argon sputter etching ambient to smooth the sharp corners at the upper surface of the multilayer layer 16, 20 and the point where the isotropic etching ended and the anisotropic etching began, that is where patterns 26 and 28 meet.
This smoothing can be controlled depending upon the time that the Argon sputtering continues and the amount of material removed. The Ar plasma is generated with an electrical field and the Ar ion lifetime is prolonged with an magnetic field, so that during etching Ar ions etch the surface. For example, where borophosphosilicate glass is being smoothed, the etching of 500 Angstroms give metal step coverage of about 34%; 750 Angstroms give about 53%; 1000 Angstroms give about 66% and 1250 Angstroms give about 69%. Metal step coverage is defined as the ratio of thickness of the thinnest metal in contact hole to the metal thickness on horizontal area.
For nonsilicided devices, a soft reactive ion etching is preferably now used to reduce the contact resistance that is increased during the Argon sputter etching process described. The soft etching uses carbon tetrafluoride/helium (CF4/He) plasma to remove a very thin layer of the silicon surface. The Argon sputter etching was observed to have no adverse effect upon the titanium silicide integrity as revealed by thermowave counts and sheet resistance. Hence,no contact resistance increase, after the Ar sputtering is observed. Namely, no soft-etching is required.
The contact metallurgy 30, 32 consists typically of titanium (Ti)/titanium-tungsten(TiW)/alumium (Al) are now deposited by a sputtering machine and under the conditions 6 to 12 kwatts. Layer thickness range is 100 to 300 Angstroms for titanium; 1000 to 1500 Angstroms for TiW; 5000 to 9000 Angstroms for Al. The result is that good metal step coverage is found and no high temperature flow processing was needed. For purposes of the drawing the layer 30 includes the Ti/TiW and layer 32 included the Al.
The following Example is given to show the important features of the invention and to aid in the understanding thereof and variations may be made by one skilled in the art without departing from the spirit and scope of the invention.
Experiments were carried out on contacts patterned on 7500 Angstroms of borophosphosilicate glass atop 1000 Angstroms of undoped silicon oxide. The contacts were isotropically wet etched with 10 H20:1 HF buffered solution and anisotropically etched with Lam 4500 etcher with carbon tetrafluoride/trifluoromethane plasma at RF power of 750 watts with the resist masking layer in place. The resist masking layer was removed. Argon sputtering was used to etch and smooth the corners caused by the first two etching processes. The contact opening was 0.7 micrometers. The Argon sputter etching was done with an Applied Material P5000 etchback chamber. The RF power used is 400W; the magnetic field is 50 Gauss. The Argon ion preferentially etch faster along 45 degree to the horizontal plane, hence it is capable of rounding off the sharp corners on contact sidewalls. For example, for conventional wet+dry contact etching, the metal step coverage is 9.6% which is improved to 39.8% and 52.9% with a one- and two-minute Ar sputtering respectively. The metal contacts, consisting of Aluminum, silicon and copper, was deposited by ULVAC system. The power used is 12 kw; pressure at 10-8 torr.
The results of the experiments were reviewed and it was found that the Argon sputtering does not cause subthreshold leakage increase. Metal step coverage improves with Argon sputter time. For nonsilicided, a soft etching is required to decrease the contact resistance, as shown in FIG. 5 for 1.0 micrometer contact. For silicided devices the soft-etching is not needed. Typically, for a 0.8 micrometers contact, the contact resistance is around 1.4 ohm/contact.
FIG. 5 shows the 0.8 micrometer contact resistances for metal to N-substrate, P-substrate and polysubstrate contacts respectively. Also shown is the thermowave counts as measured on silicon substrate. It can be seen that, for nonsilicided devices, the contact resistance and the thermowave counts can be reduced to normal values after 30 seconds of soft etching. FIG. 5 shows the contact resistance and thermowave counts versus post treatment time which is needed for nonsilicided devices. For silicide devices, there is no contact resistance increases due to the Argon sputtering process. It shows the contact resistance, Rc increases upon Argon sputtering, but that it can be reduced to normal values with soft etching. The soft etching used in the experiments was helium, trifluoromethane and carbon tetrafluoride. The preferred time of soft etching was 35 seconds and about 150 to 300 Angstroms of silicon was removed from the surfaces of the contact openings before the metallurgy desposition.
While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4372034 *||Mar 26, 1981||Feb 8, 1983||Intel Corporation||Process for forming contact openings through oxide layers|
|US4764245 *||Feb 26, 1987||Aug 16, 1988||Siemens Aktiengesellschaft||Method for generating contact holes with beveled sidewalls in intermediate oxide layers|
|US4807016 *||Nov 20, 1987||Feb 21, 1989||Texas Instruments Incorporated||Dry etch of phosphosilicate glass with selectivity to undoped oxide|
|US4814041 *||Sep 22, 1987||Mar 21, 1989||International Business Machines Corporation||Method of forming a via-hole having a desired slope in a photoresist masked composite insulating layer|
|US4857141 *||Apr 13, 1988||Aug 15, 1989||Kabushiki Kaisha Toshiba||Method of forming holes in semiconductor integrated circuit device|
|US4902377 *||May 23, 1989||Feb 20, 1990||Motorola, Inc.||Sloped contact etch process|
|US4931411 *||Dec 20, 1988||Jun 5, 1990||Texas Instruments Incorporated||Integrated circuit process with TiN-gate transistor|
|US5104822 *||Jul 30, 1990||Apr 14, 1992||Ramtron Corporation||Method for creating self-aligned, non-patterned contact areas and stacked capacitors using the method|
|JPS5720450A *||Title not available|
|JPS5769745A *||Title not available|
|JPS61288428A *||Title not available|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US5269880 *||Apr 3, 1992||Dec 14, 1993||Northern Telecom Limited||Tapering sidewalls of via holes|
|US5346585 *||Apr 20, 1993||Sep 13, 1994||Micron Semiconductor, Inc.||Use of a faceted etch process to eliminate stringers|
|US5416048 *||Apr 16, 1993||May 16, 1995||Micron Semiconductor, Inc.||Method to slope conductor profile prior to dielectric deposition to improve dielectric step-coverage|
|US5453403 *||Oct 24, 1994||Sep 26, 1995||Chartered Semiconductor Manufacturing Pte, Ltd.||Method of beveled contact opening formation|
|US5567270 *||Oct 16, 1995||Oct 22, 1996||Winbond Electronics Corp.||Process of forming contacts and vias having tapered sidewall|
|US5612572 *||Jun 6, 1995||Mar 18, 1997||Lg Semicon Co., Ltd.||Semiconductor device with an insulation groove|
|US5629237 *||Oct 19, 1995||May 13, 1997||Taiwan Semiconductor Manufacturing Company Ltd.||Taper etching without re-entrance profile|
|US5661084 *||Oct 4, 1996||Aug 26, 1997||Taiwan Semiconductor Manufacturing Company, Ltd||Method for contact profile improvement|
|US5716872 *||Nov 27, 1995||Feb 10, 1998||Nec Corporation||Method of manufacturing multilayer interconnection structure having a dielectric film with improved flatness|
|US5723893 *||May 28, 1996||Mar 3, 1998||Taiwan Semiconductor Manufacturing Company, Ltd.||Method for fabricating double silicide gate electrode structures on CMOS-field effect transistors|
|US5756397 *||Aug 30, 1996||May 26, 1998||Lg Semicon Co., Ltd.||Method of fabricating a wiring in a semiconductor device|
|US5888901 *||Aug 5, 1996||Mar 30, 1999||Motorola, Inc.||Multilevel interconnection and method for making|
|US5892285 *||Feb 19, 1997||Apr 6, 1999||Micron Technology, Inc.||Semiconductor connection with a top surface having an enlarged recess|
|US5895271 *||Dec 27, 1995||Apr 20, 1999||Sony Corporation||Metal film forming method|
|US5915198 *||Apr 28, 1997||Jun 22, 1999||Vanguard International Semiconductor Corporation||Contact process using taper contact etching and polycide step|
|US5933754 *||Jun 13, 1997||Aug 3, 1999||Micron Technology, Inc.||Semiconductor processing method of forming an electrically conductive contact plug|
|US5940730 *||Dec 20, 1996||Aug 17, 1999||Hyundai Electronics Industries Co., Ltd.||Method of forming a contact hole of a semiconductor device|
|US5994220 *||Feb 2, 1996||Nov 30, 1999||Micron Technology, Inc.||Method for forming a semiconductor connection with a top surface having an enlarged recess|
|US6017796 *||Aug 24, 1998||Jan 25, 2000||United Semiconductor Corp.||Method of fabricating flash electrically-erasable and programmable read-only memory (EEPROM) device|
|US6043151 *||Apr 14, 1998||Mar 28, 2000||Micron Technology, Inc.||Method for forming a semiconductor connection with a top surface having an enlarged recess|
|US6066559 *||Dec 4, 1997||May 23, 2000||Micron Technology, Inc.||Method for forming a semiconductor connection with a top surface having an enlarged recess|
|US6159850 *||Aug 7, 1998||Dec 12, 2000||United Microelectronics Corp.||Method for reducing resistance of contact window|
|US6163067 *||Dec 31, 1998||Dec 19, 2000||Kabushiki Kaisha Toshiba||Semiconductor apparatus having wiring groove and contact hole in self-alignment manner|
|US6171964 *||Jan 26, 1998||Jan 9, 2001||Micron Technology, Inc.||Method of forming a conductive spacer in a via|
|US6207483||Mar 17, 2000||Mar 27, 2001||Taiwan Semiconductor Manufacturing Company||Method for smoothing polysilicon gate structures in CMOS devices|
|US6222273||Jan 30, 1998||Apr 24, 2001||Micron Technology, Inc.||System having vias including conductive spacers|
|US6245671||Feb 1, 1999||Jun 12, 2001||Micron Technology, Inc.||Semiconductor processing method of forming an electrically conductive contact plug|
|US6265317 *||Jan 9, 2001||Jul 24, 2001||Taiwan Semiconductor Manufacturing Company||Top corner rounding for shallow trench isolation|
|US6274457 *||Jan 12, 2000||Aug 14, 2001||Mitsubishi Denki Kabushiki Kaisha||Method for manufacturing an isolation trench having plural profile angles|
|US6277731||May 31, 2000||Aug 21, 2001||Micron Technology, Inc.||Method for forming a semiconductor connection with a top surface having an enlarged recess|
|US6420786||Feb 2, 1996||Jul 16, 2002||Micron Technology, Inc.||Conductive spacer in a via|
|US6426287||Jul 11, 2001||Jul 30, 2002||Micron Technology, Inc.||Method for forming a semiconductor connection with a top surface having an enlarged recess|
|US6448656||May 31, 2000||Sep 10, 2002||Micron Technology, Inc.||System including a memory device having a semiconductor connection with a top surface having an enlarged recess|
|US6565721 *||Oct 9, 1997||May 20, 2003||Micron Technology, Inc.||Use of heavy halogens for enhanced facet etching|
|US6583055 *||Jan 25, 2002||Jun 24, 2003||Powerchip Semiconductor Corp.||Method of forming stepped contact trench for semiconductor devices|
|US6762125||May 14, 2001||Jul 13, 2004||Micron Technology, Inc.||Modified facet etch to prevent blown gate oxide and increase etch chamber life|
|US6774023 *||May 28, 1993||Aug 10, 2004||Samsung Electronics Co., Ltd.||Method of manufacturing a semiconductor device having a multilayer structure including a dual-layer silicide|
|US7014887||Sep 2, 1999||Mar 21, 2006||Applied Materials, Inc.||Sequential sputter and reactive precleans of vias and contacts|
|US7244683||Dec 19, 2003||Jul 17, 2007||Applied Materials, Inc.||Integration of ALD/CVD barriers with porous low k materials|
|US7262136||Jul 8, 2004||Aug 28, 2007||Micron Technology, Inc.||Modified facet etch to prevent blown gate oxide and increase etch chamber life|
|US7544579 *||Mar 15, 2005||Jun 9, 2009||National Semiconductor Corporation||System and method for faceting the corners of a resistor protect layer to reduce vertical step height|
|US7585775||Nov 21, 2005||Sep 8, 2009||National Semiconductor Corporation||System and method for faceting a masking layer in a plasma etch to slope a feature edge|
|US7807567 *||Feb 8, 2007||Oct 5, 2010||Nec Electronics Corporation||Semiconductor device with interconnection structure for reducing stress migration|
|US7829428||Aug 26, 2008||Nov 9, 2010||National Semiconductor Corporation||Method for eliminating a mask layer during thin film resistor manufacturing|
|US7982287 *||Jul 19, 2011||National Semiconductor Corporation||System and method for faceting the corners of a resistor protect layer to reduce vertical step height|
|US20040238964 *||May 28, 2004||Dec 2, 2004||Nec Electronics Corporation||Semiconductor device with interconnection structure for reducing stress migration|
|US20040248355 *||Jul 8, 2004||Dec 9, 2004||Polinsky William A.||Modified facet etch to prevent blown gate oxide and increase etch chamber life|
|US20040256351 *||Dec 19, 2003||Dec 23, 2004||Hua Chung||Integration of ALD/CVD barriers with porous low k materials|
|US20070275554 *||Feb 8, 2007||Nov 29, 2007||Nec Electronics Corporation||Semiconductor device with interconnection structure for reducing stress migration|
|US20070278611 *||Aug 16, 2007||Dec 6, 2007||Micron Technology, Inc.||Modified Facet Etch to Prevent Blown Gate Oxide and Increase Etch Chamber Life|
|US20150137259 *||Aug 7, 2014||May 21, 2015||Hauk Han||Semiconductor device|
|DE19654560B4 *||Dec 27, 1996||Nov 10, 2005||Hyundai Electronics Industries Co., Ltd., Ichon||Verfahren zur Bildung eines Kontaktloches bei einem Halbleiterbauelement|
|EP0670590A2 *||Feb 13, 1995||Sep 6, 1995||Applied Materials, Inc.||High pressure plasma treatment method and apparatus|
|EP0948054A2 *||Mar 25, 1999||Oct 6, 1999||International Business Machines Corporation||Buried patterned conductor planes for semiconductor-on-insulator integrated circuit|
|U.S. Classification||438/640, 257/E21.576, 438/713, 204/192.37, 257/E21.252, 204/192.32, 204/192.35|
|International Classification||H01L21/768, H01L21/311|
|Cooperative Classification||H01L21/76804, H01L21/31116, H01L21/76826|
|European Classification||H01L21/768B2B, H01L21/768B8P, H01L21/311B2B|
|Jun 12, 1991||AS||Assignment|
Owner name: TAIWAN SEMICONDUCTOR MANUFATURING COMPANY, TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:YOO, CHUE-SAN;LIN, TING-HWANG;KUO, SUI-HEI;REEL/FRAME:005737/0304
Effective date: 19910530
|Jun 21, 1996||FPAY||Fee payment|
Year of fee payment: 4
|Oct 10, 2000||FPAY||Fee payment|
Year of fee payment: 8
|Sep 16, 2004||FPAY||Fee payment|
Year of fee payment: 12