Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS5212415 A
Publication typeGrant
Application numberUS 07/799,960
Publication dateMay 18, 1993
Filing dateNov 29, 1991
Priority dateNov 30, 1990
Fee statusPaid
Publication number07799960, 799960, US 5212415 A, US 5212415A, US-A-5212415, US5212415 A, US5212415A
InventorsKiyoharu Murakami, Ryosuke Matsuo
Original AssigneeKabushiki Kaisha Toshiba
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Precharge circuit
US 5212415 A
Abstract
A precharge circuit is provided with a step-up node circuit including a capacitor for delivering a drive voltage at a predetermined level to a load, and for raising the voltage level of the drive voltage so that it becomes equal to a value greater than the predetermined level by a specific value. This precharge circuit at least comprises a main P-channel MOS transistor for delivering the drive voltage at the predetermined level to the load through the step-up node circuit when a step-up input signal delivered to the step up node circuit is at a ground level, and a subsidiary P-channel MOS transistor for interrupting supply of the step-up input signal immediately before the drive voltage is raised to the predetermined level by the step-up input signal. Accordingly this precharge circuit normally operates immediately after being powered. Thus, initialization becomes unnecessary.
Images(4)
Previous page
Next page
Claims(4)
What is claimed is:
1. A precharge circuit having step-up node means including a capacitor for supplying a drive voltage having a predetermined level, for raising said drive voltage to a stepped-up voltage level which is greater by a specific value than said predetermined level and for delivering said drive voltage at said predetermined level or at said stepped-up voltage level to a load, said precharge circuit comprising:
main transistor means comprising a main P-channel metal oxide semiconductor (MOS) transistor having a gate terminal, a source terminal, a drain terminal and a substrate terminal;
subsidiary transistor means comprising a subsidiary P-channel metal oxide semiconductor (MOS) transistor having a gate terminal, a source terminal, a drain terminal and a substrate terminal;
means for connecting said drain terminal of said subsidiary transistor to said gate terminal of said main transistor;
means for connecting said source terminal of said main transistor to a positive potential power supply;
means for supplying a first input signal to said gate terminal of said subsidiary transistor; and
means for supplying said drive voltage to said source and substrate terminals of said subsidiary transistor;
said main transistor means providing said drive voltage at said predetermined level for delivery to said load through said step-up node means when a step-up input signal at ground level is input to said step-up node means;
said subsidiary transistor means turning on, due to said drive voltage being raised by said step-up input signal, immediately before said drive voltage exceeds said predetermined value and turning off due to said gate of said subsidiary transistor being input with a voltage level which is the same level as said drive voltage.
2. A precharge circuit as set forth in claim 1, which further comprises an N-channel MOS transistor having a gate terminal supplied with said first input signal, a source terminal to which a ground power supply is connected, and a drain terminal to which said drain terminal of said subsidiary transistor is connected.
3. A precharge circuit as set forth in claim 2, wherein said capacitor comprises an N-channel MOS capacitor having a first terminal supplied with said step-up input signal, and a second terminal at which said drive voltage appears.
4. A precharge circuit as set forth in claim 3, wherein when said step-up input signal is at a ground level, said first input signal serves as a positive potential supply source, and immediately before said step-up input signal rises up to a positive potential supply source level, said first input signal falls down to said ground level.
Description
BACKGROUND OF THE INVENTION

This invention relates to a precharge circuit, and more particularly to a precharge circuit used for the precharge operation of a dynamic random access memory (DRAM), etc. driven by a single power supply and having no need for initialization. The initialization mentioned above refers to a standby operation for a time period until the precharge circuit is caused to normally function after being powered.

A conventional precharge circuit used for the precharge operation of a DRAM, etc. is shown in FIG. 1. This precharge circuit comprises N-channel metal oxide semiconductor (MOS) transistors (hereinafter referred to as transistors for convenience) N1, . . . N8, N-channel MOS capacitors (hereinafter referred to as capacitors for convenience Capl, . . . Cap4, inverter circuits INV1, . . . INV3, and a NOR circuit NORl. This precharge circuit operates in such a manner that when the voltage level of an input signal provided for step-up operation as inputted to the input terminal of capacitor Cap4 is equal to a zero level irrespective of values of an input signal IN1 inputted to the drain of the transistor Nl, an input signal IN2 inputted to one end of the capacitor Capl, and an input signal IN3 inputted to the input terminal of the inventor circuit INVl, the level of the potential on the output terminal Boot becomes the power supply voltage Vcc level. However, when the voltage level of the input signal Push is equal to the power supply voltage Vcc level, the potential on the output terminal Boot is stepped up so that it is greater than Vcc +VTh, where VTh represents a threshold value of a MOS transistor.

The problems with the above-mentioned conventional precharge circuit will now be described with reference to FIG. 2. In the initial state (time t0) immediately after the precharge circuit is powered, input signals IN1, IN2 and IN3 are either at the power supply voltage Vcc level provided by a single power supply, i.e., at a high of "H" level, or at a zero level (reference level), i.e., at a low or "L" level. It is now assumed that those signals are at "H" level. Generally, capacitors Capi (i=1, . . . 4) are (electrostatically) coupled with nodes connected to respective output terminals at the points of time when input signals inputted to the respective input terminals vary, and their rise or fall operations have been completed. For this reason, at the time t0, there occurs no connection between the capacitor Capl and the node 101. As a result, the level of a potential on the node 101 connected to the source of the transistor N1 becomes equal to the level of Vcc -VTh. This potential is applied to the gates of the transistors N2 and N3. On the other hand, the node 103 connected to the output terminal of the inverter circuit INVl is placed at the in "L" level in potential because the input signal IN3 is in the state of "H" level. Accordingly, the level of potential on the node 104 connected to the output terminal of the inverter circuit INV2 becomes equal to "H" level, and the level of a potential on the node 105 connected to the output terminal of the inverter circuit INV3 becomes equal to "L" level. Since the nodes 103 and 105 connected to respective input terminals of the NOR circuit NORl are at "L" level, the node 106 connected to the output terminal of the NOR circuit NORl is held at "H" level, i.e., level of the power supply voltage Vcc. On the other hand, the node 102 connected to the drains of the transistors N3 and N4 and the gate of the. transistor N5 is kept at a potential level Vcc -VTh by the transistor N4. Further, the node 107 connected to the drains of the transistors N5 and N.sub. 6, the gate of the transistor N7, and the output terminal of the capacitor Cap3 is kept at a potential level Vcc -VTh by the transistor N6. In addition, the output terminal Boot of the precharge circuit connected to the drains of the transistors N7 and N8 and the output terminal of the capacitor Cap4 is kept at a potential level Vcc -VTh by the transistor N8.

When the input signal IN1 is caused to change or shift from "H" to "L" level at time t1, the transistor N1 is placed in an OFF state. As a result, while the node 101 is seemingly at a potential level of Vcc -VTh, it is actually in a floating state (also referred to as H floating (high-floating) in this case). Thereafter, at time t2, when the input signal IN2 is caused to shift from "H" to "L" level, the capacitor Cap1 is (electrostatically) coupled with the node 101. As a result, the level of potential on the node 101 shifts from the level Vcc -VTh to "L" level, but the levels of potentials on the other nodes, e.g., the level of potential on the node 107 or the output terminal Boot remain at the previous level. Further, at time t3, when the input signal IN3 is caused to shift from "H" to "L" level, the level of a potential on the node 103 shifts to "H" level and the level of potential on the node 106 shifts to "L" level, and the capacitor Cap2 is coupled with the node 102. Thus, the potential level of the node 102 is stepped up, so a level of a potential on of node 102 becomes equal to a value of Vcc -VTh or more. For this reason, the level of the potential on the node 107 connected to the drain of the transistor N5 becomes equal to the Vcc level. At this time (time t3), when the level of the input signal Push is caused to shift from "L" to "H" level, the capacitor Cap4 is (electrostatically) coupled with the output terminal Boot, so the level of voltage (potential) on the output terminal Boot is stepped up. Namely, when the input signal Push is at "L" level a potential, the level of a potential on the output terminal Boot is equal to Vcc -Vth, while when the input signal Push is at "H" level, the level of potential on the output terminal Boot is equal to Vcc. In other words, when the input signal Push is at "L" level, a normal output of the precharge circuit does not exceed the level Vcc. Further, when the input signal Push is at "H" level, the level of the normal output of the precharge circuit does not exceed a level of more than Vcc +VTh. For this reason, it is required to carry out initialization as shown below.

At time t4, the level of the input signal IN1 is caused to shift from "L" to "H" level, and the level of the input signal Push is caused to shift from "H" to "L" level. As a result, the node 101 is kept at the level Vcc -VTh by the transistor N1, and the output terminal Boot is kept also at the level Vcc -VTh. Thereafter, at time t5, when the level of the input signal IN2 is caused to shift from "L" to "H" level, the capacitor Cap1 is coupled with the node 101. As a result, the level of voltage (potential) on the node 101 is stepped up to a certain level more than Vcc +VTh. Further, at time t6, When the potential level of the input signal IN3 is caused to shift from "L" to "H" level, the node 103 is kept at "L" level by the inverter circuit INV1, so the capacitor Cap2 is coupled with the node 102. At this time, since the level of potential on the node 101 is above Vcc +VTh, the node 102 is kept at the level Vcc by the transistor N3. On the other hand, the level of potential on the node 106 connected to the output terminal of the NOR circuit NORl shifts from "L" to "H" level. Thus, the capacitor Cap3 is coupled with the node 107, so the level of voltage (potential) on the node 107 is stepped up to a certain level above Vcc +VTh. Accordingly, the output terminal Boot is kept at the level Vcc by the transistor N7.

When the level of the input signal IN1 is caused to shift from "H" to "L" level at time t7, and the level of the input signal IN2 is caused to shift from "H" to "L" level at time t8, the level of voltage (potential) on the node 101 is stepped or dropped down to a certain level below Vcc -VTh by the capacitor Capl. Thereafter, at time t9, when the potential level of the input signal IN3 is caused to shift from "H" to "L" level, the level of potential on the node 103 is allowed to shift from "L" to "H" level by the inverter circuit INV1, and the level of potential on the node 106 is caused to shift from "H" to "L" level by the inverter circuits INV2 and INV3 and the NOR circuit NORl. Accordingly, the capacitor Cap2 is coupled with the node 102, and the capacitor Cap3 is coupled with the node 107. Thus, the level of voltage (potential) on the node 102 is stepped up by the capacitor Cap2 from the level Vcc to a certain level above Vcc +VTh, and the level of voltage (potential) on the node 107 is dropped down by the capacitor Cap3 to the level Vcc. At this time (time t9), when the potential level of the input signal Push is caused to shift from "L" to "H" level, the level of voltage (potential) on the output terminal Boot is stepped up from the level Vcc to a certain level above Vcc +VTh.

Thereafter, when the potential levels of the input signals IN1, IN2 and IN3 are respectively caused to shift from "L" to "H" level at times t10, t11 and t12, and the level of the input signal Push is caused to shift from "H" to "L" at time t10, the output terminal Boot of the precharge circuit is held at the level Vcc.

As described above, in the conventional precharge circuit, immediately after being powered, the level of potential on the output terminal Boot is below Vcc -VTh. At this time, even if the potential level of the input signal Push shifts from "L" to "H" level, the level of potential on the output terminal Boot becomes equal to Vcc. Namely, this level is lower than a normal level (above Vcc +VTh). That potential level is conspicuously dropped by greater degree according to the power supply voltage becoming smaller. As a result, there was the possibility that a device using such a precharge circuit, e.g., a DRAM might be erroneously operated.

Further, it is necessary to carry out initialization in order to provide a normal output level, but the node 101 is in a floating state as previously described for a time period from the time t1 to the time t2. Generally, such a node in the floating state may be apt to follow other nodes because of the coupling, etc., causing erroneous operation of the precharge circuit.

SUMMARY OF THE INVENTION

This invention has been made in consideration of the above-mentioned problems, and its object is to provide a precharge circuit capable of normally operating without the necessity of carrying out initialization.

The precharge circuit of this invention comprises a first P channel MOS transistor having a gate terminal supplied with a first input signal, and a source terminal and a substrate terminal supplied with an output signal; an N-channel MOS .transistor having a gate terminal supplied with the first input signal, a source terminal to which the ground of a power supply is connected, and a drain terminal to which a drain terminal of the first P-channel MOS transistor is connected; and a second P-channel MOS transistor having a gate terminal to which the drain terminal of the. first P-channel MOS transistor is connected, a source terminal to which a positive potential supply source is connected, and a drain terminal and a substrate terminal, supplied with the output signal.

In accordance with the precharge circuit thus constructed, a .first input signal is inputted to the input terminal of a CMOS inverter comprised of the first P-channel MOS transistor and the N channel MOS transistor. As a result, an output of the CMOS inverter is delivered to the gate terminal of the second P-channel MOS transistor. Thus, when the drain terminal of the second P-channel MOS transistor is used as the output terminal of the precharge circuit of this invention, the precharge circuit of this invention normally operates immediately after it is powered. For this reason, initialization as required in the prior art becomes unnecessary.

In accordance with this invention, the precharge circuit may normally operate without carrying out initialization.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIG. 1 is a circuit diagram showing a conventional precharge circuit;

FIG. 2 is a time chart for explaining the operation of the conventional precharge circuit shown in FIG. 1;

FIG. 3 is a circuit diagram showing a precharge circuit according to an embodiment of this invention; and

FIG. 4 is a time chart for explaining the operation of the precharge circuit shown in FIG. 3.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

An embodiment of a precharge circuit according to this invention is shown in FIG. 3. The precharge circuit of this embodiment comprises a CMOS inverter, comprised of an N-channel MOS transistor (hereinafter simply referred to as a transistor) N1 and a P-channel MOS transistor (hereinafter simply referred to as a transistor) P1, a P-channel MOS transistor P2, and an N-channel MOS capacitor (hereinafter referred to as a capacitor) Cap1. The source terminal of the transistor P2 is connected to the power supply voltage Vcc terminal, and the drain terminal thereof is connected to the substrate terminal and is also connected to the source terminal of the transistor P1 of the CMOS inverter. Further, the gate terminal of the transistor P2 is connected to an intermediate node 11 of the transistors P1 and N1, which serves as an output terminal of the CMOS inverter. One end (output terminal) of the capacitor Cap1 is connected to the output terminal Boot together with the drain terminal of the transistor P2. Further, a ground potential Vss (=0) is applied to the source terminal of the transistor N1 of the CMOS inverter, and an input signal IN1 is applied to the gates of the transistors P1 and N1. In addition, another input signal Push is applied to the input terminal of the capacitor Cap1.

The operation of the above-described precharge circuit will now be described with reference to FIG. 4. In the initial state immediately after the precharge circuit is powered (time t0), it is now assumed that the input signal IN1 is at the level Vcc, i.e., in "H" level state, and the input signal Push is at zero level, i.e., in "L" level state. At this time, the transistors P1 and N1 constituting the CMOS inverter are turned OFF and ON, respectively. As a result, the potential level of the node 11 becomes equal to the ground level Vss, i.e., "L" level. Thus, the transistor P2 is turned ON, so the potential level of the output terminal Boot becomes equal to Vcc level. Thereafter, when the level of the input signal IN1 shifts to "L" level at time t1 (>t0), the transistor IN1 is turned OFF and the transistor P1 is turned ON. Thus, the potential level of the node 11 shifts from "L" to "H" level, so the transistor P2 is turned OFF. However, since the output terminal Boot is connected also to the substrate terminal, its potential level is unchanged to maintain the state Vcc.

When the level of the input signal Push changes from "L" to "H" at time t2 (>t1), the capacitor Capl is coupled with the output terminal Boot to step up the potential level of the output terminal Boot so that it is above the level Vcc +VTh. At this time, the node 11 is charged so that its level becomes equal to substantially the same level as the level of the output terminal Boot through the transistor P1. Thus, there is no possibility that charges on the output terminal Bopt are discharged to the power supply connected on the source side of the transistor P2 through the transistor P2.

Thereafter, at time t3, when the level of the input signal IN1 is caused to shift from "L" to "H" level, and the level of the input signal Push is caused to shift from "H" to "L" level, the transistors P1 and N1 are turned OFF and ON, respectively. As a result, the potential level of the node 11 shifts to "L" level. Thus, the transistor P2 is turned ON, so the level of the output terminal Boot becomes equal to Vcc.

As described above, the precharge circuit of this embodiment can normally operate immediately after being powered. Thus, initialization becomes unnecessary.

It is to be noted that since a CMOS inverter is used, no node is placed in a high-floating state.

In addition, the circuit configuration of the precharge circuit according to this invention becomes is simpler than that of the conventional precharge circuit.

As will be understood from the above description, this invention aims at stepping up a voltage level Vcc from a single power supply to a specific level higher by the threshold value VTh in order to drive a load such as a DRAM, etc. The technology for realizing this by using the configuration of the present P-channel MOS transistor P2 has been not disclosed until now. Only the prior technology using the above N-channel transistor configuration rather than the P-channel transistor P2 configuration had been conventionally proposed. However, with an approach which merely replaces the N-channel transistor by the P-channel transistor P2, there was considerable difficulty in that, when the potential level of the output terminal Boot reaches the power supply voltage level Vcc, discharge begins from the sub-terminal of the transistor P2, so a desired voltage level above "Vcc +VTh " cannot be maintained. For this reason, this invention employs a novel configuration and technique such that the P-channel MOS transistor P1 is turned on immediately before the output drive voltage Boot exceeds the predetermined voltage V.sub. cc due to the drive voltage Boot being raised by the step-up input signal Push, and is turned off when the gate voltage of the P-channel MOS transistor P1 becomes the same as the drive voltage Boot.

Thus, this invention is characterized by the provision of a main P-channel MOS transistor for raising the dive voltage level up to the power supply voltage level Vcc which serves as a reference, and the provision of a subsidiary P-channel MOS transistor for interrupting the action of the step-up input voltage in order to eliminate the problem in which discharge starts when the main transistor reaches the Vcc level.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US5021686 *Jan 25, 1990Jun 4, 1991Hitachi, Ltd.Logic circuit
US5029282 *Dec 14, 1989Jul 2, 1991Kabushiki Kaisha ToshibaVoltage regulator circuit
Non-Patent Citations
Reference
1IBM Tech. Disc. Bul. vol. 31 No. 1 Jun. 1988 "Circuit for pumping current out of a negative substrate".
2 *IBM Tech. Disc. Bul. vol. 31 No. 1 Jun. 1988 Circuit for pumping current out of a negative substrate .
3IBM Tech. Discl Bul. vol. 29 No. 1, Jun. 1986 "Charge Pump Circuit for a CMOS Substrate Generator".
4 *IBM Tech. Discl Bul. vol. 29 No. 1, Jun. 1986 Charge Pump Circuit for a CMOS Substrate Generator .
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US5266842 *Aug 4, 1992Nov 30, 1993Samsung Electronics Co., Ltd.Charge pump circuit for a substrate voltage generator
US5644266 *Nov 13, 1995Jul 1, 1997Chen; Ming-JerDynamic threshold voltage scheme for low voltage CMOS inverter
US5828259 *Nov 18, 1996Oct 27, 1998International Business Machines CorporationMethod and apparatus for reducing disturbances on an integrated circuit
US6060948 *Jun 11, 1998May 9, 2000Stmicroelectronics S.R.L.Protection circuit for controlling the gate voltage of a hv LDMOS transistor
US6366141 *Oct 17, 2000Apr 2, 2002Oki Electric Industry Co, Ltd.Semiconductor driver circuit utilizing substrate voltage control
US6492866 *Apr 22, 1998Dec 10, 2002Koninklijke Philips Electronics N.V.Electronic circuit with bulk biasing for providing accurate electronically controlled resistance
Classifications
U.S. Classification327/390, 327/306, 327/534, 327/231
International ClassificationG11C11/409, H03K19/094, G11C11/4094
Cooperative ClassificationG11C11/4094
European ClassificationG11C11/4094
Legal Events
DateCodeEventDescription
Nov 29, 1991ASAssignment
Owner name: KABUSHIKI KAISHA TOSHIBA, JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:MURAKAMI, KIYOHARU;MATSUO, RYOSUKE;REEL/FRAME:005946/0912
Effective date: 19911115
Sep 24, 1996FPAYFee payment
Year of fee payment: 4
Sep 28, 2000FPAYFee payment
Year of fee payment: 8
Sep 22, 2004FPAYFee payment
Year of fee payment: 12