|Publication number||US5237219 A|
|Application number||US 07/880,908|
|Publication date||Aug 17, 1993|
|Filing date||May 8, 1992|
|Priority date||May 8, 1992|
|Also published as||DE69304404D1, EP0569136A2, EP0569136A3, EP0569136B1|
|Publication number||07880908, 880908, US 5237219 A, US 5237219A, US-A-5237219, US5237219 A, US5237219A|
|Inventors||Richard G. Cliff|
|Original Assignee||Altera Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (6), Referenced by (90), Classifications (13), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention relates to methods and apparatus for programming cellular programmable logic integrated circuits such as field programmable gate arrays ("FPGAs") and many kinds of programmable logic devices ("PLDs").
Extremely powerful and flexible cellular programmable logic circuit architectures are known as shown, for example, by commonly assigned, co-pending application Ser. Nos. 754,017, filed Sep. 3, 1991, and 880,942, filed May 8, 1992, both of which are hereby incorporated by reference herein. These architectures include large numbers of logic modules, each of which is programmable to perform any of several relatively elementary logic functions. An extensive network of conductors is provided for programmably interconnecting these logic modules in order to provide much more complex logic functions. These logic circuits include very large numbers of programmable elements. Each logic module has a substantial number of these elements, and the interconnection network also requires many such elements to produce the desired interconnections between logic modules.
A typical technique for programming the programmable elements in devices of the type described above is to employ shift registers as shown, for example, in Wahlstrom U.S. Pat. No. 3,473,160 and Freeman U.S. Pat. No. 4,870,302. Each shift register stage controls an associated logic or switching element. Programming data is shifted through the shift register or registers until the data desired for controlling each logic or switching element is stored in the shift register stage associated with that element. A disadvantage of this approach is that shift registers are relatively complex and require substantial numbers of conductors for interstage data transfer, clocking, etc. Thus in complex logic circuit structures, the shift register approach to programming may take up excessive space and other resources, and may even become a limiting factor in the design of the device. The testing of shift register programmed devices is also relatively cumbersome because the shift register can only be tested by shifting data all the way through it. If, as is common in very complex logic circuits, the shift registers are long, it may take a relatively long time to shift test data through them.
In view of the foregoing, it is an object of this invention to provide improved techniques for programming cellular programmable logic circuits.
It is a more particular object of the invention to simplify the structures used for programming cellular programmable logic circuits.
It is still another more particular object of this invention to provide cellular programmable logic circuit programming techniques which facilitate testing of the device.
These and other objects of the invention are accomplished in accordance with the principles of the invention by connecting multiple programmable elements in a cellular programmable logic integrated circuit in a series in which the serial interconnections are controlled by addressable switches. The first addressable switch in each series is connected to a data source such as one element of a data register. The output of the last programmable element in each series may be connected to a test point such as one element of a test register. To test the operation of each series, all of the programmable switches are turned on. If all of the programmable elements in the series are working properly, data from the data source will flow through the series and appear at the test point. This will not happen if any programmable element in the series is defective.
The programmable elements in the series are programmed one after another starting with the one which is most remote from the data source. This most remote element is programmed by turning on all the programmable switches and having the data source supply the data desired for storage in the most remote programmable element. Because all of the programmable switches are on, this data flows through all of the programmable elements to the most remote one. The programmable switch just upstream from the most remote programmable element is then turned off and the data source supplies the data desired for storage in the second-most-remote programmable element. This data flows through the series of programmable elements to the second-most-remote programmable element. The most remote programmable element is unaffected and continues to store the previously applied data because the programmable switch upstream from it has been turned off. The programmable switch upstream from the second-most-remote programmable element is now turned off and the data source supplies the data to be stored in the third-most-remote programmable element. This process continues until the desired data has been stored in all of the programmable elements and all of the programmable switches have been turned off. Any number of series of programmable elements can be programmed at the same time in parallel.
It will be apparent that the above-described methods and apparatus eliminate the need for separate shift registers for each series of programmable elements, thereby simplifying the programming structure. In addition, testing of the programmable elements is greatly facilitated by initially passing data through several programmable elements connected in series in order to simultaneously and virtually instantaneously test all of those programmable elements.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.
FIG. 1 is a simplified schematic block diagram of an illustrative cellular programmable logic integrated circuit constructed in accordance with the principles of this invention.
FIG. 2 is a schematic diagram of a programmable element which can be used in the circuit of FIG. 1
FIG. 3 is a schematic diagram showing how a plurality of programmable elements of the type shown in FIG. 2 can be interconnected and controlled in accordance with this invention.
FIG. 1 shows a cellular programmable logic integrated circuit 10 of a type shown in abovementioned application Ser. No. 880,942, with added features in accordance with the present invention. Although this particular type of circuit is shown herein for purposes of illustration, it will be understood that the principles of this invention are equally applicable to a wide variety of programmable logic circuits such as field programmable gate arrays ("FPGAs") and programmable logic devices ("PLDs"), all of which are referred to generically herein as cellular programmable logic circuits.
Circuit 10 includes a main logic portion 12, a data register 14, an address register 16, and a test register 18. Main portion 12 includes 132 logic array blocks or LABs 20 arranged in six rows of 22 LABs per row. Each LAB includes eight logic modules 24. Each logic module can be programmed to perform a desired relatively elementary logic function. For example, each logic module may include a look up table for providing any desired output in response to any one of the 16 possible combinations of four inputs. More complex logic functions can be performed by using a programmable network of conductors (not shown) to interconnect the individual logic modules and LABs in any of a wide variety of ways. More detail regarding the main portion 12 of circuit 10 will be found in the immediately above-mentioned reference, but these details are not necessary for understanding or practicing the present invention. It is sufficient to appreciate that main portion 12 (like many other devices of this general type) has many elements (called function control elements or FCEs in the immediately above-mentioned reference) requiring programming. For example, each of the above-mentioned look up tables has 16 programmable elements. Additional programmable elements may be used for many other purposes throughout the circuit such as selecting the interconnections to be made between logic modules 24 and LABs 20, controlling switches within the logic modules and LABs, determining whether logic modules will register or simply pass through data, etc. In a circuit of the size and type described above there could easily be over 300 rows and over 700 columns of programmable elements.
FIG. 2 shows a typical programmable element 30 which can be used in circuit 10. Programmable element 30 is a conventional static random access memory or SRAM element. Data is applied to terminal 32. N-channel transistor 34 can be turned on by a suitable address signal applied to terminal 36. When transistor 34 is turned on, the data applied to terminal 32 is applied to the input terminal of relatively strong inverter 38. Relatively weak inverter 40, connected in a feedback relationship with inverter 38, is not strong enough to prevent inverter 38 from responding to the data from terminal 32, but is strong enough to maintain inverter 38 in whatever state it is placed by the terminal 32 data when transistor 34 is turned off again. Accordingly, programmable element 30 stores the data applied to it. That data is available (in inverted form) at terminal 42.
In order to avoid having to provide a separate data input conductor to each of the large number of programmable elements typically required in field programmable gate array circuits of the type shown in FIG. 1, subsets of these programmable elements are connected in series in accordance with this invention as shown in FIG. 3. Two representative series are shown in FIG. 3 with vertical alignment. The first of these series includes data register element 32A, programmable elements 30A1 through 30An, and test register element 50A. The second series includes data register element 32B, programmable elements 30B1 through 30Bn, and test register element 50B. Elements 32 collectively comprise data register 14 in FIG. 1 and, if desired, may form a shift register as suggested by the arrows extending from left to right. Elements 50 collectively comprise test register 18 in FIG. 1 and may also be connected to one another to form a shift register if desired. All of transistors 34A1, 34B1, etc., are controlled by address register element 36/1 via address conductor 37/1. All of transistors 34A2, 34B2, etc., are controlled by address register element 36/2 via address conductor 37/2. This sharing of address elements continues to the ends of the series. Elements 36 collectively comprise address register 16 in FIG. 1, which may also be a shift register as suggested by the arrows from the bottom to the top in FIG. 3.
In typical operation, test data is first loaded into data register 14, and all of transistors 34 are rendered conducting by appropriate address information in address register 16. With all of programmable elements 30A connected in series and all of transistors 34A conducting, the data in data register elements 32A passes through elements 30A to test register element 50A, assuming that all of elements 30A are operating properly. (The data received by element 50A will be inverted if n is odd or uninverted if n is even.) The B series similarly passes data from data register element 32B to test register element 50B. Accordingly, the proper replication of the data register data in test register 18 indicates that programmable elements 30 are operating properly, at least to the extent that they are able to receive and pass on data. If any series of elements 30 is not operating properly to this extent, that will be indicated by the failure of the associated test register element 50 to receive the intended data from the associated data register element 32. Each series of programmable elements 30 may be tested with data of both polarities. If registers 14 and 18 are shift registers, the desired data may be shifted into data register 14 from left to right, and shifted out of test register 18, also from left to right.
After testing as described above, data can be stored in programmable elements 30 as will now be described. Programmable elements 30An, 30Bn, etc., are the first to store data. This is done by loading the desired data (or its complement, depending on the number of inverter stages above the programmable elements to receive the data) in data register 14. All of transistors 34A1-34An, 34B1-34Bn, etc., are turned on by appropriate address information stored in address register 16. The data in each data register element 32 therefore passes through all of the associated programmable elements 30 to the bottom-most element 30An, 30Bn, etc. The transistors 34An, 34Bn, etc., immediately above elements 30An, 30Bn, etc., are then turned off by an appropriate change in the address information in address element 36/n in order to latch the data into elements 30An, 30Bn, etc.
The next programmable elements to store data are elements 30An-1, 30Bn-1, etc. The desired data is loaded in register 14. All of transistors 34 are turned on except transistors 34An, 34Bn, etc. This transfers the data from register 14 to elements 30An-1, 30Bn-1, etc. This data is latched into these programmable elements by turning off transistors 34An-1, 34Bn-1, etc.
The foregoing process is repeated, working up the series of programmable elements 30 as viewed in FIG. 3, until data has been stored in all of the programmable elements. This process may be facilitated by constructing address register 16 as a shift register and gradually filling it up with zeros from the bottom to the top as viewed in FIG. 3 in order to progressively turn off transistors 34 (assuming that zeros in register 16 turn off transistors 34). The data stored in each programmable element 30 is available at the associated terminal 44 for use in controlling a look up table element, a switch, or any other programmable function in the associated field programmable gate array 10. For example, referring to above-mentioned application Ser. No. 880,942, the signals applied to terminals 44 can be variously used as the outputs of FCEs 44 (FIG. 4), as the outputs of FCEs 51 and 57 (FIG. 2), etc.
It will be understood that the foregoing is merely illustrative of the principles of this invention, and that various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention. For example, although the invention has been illustrated in the context of a particular cellular programmable logic circuit architecture, it will be understood that the invention is equally applicable to many other types of cellular programmable logic circuits.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4805139 *||Oct 22, 1987||Feb 14, 1989||Advanced Micro Devices, Inc.||Propagating FIFO storage device|
|US4864544 *||Nov 17, 1988||Sep 5, 1989||Advanced Micro Devices, Inc.||A Ram cell having means for controlling a bidirectional shift|
|US5021689 *||Jan 16, 1990||Jun 4, 1991||National Semiconductor Corp.||Multiple page programmable logic architecture|
|US5055710 *||May 9, 1990||Oct 8, 1991||Hitachi, Ltd.||Integrated logic circuit having plural input cells and flip-flop and output cells arranged in a cell block|
|US5065363 *||Jan 7, 1991||Nov 12, 1991||Hitachi, Ltd.||Semiconductor storage device|
|US5095462 *||May 25, 1990||Mar 10, 1992||Advanced Micro Devices, Inc.||Fifo information storage apparatus including status and logic modules for each cell|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US5442306 *||Sep 9, 1994||Aug 15, 1995||At&T Corp.||Field programmable gate array using look-up tables, multiplexers and decoders|
|US5459342 *||Nov 2, 1993||Oct 17, 1995||Kabushiki Kaisha Toshiba||Field programmable gate array with spare circuit block|
|US5521833 *||Oct 28, 1992||May 28, 1996||Siemens Aktiengesellschaft||Method for programming programmable integrated circuits|
|US5543730 *||May 17, 1995||Aug 6, 1996||Altera Corporation||Techniques for programming programmable logic array devices|
|US5548228 *||Sep 28, 1994||Aug 20, 1996||Altera Corporation||Reconfigurable programmable logic device having static and non-volatile memory|
|US5548552 *||May 31, 1995||Aug 20, 1996||Altera Corporation||Reconfigurable programmable logic device|
|US5654649 *||Jul 12, 1995||Aug 5, 1997||Quicklogic Corporation||Programmable application specific integrated circuit employing antifuses and methods therefor|
|US5675589 *||Apr 30, 1996||Oct 7, 1997||Xilinx, Inc.||Programmable scan chain testing structure and method|
|US5680061 *||Nov 12, 1996||Oct 21, 1997||Altera Corporation||Techniques for programming programmable logic array devices|
|US5682106 *||Sep 18, 1996||Oct 28, 1997||Quicklogic Corporation||Logic module for field programmable gate array|
|US5694249 *||Oct 3, 1995||Dec 2, 1997||Central Glass Company, Limited||Three-dimensional optical memory element and method of writing information therein|
|US5696455 *||Aug 19, 1996||Dec 9, 1997||Altera Corporation||Reconfigurable programmable logic device|
|US5705938 *||Sep 5, 1995||Jan 6, 1998||Xilinx, Inc.||Programmable switch for FPGA input/output signals|
|US5737612 *||Sep 30, 1994||Apr 7, 1998||Cypress Semiconductor Corp.||Power-on reset control circuit|
|US5751163 *||Apr 16, 1996||May 12, 1998||Lattice Semiconductor Corporation||Parallel programming of in-system (ISP) programmable devices using an automatic tester|
|US5796750 *||Aug 13, 1996||Aug 18, 1998||Lattice Semiconductor Corporation||Method for programming a programmable logic device in an automatic tester|
|US5804960||Sep 27, 1996||Sep 8, 1998||Actel Corporation||Circuits for testing the function circuit modules in an integrated circuit|
|US5809312 *||Sep 2, 1997||Sep 15, 1998||Cypress Semiconductor Corp.||Power-on reset control circuit|
|US5825197 *||Nov 1, 1996||Oct 20, 1998||Altera Corporation||Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices|
|US5859562 *||Dec 24, 1996||Jan 12, 1999||Actel Corporation||Programming circuit for antifuses using bipolar and SCR devices|
|US5867422 *||Aug 8, 1995||Feb 2, 1999||University Of South Florida||Computer memory chip with field programmable memory cell arrays (fpmcas), and method of configuring|
|US5892684 *||Jul 14, 1997||Apr 6, 1999||Quicklogic Corporation||Programmable application specific integrated circuit employing antifuses and methods therefor|
|US5896329 *||Jun 25, 1998||Apr 20, 1999||Xilinx, Inc.||Repairable memory cell for a memory cell array|
|US5910732 *||Mar 12, 1997||Jun 8, 1999||Xilinx, Inc.||Programmable gate array having shared signal lines for interconnect and configuration|
|US5940345 *||Dec 12, 1997||Aug 17, 1999||Cypress Semiconductor Corp.||Combinational logic feedback circuit to ensure correct power-on-reset of a four-bit synchronous shift register|
|US5962910 *||Jul 17, 1997||Oct 5, 1999||Actel Corporation||Metal-to-metal via-type antifuse|
|US5995419 *||Dec 15, 1998||Nov 30, 1999||Xilinx, Inc.||Repairable memory cell for a memory cell array|
|US6011406 *||Feb 20, 1998||Jan 4, 2000||Altera Corporation||Ultra-fast configuration mode for a programmable logic device|
|US6028445 *||Dec 30, 1997||Feb 22, 2000||Xilinx, Inc.||Decoder structure and method for FPGA configuration|
|US6034536 *||Dec 1, 1997||Mar 7, 2000||Altera Corporation||Redundancy circuitry for logic circuits|
|US6037800 *||Mar 16, 1999||Mar 14, 2000||Xilinx, Inc.||Method for programming a programmable gate array having shared signal lines for interconnect and configuration|
|US6072332 *||Feb 13, 1998||Jun 6, 2000||Altera Corporation||Variable depth memories for programmable logic devices|
|US6091258 *||Nov 3, 1999||Jul 18, 2000||Altera Corporation||Redundancy circuitry for logic circuits|
|US6107820 *||May 20, 1998||Aug 22, 2000||Altera Corporation||Redundancy circuitry for programmable logic devices with interleaved input circuits|
|US6128215 *||Mar 11, 1998||Oct 3, 2000||Altera Corporation||Static random access memory circuits|
|US6128692 *||Jun 11, 1998||Oct 3, 2000||Altera Corporation||Programming and verification address generation for random access memory blocks in programmable logic array integrated circuit devices|
|US6157210 *||May 21, 1998||Dec 5, 2000||Altera Corporation||Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits|
|US6160418 *||Jan 14, 1999||Dec 12, 2000||Xilinx, Inc.||Integrated circuit with selectively disabled logic blocks|
|US6160420||Nov 12, 1996||Dec 12, 2000||Actel Corporation||Programmable interconnect architecture|
|US6166559 *||May 9, 2000||Dec 26, 2000||Altera Corporation||Redundancy circuitry for logic circuits|
|US6172520||Feb 12, 1999||Jan 9, 2001||Xilinx, Inc.||FPGA system with user-programmable configuration ports and method for reconfiguring the FPGA|
|US6184705||Dec 2, 1997||Feb 6, 2001||Altera Corporation||Techniques for programming programmable logic array devices|
|US6191608||May 5, 1997||Feb 20, 2001||Altera Corporation||Techniques for programming programmable logic array devices|
|US6201404||Apr 20, 1999||Mar 13, 2001||Altera Corporation||Programmable logic device with redundant circuitry|
|US6222382||Mar 17, 2000||Apr 24, 2001||Altera Corporation||Redundancy circuitry for programmable logic devices with interleaved input circuits|
|US6301695||Jan 14, 1999||Oct 9, 2001||Xilinx, Inc.||Methods to securely configure an FPGA using macro markers|
|US6305005||Jan 14, 1999||Oct 16, 2001||Xilinx, Inc.||Methods to securely configure an FPGA using encrypted macros|
|US6324676||Jan 14, 1999||Nov 27, 2001||Xilinx, Inc.||FPGA customizable to accept selected macros|
|US6337578||Feb 28, 2001||Jan 8, 2002||Altera Corporation||Redundancy circuitry for programmable logic devices with interleaved input circuits|
|US6344755||Oct 18, 2000||Feb 5, 2002||Altera Corporation||Programmable logic device with redundant circuitry|
|US6353551||Nov 19, 1999||Mar 5, 2002||Altera Corporation||Static random access memory circuits|
|US6357037||Jan 14, 1999||Mar 12, 2002||Xilinx, Inc.||Methods to securely configure an FPGA to accept selected macros|
|US6381732||Aug 7, 2001||Apr 30, 2002||Xilinx, Inc.||FPGA customizable to accept selected macros|
|US6384630||Jan 12, 2001||May 7, 2002||Altera Corporation||Techniques for programming programmable logic array devices|
|US6407576||Mar 2, 2000||Jun 18, 2002||Altera Corporation||Interconnection and input/output resources for programmable logic integrated circuit devices|
|US6481000||Jun 29, 2000||Nov 12, 2002||Altera Corporation||Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits|
|US6614261||Jan 14, 2002||Sep 2, 2003||Altera Corp||Interconnection and input/output resources for programable logic integrated circuit devices|
|US6654889||Feb 19, 1999||Nov 25, 2003||Xilinx, Inc.||Method and apparatus for protecting proprietary configuration data for programmable logic devices|
|US6842039||Oct 21, 2002||Jan 11, 2005||Altera Corporation||Configuration shift register|
|US6894533||Jun 9, 2003||May 17, 2005||Altera Corporation||Interconnection and input/output resources for programmable logic integrated circuit devices|
|US6897678||Sep 25, 2002||May 24, 2005||Altera Corporation||Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits|
|US6972987||May 27, 2004||Dec 6, 2005||Altera Corporation||Techniques for reducing power consumption in memory cells|
|US6989689||May 24, 2004||Jan 24, 2006||Altera Corporation||Interconnection and input/output resources for programmable logic integrated circuit devices|
|US6996713||Mar 29, 2002||Feb 7, 2006||Xilinx, Inc.||Method and apparatus for protecting proprietary decryption keys for programmable logic devices|
|US7111110||Dec 10, 2002||Sep 19, 2006||Altera Corporation||Versatile RAM for programmable logic device|
|US7112992||Dec 8, 2004||Sep 26, 2006||Altera Corporation||Configuration shift register|
|US7134025||May 14, 2002||Nov 7, 2006||Xilinx, Inc.||Methods and circuits for preventing the overwriting of memory frames in programmable logic devices|
|US7162644||Mar 29, 2002||Jan 9, 2007||Xilinx, Inc.||Methods and circuits for protecting proprietary configuration data for programmable logic devices|
|US7200235||May 17, 2002||Apr 3, 2007||Xilinx, Inc.||Error-checking and correcting decryption-key memory for programmable logic devices|
|US7219237||May 17, 2002||May 15, 2007||Xilinx, Inc.||Read- and write-access control circuits for decryption-key memories on programmable logic devices|
|US7310757||Oct 10, 2002||Dec 18, 2007||Altera Corporation||Error detection on programmable logic resources|
|US7317332||Nov 7, 2005||Jan 8, 2008||Altera Corporation||Interconnection and input/output resources for programmable logic integrated circuit devices|
|US7328377||Jan 27, 2004||Feb 5, 2008||Altera Corporation||Error correction for programmable logic integrated circuits|
|US7343470||Sep 26, 2003||Mar 11, 2008||Altera Corporation||Techniques for sequentially transferring data from a memory device through a parallel interface|
|US7366306||May 17, 2002||Apr 29, 2008||Xilinx, Inc.||Programmable logic device that supports secure and non-secure modes of decryption-key access|
|US7373668||May 17, 2002||May 13, 2008||Xilinx, Inc.||Methods and circuits for protecting proprietary configuration data for programmable logic devices|
|US7389429||May 17, 2002||Jun 17, 2008||Xilinx, Inc.||Self-erasing memory for protecting decryption keys and proprietary configuration data|
|US7480763||Aug 28, 2006||Jan 20, 2009||Altera Corporation||Versatile RAM for a programmable logic device|
|US7492188||Jul 30, 2007||Feb 17, 2009||Altera Corporation||Interconnection and input/output resources for programmable logic integrated circuit devices|
|US7525836 *||Apr 15, 2008||Apr 28, 2009||Maxim Integrated Products, Inc.||Non-imprinting memory with high speed erase|
|US7577055||Oct 31, 2007||Aug 18, 2009||Altera Corporation||Error detection on programmable logic resources|
|US7755419||Jan 16, 2007||Jul 13, 2010||Cypress Semiconductor Corporation||Low power beta multiplier start-up circuit and method|
|US7830200||Jan 16, 2007||Nov 9, 2010||Cypress Semiconductor Corporation||High voltage tolerant bias circuit with low voltage transistors|
|US7839167||Jan 20, 2009||Nov 23, 2010||Altera Corporation||Interconnection and input/output resources for programmable logic integrated circuit devices|
|US7907460||Jul 15, 2009||Mar 15, 2011||Altera Corporation||Error detection on programmable logic resources|
|US8085857||Sep 22, 2004||Dec 27, 2011||Cypress Semiconductor Corporation||Digital-compatible multi-state-sense input|
|US8112678||Dec 13, 2007||Feb 7, 2012||Altera Corporation||Error correction for programmable logic integrated circuits|
|US8130574||Feb 10, 2011||Mar 6, 2012||Altera Corporation||Error detection on programmable logic resources|
|USRE37060||Jan 21, 1998||Feb 20, 2001||Altera Corporation||Apparatus for serial reading and writing of random access memory arrays|
|USRE37195||Jan 6, 2000||May 29, 2001||Xilinx, Inc.||Programmable switch for FPGA input/output signals|
|U.S. Classification||326/38, 326/41, 365/189.05, 365/221, 365/230.08, 326/16|
|International Classification||G06F9/06, H03K19/177, G01R31/3185, H03K19/173, G05B19/05|
|Jun 25, 1992||AS||Assignment|
Owner name: ALTERA CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:CLIFF, RICHARD G.;REEL/FRAME:006177/0463
Effective date: 19920610
|Sep 23, 1996||FPAY||Fee payment|
Year of fee payment: 4
|Nov 12, 1997||AS||Assignment|
Owner name: ALTERA CORPORATION (A CORPORATION OF DELAWARE), CA
Free format text: MERGER;ASSIGNOR:ALTERA CORPORATION (A CORPORATION OF CALIFORNIA);REEL/FRAME:008811/0577
Effective date: 19970618
|Mar 5, 1998||AS||Assignment|
Owner name: ALTERA CORPORATION, A DELAWARE CORPORATION, CALIFO
Free format text: MERGER;ASSIGNOR:ALTERA CORPORATION, A CALIFORNIA CORPORATION;REEL/FRAME:009015/0336
Effective date: 19970325
|Feb 2, 2001||FPAY||Fee payment|
Year of fee payment: 8
|Dec 3, 2004||FPAY||Fee payment|
Year of fee payment: 12