US5245646A - Tuning circuit for use with an integrated continuous time analog filter - Google Patents
Tuning circuit for use with an integrated continuous time analog filter Download PDFInfo
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- US5245646A US5245646A US07/891,082 US89108292A US5245646A US 5245646 A US5245646 A US 5245646A US 89108292 A US89108292 A US 89108292A US 5245646 A US5245646 A US 5245646A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/04—Frequency selective two-port networks
- H03H11/12—Frequency selective two-port networks using amplifiers with feedback
- H03H11/1291—Current or voltage controlled filters
Definitions
- the present invention generally relates to filters, and more specifically to analog filter tuner circuitry.
- Analog electronic filter circuits are an integral part of a wide variety of electronic and semiconductor products. Filter circuits generally perform a predetermined function of preventing and permitting certain signal frequencies to be communicated. Analog filter circuits are characterized by being implemented with components such as resistors and capacitors. Resistors and capacitors can each be chosen to have one of a wide variety of component values. However, all integrated circuit analog component values, including resistors and capacitors, are subject to variation of the component value as a function primarily of temperature and processing (i.e. manufacturing) variations. Therefore, tuning circuits may be used with analog filter circuits in order to fine tune or adjust the filter to compensate for variation in the filter's analog components.
- switched capacitor filter One well known category of analog filters is the switched capacitor filter, so called because only switches and capacitors are used with an amplifier.
- An advantage of the switched capacitor filter is that resistors, which can vary in value, are not used. Also, the time constant is proportional to capacitor ratios as opposed to absolute analog capacitance values. Although capacitors also vary in value, capacitors can be ratioed and matched in a manner to minimize the effects of variation.
- amplifier frequency bandwidth must be much greater than an input signal sampling frequency, and the filter's input signal sampling frequency must be at least twice greater than the filter's pole frequency.
- switched capacitor filters are subject to frequency aliasing errors, require an additional filter stage known as an anti-aliasing filter and a smoothing filter, and have performance degradations at higher frequencies.
- Another known category of analog filters is the continuous time filter.
- One known implementation of the continuous time filter uses both capacitors and resistors and an amplifier.
- the frequency response is directly proportional to variation of the values of resistors and capacitors. Since these values vary greatly, the frequency response also varies. Therefore, a tuning circuit is often required for a continuous time filter.
- OTA-C operational transconductance amplifier-capacitor
- An operational transconductance amplifier filter uses the transconductance (gm) of an operational amplifier as the resistance required to implement the filter.
- Gm transconductance of an operational amplifier
- the transconductance of an amplifier is subject to nonlinear variation.
- Operational transconductance amplifiers also have relatively poor dynamic range and must be tunable.
- a wide variety of known filter tuning circuits exists.
- a common method of filter tuning is to laser trim the resistors or capacitors, or both.
- a primary disadvantage with circuits having components which must be trimmed is the cost associated with the additional manufacturing and production.
- Another common tuning circuit which is used in connection with analog filters is the use of off-chip external discrete resistors and capacitors which are less susceptible to variation and which may be readily adjusted to tune the filter.
- a disadvantage with this method is the requirement for components external to a filter integrated circuit. External components add cost, increase integrated circuit pin count and provide opportunities for noise and error to be introduced into the filter operation.
- a further common tuning circuit is integrated with the filter, but uses switched capacitors to simulate resistors. Capacitors can be ratioed with one another to minimize the effects of varying capacitances.
- phase lock loop uses a phase detector, a loop filter, and a voltage controlled oscillator (VCO) to tune the filter.
- VCO voltage controlled oscillator
- Phase lock loops require a large amount of circuitry in relation to the filter and typically introduce noise at a reference frequency provided for the phase lock loop.
- the reference frequency must also be equal to the filter's pole frequency. Therefore, additional clock frequency circuitry may be required to provide a specific reference frequency.
- a circuit comprising input means for receiving an analog input signal.
- the input means has a resistive/capacitive (RC) time constant and provides an intermediate signal having a value which varies between a first predetermined signal value and a second predetermined signal value during a time period determined by the resistive/capacitive time constant.
- An output means is coupled to the input means for receiving the intermediate signal and providing a digital equivalent of the analog input signal by providing a digital count value of cycles of a predetermined clock signal which are counted during the time period.
- a tuning circuit and method of operation for an analog filter is provided.
- the tuning circuit comprises an integrator having an input for receiving a first reference voltage and an output for providing an integration signal which varies from a first predetermined value to a second predetermined value within a time period.
- the time period is proportional to a time constant of the analog filter.
- a comparator has a first input coupled to the output of the integrator, a second input for receiving a second reference voltage which is greater in magnitude than the first reference voltage, and an output for providing an enable signal which maintains a predetermined logic value during the time period.
- a counter has a first input for receiving the output of the comparator, a second input for receiving a reference clock signal, and an output for providing an output count value of the time period.
- a decoder has an input coupled to the output of the counter. The decoder converts the output count value to a control signal for controlling and selectively modifying a component value of the analog filter to control the time constant of the analog filter to compensate for process variations affecting the time constant of the analog filter.
- FIG. 1 illustrates in partial schematic form a tuning circuit in accordance with the present invention
- FIG. 2 illustrates in table form a truth table of a decoder in the tuning circuit of FIG. 1;
- FIG. 3 illustrates in partial schematic form an analog filter for use with the tuning circuit of FIG. 1.
- a tuning circuit 10 generally having an integrator with an input portion 12 and a comparator portion 14, a count portion 16, and a decode portion 18.
- a resistor 24 has a first terminal connected to a first reference voltage, labeled "V REF 1 ".
- a second terminal of resistor 24 is connected to an inverting or negative input of an operational amplifier 21.
- a noninverting or positive input of operational amplifier 21 is connected to a second reference voltage labeled "V REF 2.”
- a capacitor 26 has a first electrode connected to the negative input of operational amplifier 21.
- a second electrode of capacitor 26 is connected to an output of operational amplifier 21.
- a switch 28 has a first terminal connected to the first electrode of capacitor 26 and a second terminal connected to the output of operational amplifier 21.
- Switch 28 has a control terminal for receiving a control signal labeled " ⁇ 1".
- Comparator portion 14 has an operational amplifier 30 having an inverting or negative input connected to the output of operational amplifier 21.
- a noninverting or positive input of operational amplifier 30 is connected to a third reference voltage labeled "V REF 3."
- V REF 3 may have a voltage value which is either greater than or less than V REF 2.
- Each of the three reference voltages are referenced with respect to some predetermined voltage, preferably a supply voltage V SS .
- An output of operational amplifier 30 is connected to an enable input of a counter 32 of the count portion 16.
- Control signal ⁇ 1 is connected to a Reset input of counter 32, and a system clock signal labeled "CLOCK” is connected to a clock input of counter 32.
- Counter 32 provides a multi-bit count output. In the illustrated form, each of a plurality of five single-bit outputs is connected to one of a plurality of five inputs of a decoder 34 of decode portion 18. Decoder 34 provides five outputs respectively labeled "B0", “B1", “B2”, “B3”, and "B4".
- tuning circuit 10 functions to provide a decoded output signal for use by an analog filter in adjusting the resistive/capacitive time constant of the filter to an optimum value. Because analog filters are made with analog components which vary in value over processing and temperature variations, adjustment of the analog components is desirable.
- Input portion 12 and comparator portion 14 function to provide an enable signal to counter 32 for a predetermined amount of time. However, this predetermined amount of time will vary primarily as the values of capacitor 26 and resistor 24 vary with respect to processing and temperature.
- Input portion 12 functions to integrate a fixed input current signal conducted at the negative input of operational amplifier 21. The time to perform this integration is proportional to the amount of time required to change capacitor 26 to substantially the V REF 2 voltage. Accordingly, switch 28 functions to periodically discharge capacitor 26 or autozero the operational amplifier 21.
- a ramp time, T ramp, of the integrator may be represented in equation one below as:
- Comparator portion 14 functions to compare the output of input portion 12 with the value of V REF 3. Until the output of input portion 12 is greater than V REF 3 in value, counter 32 remains enabled. Once the output of input portion 12 equals V REF 3, counter 32 is disabled. During the time period which counter 32 is enabled, counter 32 is counting the number of clock cycles of the system CLOCK signal. The number of clock cycles which are counted while input portion 12 is integrating is provided by counter 32 as an output.
- the output of counter 32 may be represented in equation two below as:
- T clock is the clock frequency period of the CLOCK signal connected to counter 32.
- the output of counter 32 is decoded into a binary output value represented by bits B0 thru B4.
- Bits B0 thru B4 are an encoded time constant variation compensation code of the RC time constant of input portion 12.
- FIG. 2 Illustrated in FIG. 2 is a truth table for decoder 34.
- five input bits and five output bits are discussed. It should be readily apparent that any number of decoder inputs/outputs may be utilized depending upon the amount of tuning resolution desired for the analog filtering.
- For a five-bit input there are 2 5 or thirty-two possible binary values.
- For each five-bit binary value there is an assigned predetermined binary output. As may be readily noted in FIG. 2, some of the binary inputs are assigned to the same binary output value for controlling the analog filter. Before an analysis of the assignment of output values for bits B0-B4 is made, a discussion of the effect which control bits B0-B4 have on an analog filter is desirable.
- Analog filter 40 generally has a resistive/capacitive portion 42 and an amplifier portion 44. Within resistive/capacitive portion 42 there is provided an input terminal labeled "Filter input" for receiving a filter input. The input terminal is connected to a first terminal of a resistor 50. A second terminal of resistor 50 is connected at a node 51 to a first terminal of a resistor 52. A second terminal of resistor 52 is connected at a node 53 to a positive or noninverting input of an operational amplifier 54. Connected to node 53 is a first electrode of each of a plurality of binary weighted capacitors 60-64.
- capacitor 60 has a designated unit weight of "C”
- capacitor 61 has a designated weight of 2C
- capacitor 62 has a designated weight of "4C”
- Each of capacitors 60-64 has a second electrode connected to a first terminal of a respective one of a plurality of switches 70-74.
- the second electrode of capacitor 60 is connected to the first terminal of switch 70, and so forth for capacitors 61-64 and switches 71-74.
- Each of switches 70-74 has a second terminal connected to a reference voltage terminal for receiving a supply voltage labeled "V SS ".
- Each of switches 70-74 has a control terminal for receiving a respective one of a plurality of control signals B0-B4 from the output of decoder 34 of FIG. 1.
- the control terminal of switch 70 is connected to control signal B0
- the control terminal of switch 71 is connected to control signal B1, and so forth.
- a first electrode of each of a plurality of binarily weighted capacitors 80-84 is connected to node 51.
- capacitor 80 has a designated unit weight of "C”
- capacitor 81 has a designated weight of "2C”
- capacitor 82 has a designated weight of "4C”
- Each of capacitors 80-84 has a second electrode connected to a first terminal of a respective one of a plurality of switches 90-94.
- the second electrode capacitor 80 is connected to the first terminal of switch 90, and so forth for capacitors 81-84 and switches 91-94.
- Each of switches 90-94 has a second terminal connected to an inverting or negative input of operational amplifier 54.
- Each of switches 90-94 has a control terminal for respectively receiving control signals B0-B4 from decoder 34 of FIG. 1.
- An output of operational amplifier 54 is connected to the negative input thereof and to the second terminals of switches 90-94.
- the output of operational amplifier 54 provides an output of analog filter 40 labeled "Filter Output.”
- an analog filter input signal is coupled to filter 40 at the filter input and filtered by operational amplifier 54 in combination with the net capacitive effect of capacitors 60-64 and 80-84 and resistors 50, 52.
- Resistors 50, 52 and capacitors 60-64 and 80-84 function as a resistive/capacitive (RC) network having an effective RC time constant.
- the RC time constant establishes a frequency pole of filter 40.
- Each of the resistors 50, 52 and capacitors 60-64, 80-84 is subject to processing and temperature variation which can vary the frequency pole of filter 40 and otherwise vary the frequency response of the filter.
- the present invention functions to use tuner circuit 10 to vary the capacitance of resistance/capacitance portion 42 to compensate for variations in both the resistance and capacitance of resistance/capacitance portion 42.
- the output of tuner 10 may be readily modified to also directly control only resistive values in analog filter 40 or a combination of both resistive and capacitive values.
- variations in resistors 50, 52 and capacitors 60-64 and 80-84 will generally directly track with variations in resistor 24 and capacitor 26 provided all of the resistors are fabricated to be of the same type and physical orientation (i.e. circuit layout) and all of the capacitors are fabricated to be of the same type and physical orientation.
- decoder 34 can provide a dynamic signal which will control the amount of effective capacitance in the resistance/capacitance portion 42. Therefore, an effective method exists to maintain a constant frequency pole for analog filter 40 by selecting a variable number of capacitors in a bank of capacitors.
- the output value can assume a B0-B4 signal value which has the effect of switching in all of capacitors 60-64 and capacitors 80-84 in resistance/capacitance portion 42.
- the B0-B4 signal value may have the effect of switching only capacitors 60, 61 and 80-81 in resistance/capacitance portion 42.
- there is no B0-B4 output signal which has the effect of switching from only capacitor 60 to capacitor 61 and from capacitor 80 to capacitor 81. The reason to avoid switching from one unit of capacitance (i.e. capacitor 60) to two units of capacitance (i.e.
- capacitor 61 is to avoid a two-to-one or one hundred percent change which creates very poor tuning resolution. It should be noted that the lowest valued output signal provided by decoder 34 is equivalent to three units of capacitance. The next highest increment is to increase to four units of capacitance which is an increase having a less negative effect on resolution.
- a predetermined input value is chosen as being the value which represents the desired value of capacitance assuming that no error in the component values exists. The predetermined input value representing the desired value of capacitance should not preferably be in the middle of the input values. The predetermined input value representing the desired value of capacitance should be in the upper third of the range, i.e. in the lower value range of the inputs in order to permit better resolution at the low end of the capacitive switching range.
- the switching of capacitors having capacitive units between fifteen, sixteen, seventeen, eighteen, nineteen, twenty, etc. units of capacitance is a much smaller change in percentage than when changing between one, three, four, etc., units of capacitance.
- the truth table of FIG. 2 represents an efficient decoding which permits a deviation in the count value of counter 32 to be corrected with optimum resolution when using a five-bit count signal.
- the present invention provides a circuit which: (1) receives an analog input signal; (2) integrates the input signal with input portion 12; and (3) provides a digital equivalent of the analog input signal with count portion 16.
- the integration is related to a predetermined RC time constant, where the resistance may also be implemented as a transconductance rather than a resistance.
- the known RC time constant is utilized to adjust another RC time constant having the same physical and electrical properties of another circuit.
- the digital equivalent may be directly used if only a digital equivalent of the analog input signal is desired. In other forms, other decodings of the resulting digital equivalent of the analog input signal may be implemented.
- the tuning circuit and method taught herein require no trimming or adjusting of component values. Also, no components which are external to an integrated circuit containing the filter are required.
- the tuner circuit taught herein does not rely on feedback and is therefore more stable than a phase lock loop.
- the decoder 34 may be implemented as a programmable logic device (PLA), by conventional logic circuitry, or by a memory, as well as in other known forms. Similarly, many known counter circuits may be utilized as counter 32 of the inventive tuner. Although capacitors having a binary weighting have been discussed, it should be readily apparent that capacitors having other weighting factors (i.e.nary or logarithmic) may be used. Although a specific decoding has been provided for decoder 34, it should be noted that other decodings which implement a nonlinear relationship between the input and the output of decoder 34 may be used.
- an integrator is illustrated in the disclosed tuning circuit, other circuits which do not integrate but which have an RC time constant may be used.
- a filter stage having an RC network may be used rather than an integrator.
- the output of the filter stage is exponential rather than linear when an integrator is used.
- An implementation with an integrator is generally preferable because the linear output of the integrator ensures that the response time of comparator portion 14 will not be variable. If an exponential signal is input into comparator portion 14, the response time of the comparator will be variable.
Abstract
Description
T ramp=[(V.sub.REF 3 -V.sub.REF 2)/(V.sub.REF 2 -V.sub.REF 1)]* R.sub.24 * C.sub.26 (1)
Output ofCounter 32=[T ramp]/[T clock] (2)
Claims (11)
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US07/891,082 US5245646A (en) | 1992-06-01 | 1992-06-01 | Tuning circuit for use with an integrated continuous time analog filter |
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Cited By (39)
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US5416438A (en) * | 1992-03-18 | 1995-05-16 | Nec Corporation | Active filter circuit suited to integration on IC chip |
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US20080191795A1 (en) * | 2007-02-08 | 2008-08-14 | Mediatek Singapore Pte Ltd | Method and apparatus for tuning an active filter |
US20090108858A1 (en) * | 2007-10-24 | 2009-04-30 | Industrial Technology Research Institute | Methods and systems for calibrating rc circuits |
US20100013546A1 (en) * | 2006-12-01 | 2010-01-21 | Jung-Hoon Yoo | Systems and methods for filter tuning using binary search algorithm |
US20100073048A1 (en) * | 2008-09-24 | 2010-03-25 | Mediatek Inc. | Phase locked loop and calibration method |
US20100323651A1 (en) * | 2009-06-23 | 2010-12-23 | Qualcomm Incorporated | Tunable adaptive filter with variable gain trans-conductance stage |
US20110128071A1 (en) * | 2009-11-27 | 2011-06-02 | Masaru Fukusen | Filter automatic adjustment circuit and method for adjusting characteristic frequency of filter, and wireless communication apparatus provided with the same |
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Cited By (69)
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US5416438A (en) * | 1992-03-18 | 1995-05-16 | Nec Corporation | Active filter circuit suited to integration on IC chip |
US5473278A (en) * | 1993-02-15 | 1995-12-05 | Nec Corporation | Filter circuit including a switch circuit inserted between input terminal and RC filter |
EP0851378A1 (en) * | 1996-12-30 | 1998-07-01 | Datalogic S.P.A. | Method and device for measuring and regulating a time constant of an electronic circuit forming part of an optical code reader |
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