|Publication number||US5247376 A|
|Application number||US 07/433,925|
|Publication date||Sep 21, 1993|
|Filing date||Nov 9, 1989|
|Priority date||Nov 17, 1988|
|Publication number||07433925, 433925, US 5247376 A, US 5247376A, US-A-5247376, US5247376 A, US5247376A|
|Original Assignee||Seiko Epson Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (26), Non-Patent Citations (4), Referenced by (36), Classifications (8), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention relates generally to a method of activating a liquid crystal display and, in particular, to a display activation method which eliminates crosstalk occurring between adjacent column elements in a liquid crystal display.
Conventional liquid crystal displays include a matrix of liquid crystal display elements. Some conventional displays are classified as passive matrix displays and are activated with high duty cycles and time-division multiplexing. Other conventional displays are classified as active matrix displays and each liquid crystal element, or pixel, includes a switching element having storage capabilities. Active matrix liquid crystal displays employing two terminals, separated by a non-linearly conducting material such as a metal-insulator-metal (MIM) device, require relatively simple manufacturing processes and provide high contrast. A driving circuit for a liquid crystal electro-optical device is described in U.S. Pat. No. 4,560,982, the contents of which are hereby incorporated herein by reference.
A simplified configuration of a MIM active matrix liquid crystal display is shown as a display 200 in FIG. 2(A). An A/D converter 201 of display 200 converts an incoming analog video signal into 4-bits of digital video data (D0 -D3). The 4-bits of video data D0 -D3 are supplied to a Y driver 202 which produces a data signal to a plurality of column electrodes 205 of a liquid crystal panel 204. Liquid crystal panel 204 is in the form of a sheet having orthogonal electrodes arranged in rows and columns. A plurality of row electrodes 206 of panel 204 for supplying scanning signals are driven by an X driver 203.
A timing controller provides a plurality of timing signals DY, YCL, LP, FR and FGS to Y driver 202. Y driver 202 also receives voltages V0, V3, V4 and V7 for activating the liquid crystal display.
X driver 203 produces a scanning signal to row electrodes 206 of liquid crystal panel 204. X driver 203 is activated by timing signals DX, XCL and FR from the timing controller. X driver 203 also receives voltages V0, V1, V2, V5 and V6 for activating the liquid crystal material. The activating voltages decrease sequentially from V0 to V7.
A portion of panel 200, including row electrode 206, column electrode 205, a layer of liquid crystal material 207 and a MIM device 208, is shown in FIG. 2(B). Liquid crystal layer 207 and MIM device 208 are connected in series at each intersection of column electrodes 205 and row electrodes 206. One end of liquid crystal layer 207 is electrically coupled to row electrode 206 and one end of MIM device 208 is electrically coupled to column electrode 205. The current-voltage characteristics of MIM device 208 are shown in FIG. 4. The potential across liquid crystal layer 207 is denoted VLC and the potential across MIM 208 is denoted VM.
FIG. 3 is a circuit diagram for Y driver 202. Y driver 202 includes a plurality of output circuits for energizing column electrodes 205. Each output circuit is identical in configuration to the output circuit for energizing a first output Y0 of a line buffer 302.
A shift register 301 successively delivers shift data signals or start signals to each successive line buffer 302 in response to a shift clock pulse YCL. Buffer 302 includes a plurality of 4-bit memories, such as MOA's of a first line buffer 303. When shift register 301 delivers a shift signal, video data bits D0 -D3 are successively stored in the memories and video data about one line is thereby stored.
A second line buffer 304 includes a plurality of 4-bit memories such as MOB's. Video data are transferred from first line buffer 303 to second line buffer 304 in response to latch pulse LP. In this manner, video data D0 -D3, which are initially sent serially, are converted into parallel form by second line buffer 304.
The video data from second line buffer 304 are inverted by a plurality of inverters 305 and transmitted to a coincidence circuit 307. The other 4-bit input terminals of coincidence circuit 307 receive 4-bit logic data Q0 -Q3 from a 4-bit counter 306 which can be a 4-bit binary counter. Counter 306 is reset by signal RES and counts clock pulses FGS which are provided for producing various grey levels.
When coincidence circuit 307 detects the coincidence of inverted data from second line buffer 304 and logic data from 4-bit counter 306, coincidence circuit 307 sets an SR latch 308 by providing a signal to the S input of latch 308. Latch 308 is reset by signal RES which is input to the R input terminal of latch 308. When Y driver 202 is activated in a conventional manner, signal LP is applied to Y driver 202 at both the LP and RES input terminals of Y driver 202 such that the signals were not independent.
As shown in the timing diagram of FIG. 5, fifteen (15) FGS pulses occur within one LP (RES) time period. When signal LP (RES) is applied to SR latch 308, latch 308 takes a logic level of 0. If the inverted data from second line buffer 308 agrees with the logic data from 4-bit counter 306, SR latch 308 assumes a logic value of 1. The period of signal LP corresponds to one data output period and SR latch 308 is maintained at logic 1 during a period given by: ##EQU1##
Terminals Q and Q of SR latch 308 are electrically coupled to the gate terminals of analog switches 309 and 310 respectively. Signals FR and FR are input to analog switches 311 and 312, respectively. Voltages V0 and V7 are applied to switches 311 and 312, respectively. To activate liquid crystal material 207, either voltage V0 or V7 is applied to the source terminal of analog switch 310 via switch 314 or switch 313. The drain terminals of analog switches 309 and 310 are connected together and deliver column electrode driving output Y0.
Y driver circuit 202 produces Y signal waveforms as shown in FIG. 5. Voltages V0 -V7 assume values as follows:
The polarity of the Y signal is inverted every data output period, equal to period Ts. The phase is inverted every successive field which is equal to Ts+Tn. A first field is equal to Ts1+Tn1 and a second field is equal to Ts2+Tn2, etc. Both the ratio of the activating ON voltages Vp and (0) to the non-activating OFF voltages Vp-Va and (Va) is determined during one data output period, depending on the contents of video data D0 -D3. Accordingly, the output is pulse width-modulated to provide selected grey levels.
X driver 203 receives either shift data signal DX or a start signal and shift data successively in response to shift clock pulses of signal SCL. The particular column electrode 206 corresponding to the position to which data has been transferred receives the following signal as the scanning signal:
at a selected period, either voltage V0 or V1 ; and
during every unselected period, a first voltage level of V1 and V5 or a second voltage level of V2 and V6.
Voltages V1 -V6, shown in FIG. 5, assume values given by:
The voltage level assumed during a selected period and the voltage level during an unselected period are alternating signals, synchronized with signal FR. During a selected period, the voltage level is in phase with signal FR. During an unselected period, the voltage level is 180° out of phase with signal FR.
For the X signal shown in FIG. 5, voltage V0 becomes equal to Vp (V0 =Vp) during selected period Ts1. The first voltage level is then selected during unselected period Tn1. After the voltage V7 becomes null (V7 =0) during selected period Ts2, the second voltage level is selected during unselected period Tn2.
Signal Y-X, shown in FIG. 5, shows variations of the potential at Y electrode 205 with respect to the potential at X electrode 206. The illustrated broken lines indicate the potential at a point located midway between MIM device 208 and liquid crystal display 207, as shown in FIG. 2(B). The hatched portion indicates the effective voltage VLC applied to the liquid crystal. The difference between the Y-X signal and the level represented by the broken line indicates voltage VM applied to MIM device 208.
During selected period Ts1 or Ts2, the magnitude of |Y-X| is large, as shown in the third and first quadrants of the IM-VM characteristic curve of MIM device 208 (FIG. 4); |VM| is large, therefore |IM| is also large. Accordingly, electric charge is stored in the liquid crystal 207, resulting in a large value of |VLC|. The magnitude of |VLC| is determined both by the ratio of potential Va (Vp-Va) and potential 0 (Vp) on the application of Y signal during period Ts1 or Ts2. As the percentage of 0 (Vp) increases, |VLC| increases.
During unselected periods Tn1 and Tn2, the Y-X signal assumes levels Vb(Va-Vb) and (Va-Vb)(-Vb), respectively. Therefore, in the first and third quadrants of FIG. 4, |VM| takes smaller values than during selected periods TS1 and TS2. Electric current IM and electric discharge from liquid crystal 207 through MIM device 208 are also small. Accordingly, during unselected periods Tn1 and Tn2, electric charge is retained. Liquid crystal device 200 is activated almost statically. Hence, a liquid crystal display offering high contrast can be realized.
This conventional activation method has certain drawbacks. FIGS. 6(A), 6(B) and 6(C) depict one example of display provided by a liquid crystal. From row electrode 21 to row (2l+3), the even rows are on, and none of the odd rows are on as shown in FIG. 6(B). The other rows, row 2m and row (2m+1) of column n provide a display of another pattern (e.g. half tone pattern). It is noted that the video data to be displayed in both pixels (2m, n) and (2m+1, n) are the same as shown in FIG. 6(C). Although both display the same video data pixel (2m, n) appears bright, pixel (2m+1, n) appears dark. This phenomenon is caused by crosstalk between the successive rows, beginning from row 21 and ending with row 2l+3. The cause of this crosstalk interference is described below.
FIG. 7 shows output Yn from Y driver 202 and outputs X2m and (X2m+1) from X driver 203. Voltages Yn-X2m and Yn-X2m+1 are applied to pixels (2m, n) and (2m+1, n), respectively.
During selected period Ts, |VLC| of the liquid crystal having pixel (2m, n) is large due to pulse width modulation driving. However, during retention period Tn, |VM| is small. For this reason, electric charge is retained. During selected period Ts, when rows beginning with row 2l and end with (2l+2) are selected, Yn-X2m remains constant, having a voltage of Va-Vb or -(Va-Vb). This occurs because Yn shifts toward Vp during this selected period. Because row 21 is lit up, video data bits take logic values of 1, 1, 1, 1 and the voltage is Vp. Row (2l+1) is not lit up, i.e., video data bits take on logic values of 0, 0, 0, 0 and the voltage is Va. Consequently, |VM| is relatively small. Thus, electric discharge through MIM device 208 is small.
For pixel (2m+1, n), during unselected period Tn, when rows beginning with row 21 and ending with row 21+2 are selected, Yn-X2m+1 remains at a voltage of Vb or -Vb. Therefore, |VM| is comparatively large and the amount of electric discharge through MIM device 208 is large.
Although the video data at pixels (2m, n) and (2m+1, n) are common, the effective voltage applied to pixel (2m, n) on the liquid crystal, proportional to the area of the hatched portion is larger than the effective voltage applied to pixel (2m+1, n). Therefore, the two pixels differ in brightness, although the same signal is applied to both pixels in a selected time period.
The signal activating the liquid crystal display 200 is inverted at every line. Consequently, if the driving voltage is inverted every M rows, the pattern of either lit up dots or dots that are not lit up in each M rows appears as crosstalk between the pixels of the same column included in the pattern. Conventional liquid crystal activating methods therefore have inadequacies due to these shortcomings.
Accordingly, it is desirable to provide an improved method of activating a liquid crystal display which avoids the shortcomings of the prior art and provides a clear uniform display that lacks localized contrast variations caused by crosstalk.
Generally speaking, in accordance with the present invention, a method of activating a liquid crystal matrix panel formed with row electrodes for supplying a scanning signal and column electrodes for supplying a data signal and having liquid crystal material therebetween is provided. A selected row electrode is supplied with a signal which switches polarity at least once during a single data output period. The signal can switch from high to low or low to high. During one data output period, a signal for the data about a selected row is delivered with a first polarity and then the same signal is delivered with an opposite polarity. The switching occurs N times where N is a positive integer. The signal can be delivered with a first positive polarity or a first negative polarity and then switch to the other. This prevents crosstalk from occurring within a column.
In a preferred embodiment, N=1.
Accordingly, it is an object of the invention to provide an improved method for activating a liquid crystal display.
Another object of the invention is to provide a method of activating a liquid crystal display without producing crosstalk between pixels electrically coupled to the same column electrode.
A further object of the invention is to provide an improved circuit for driving a liquid crystal display in which crosstalk noise is substantially eliminated within a column electrode.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification and drawings.
The invention accordingly comprises the several steps and the relation of one or more of such steps with respect to each of the others thereof, which will be exemplified in the method hereinafter disclosed, and the scope of the invention will be indicated in the claims.
For a fuller understanding of the invention, reference is had to the following description taken in connection with the accompanying drawings, in which:
FIG. 1 is a waveform diagram of signals for activating a liquid crystal display in accordance with the invention;
FIG. 2(A) is a circuit diagram of an active matrix liquid crystal display;
FIG. 2(B) is an enlarged portion of FIG. 2(B);
FIG. 3 is a circuit diagram of the Y driver of FIG. 2(A);
FIG. 4 is a graph showing the current-voltage characteristics of a MIM device of FIG. 2(B);
FIG. 5 is a waveform timing diagram of signals for activating a liquid crystal cell;
FIG. 6(A) is a schematic plan view of a pattern shown on a liquid crystal display;
FIG. 6(B) is a plan view of electrodes for activating a liquid crystal display;
FIG. 6(C) is a schematic plan view of row electrodes for activating a liquid crystal display;
FIG. 7 is a waveform diagram of signals for activating a liquid crystal display element; and
FIG. 8 is a waveform diagram of signals for activating a liquid crystal display element in accordance with the invention.
FIG. 1 is a timing diagram of waveforms for activating liquid crystal display panel 200 in accordance with an embodiment of the invention. Objects of an embodiment of the invention are achieved by activating panel 200 in accordance with this driving method.
Signal Yn for activating liquid crystal pixels intersecting column is the output from Y driver 202. A pattern that can be displayed by panel 200 by activating a liquid crystal pixel along column electrode n is shown in FIG. 6(A). Signals X2m and X2m+1 represent waveforms outputs from X driver 203 at row electrodes X2m and X2m+1. The effective voltage at a liquid crystal pixel is equal to the voltage supplied by the corresponding row electrode from X driver 203 subtracted from the voltage supplied to the corresponding column electrode from Y driver 202. Accordingly, signal Yn-X2m represents the waveform of voltage applied to pixel (2m, n). Pixel (2m, n) refers to the liquid crystal cell located at the intersection of row electrode 2m from X driver 203 and column electrode n from Y driver 202. Signal Yn-X2m+1 represents the waveform of voltage applied to pixel (2m+1, n).
Y driver 202 is constructed as shown in FIG. 3 and is responsive to signals LP and RES. However, rather then being provided as the same signal, LP and RES are independent of each other. Two (2) RES pulses occur during one (1) LP period and are equivalent to 1 data output period. The period of signal FR is also equal to one data output period. Fifteen pulses from signal FGS occur during one (1) RES period. Signal FGS provides clock pulses to 4-bit counter 306 for grey levels. During one RES period, sixteen (16) different pulse width-modulated waveforms can be produced. Thus, the signal data output Yn from Y driver 202 is delivered twice, but with opposite polarities, as indicated at regions a and b during one data output period and based on the same video data.
Each row electrode receives a voltage sufficient to activate the liquid crystal pixel, sequentially, for interval Ts. The row electrode then remains at a voltage insufficient to activate the pixel for a period of Tn, until the next field.
During activation of liquid crystal display 200, a voltage is applied to liquid crystal material at pixel (2m, n) for example. The effective voltage at pixel (2m, n) is equal to the difference of the voltage of the row electrode from the voltage of the column electrode. This waveform is represented by the solid line of signal Yn-X2m. The waveform of the voltage applied across the liquid crystal material 207 (VLC) of pixel (2m, n) is indicated by the broken line shown on signal Yn-X2m. During selected period Ts, the pulse width-modulated output Yn increases by the magnitude of the potential across liquid crystal 207, which is represented by |VLC|. During unselected period Tn, Yn-X2m has a voltage of Va-Vb (Vb) or -Vb (-Va-Vb) and VM is small. Thus, electric charge is retained. The values of Va, Vb, etc. are shown in FIG. 5 and have been described above.
During period Tn, while rows 21, 2l+1, 2l+2 are selected sequentially, the voltage of Yn-Xzm (z is an integer) due to portion a, about row 2l+1 for example, of output Yn that is pulse widthmodulated by the video data is Va-Vb. The voltage due to portion b is -Vb. In this manner, the voltage does not remain constant during a selecting period. The switch in voltages diminishes crosstalk. Consequently, the amount of electric charge discharged throughout the MIM device is not affected.
The same conditions occur with respect to pixel (2m+1, n). During unselected period Tn, rows 2l, 2l+1, 2l+2, etc. are selected sequentially. Waveform Yn-X2m+1, which is due to the waveform that is pulse width-modulated by the video data about these rows, takes levels (Va-Vb) (Vb) and -Vb (-Va-Vb), alternately. Because the voltage switches, crosstalk generated at the beginning of a data output period and during the switch cancel and crosstalk is thereby effectively controlled. Consequently, the amount of discharge throughout the MIM device is unaffected. Crosstalk is not developed between pixels (2m, n) and (2m+1, n) from the video data about the rows 2l, 2l+1, and 2l+2. In this manner, disadvantages caused by crosstalk between successive pixels in the same column can be prevented.
As described above, during one data output period, the output due to the same video data is delivered twice, but with opposite polarities, as shown in portions a and b of output Yn. The effects of the amount of discharge caused by the signals applied to each pixel during the unselected time, is cancelled out. Accordingly, crosstalk between successive display elements in the same column can be controlled by repeating the output of the same video data N times with each time including waveforms of opposite polarities and wherein N is a positive integer.
In the driving waveforms shown in FIG. 1, the selected period Ts is maintained at the same position of FR=0. Therefore, the voltages (indicated by hatching) applied to the liquid crystal for the successive rows, for example rows 2m and 2m+1, are in phase with each other. This causes the whole viewing side of the liquid crystal display to flicker at the frame frequency which can be 30 Hz, for example, creating an undesirable viewing quality.
Another activation method in accordance with another embodiment of the invention is illustrated by the activating waveforms of FIG. 8, which can prevent problems associated with display flicker. The period of the FR signal is twice as long as one data output period. One FR signal is switched to the next FR signal at the middle point of one period of the LP signal. Thus, data is delivered with a different sequence of polarities in sequentially activated electrodes during successive data output periods.
For example, output Yn can be first delivered for the data about row 2m with positive polarity and then delivered with negative polarity during a data output period. When the data about row (2m +1) is delivered, the sequence of polarities is reversed. During each period in which data about each pixel is retained, the influence of the video data about other rows on the voltage waveforms (Yn-X2m) and (Yn-X2m+1), such as shown in areas c and d or e and f, are cancelled out, in the same way as in FIG. 1.
The effects from this activation method is that crosstalk between vertically adjacent pixels can be prevented. During selected period Ts for pixel (2m, n), FR=0. Selected period Ts for pixel (2m+1, 2n) occurs during FR=1. The voltage waveforms applied to the liquid crystal cells at these two pixels are 180° out of phase with each other. Consequently, the whole liquid crystal material of panel 200 is effectively activated with alternating current such that the phase of sequential rows is reversed. Hence, the flicker is greatly reduced.
As can be seen from the above description, in accordance with the invention, data are delivered N (integer) times with opposite polarities during a single data output period. During an unselected period, the video data about one pixel does not affect the video data about the other pixels of the same column and no crosstalk occurs. Where N=1, the sequence in which data of opposite polarities are delivered is thereby different between sequential data output periods. This significantly reduces flicker on the viewing side of the liquid crystal.
Accordingly, an improved display is achieved by a method of activating the matrix liquid display wherein a high voltage is applied to the electrodes of selected row electrodes and a low voltage is applied to unselected row electrodes. The method includes delivering the data signals about the selected rows and repeating this delivering step N times (N is a positive integer) with different polarities during one data output period. In one embodiment of the invention, N=1. The data signals about the selected rows may be delivered first with positive polarity and then with negative polarity during the first data output period of successive data output periods. In the second data output period, the data signals about the selected rows are delivered first with negative polarity and then with positive polarity.
It will thus be seen that the objects set forth above, among those made apparent from the preceding description, are efficiently attained and, since certain changes may be made in carrying out the above method without departing from the spirit and scope of the invention, it is intended that all matter contained in the above description shall be interpreted as illustrative and not in a limiting sense.
It is also to be understood that the following claims are intended to cover all of the generic and specific features of the invention herein described and all statements of the scope of the invention which, as a matter of language, might be said to fall therebetween.
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|U.S. Classification||345/94, 345/210, 345/95, 345/98|
|International Classification||G02F1/133, G09G3/36|
|Nov 9, 1989||AS||Assignment|
Owner name: SEIKO EPSON CORPORATION, JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:WAKAI, YOICHI;REEL/FRAME:005272/0685
Effective date: 19891027
|Mar 11, 1997||FPAY||Fee payment|
Year of fee payment: 4
|Mar 1, 2001||FPAY||Fee payment|
Year of fee payment: 8
|Feb 23, 2005||FPAY||Fee payment|
Year of fee payment: 12