|Publication number||US5249179 A|
|Application number||US 07/527,975|
|Publication date||Sep 28, 1993|
|Filing date||May 24, 1990|
|Priority date||May 24, 1989|
|Publication number||07527975, 527975, US 5249179 A, US 5249179A, US-A-5249179, US5249179 A, US5249179A|
|Original Assignee||Nec Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (10), Non-Patent Citations (2), Referenced by (3), Classifications (11), Legal Events (10)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to a full duplex data transmission system using an echo canceller, and more particularly to an echo canceller for a full duplex data transmission system suitable for using a 2B1Q code as the transmission code.
Various transmission codes have so far been proposed for application to full duplex data transmission using an echo canceller. Among the proposed codes, a 2B1Q code by which a two-bit code is converted into four signal levels (+3, +1, -1, -3) have been adopted as the standard code in the U.S. because of its superiority over other codes including an alternate mark inversion code and a biphase code in terms of the required transmission band and the effect on near-end crosstalk. While no specific circuitry has as yet been proposed for an echo canceller system suitable for a 2B1Q code, there is conceivable in general a configuration using a well-known echo canceller and a digital-to-analog (D/A) converter for converting the two-bit code into the four-level signals. The use of a D/A converter, however, involves the problem of complicating the circuitry.
An object of the present invention is to provide a novel echo canceller system suitable for a 2B1Q code and simple in configuration.
An echo canceller system according to the invention has a code converting circuit for converting binary serial data in two-bit units to generate a two-bit converted code. The bits of the converted code are added after each of them is amplified to a prescribed amplitude, and the result of the addition is subjected to a D.C. offset to generate a 2B1Q code. The 2B1Q code is sent out to a two-wire line, and part of it returns to the receiving side as an echo signal. The echo signal is cancelled by an echo canceller provided corresponding to each bit of the converted code. This configuration dispenses with a D/A converter, and makes it possible to realize an echo canceller system simple in hardware.
FIG. 1 is a block diagram illustrating a preferred embodiment of the present invention, and
FIG. 2 is a table showing the relationships among input two-bit codes, converted signals and the 2B1Q code.
FIG. 1 is a block diagram illustrating a preferred embodiment of the present invention. A code converting circuit 1 divides transmit data into two-bit (b2n, b2n-1) units, and converts the resultant two-bit data into converted signals B0 and B1 according to the conversion table of FIG. 2, wherein a signal B1 is obtained by inverting the first bit b2n of a two-bit datum and a signal B0, by figuring out the exclusive logical sum of the second bit b2n-1 and the signal B1. FIG. 2 further shows the relationship between the two-bit data and the 2B1Q code, with Qn representing the symbol value of the 2B1Q code. The converting circuit 1 for performing the conversions listed in FIG. 2 consists of a serial-to-parallel converter for converting transmit data into two-bit parallel data and a read-only memory (ROM) for storing the conversion table of FIG. 2. The converted signals B0 and B1 are sent to an encoding circuit 2 as well as to echo cancellers 4 and 5. The encoding circuit 2, comprising amplifiers 21 and 22 and adders 23 and 24, converts the converted signals B0 and B1 into the 2B1Q code (Qn of FIG. 2) according to the table of FIG. 2. More specifically, after the signals B0 and B1 are respectively amplified by the amplifiers 21 and 22, the amplified signals B0 and B1 are added by the adder 23 in an analog manner. The adder 24 further adds a signal B2 of a voltage corresponding to "+3" in an analog manner to give a transmit code Qn. The code Qn is supplied to a two-wire line via a hybrid circuit 6. If the amplifying rates of the amplifiers 21 and 22 are set at "-2" and "-4", respectively, a transmit code of a voltage proportional to the symbol value Qn shown in the table of FIG. 2, i.e. the 2B1Q code, will be obtained.
Meanwhile an echo signal, resulting from the going round of this transmit code to the receiving side via the hybrid circuit 6 and a receive code having passed the hybrid circuit 6 from the two-wire line are led to an offset removing circuit 3 as receive signals. The offset removing circuit 3 removes an D.C. offset component by subtracting from the receive signal a delayed receive signal, resulting from the delaying of the receive signal by a delay D by a one-symbol period. This D.C. offset corresponds to the signal B2, which was added in the encoding circuit 2. The echo cancellers 4 and 5 are provided to separately cancel echo signals pertaining to the signals B0 and B1, respectively, and comprise adaptive filters 41 and 51 and subtractors 42 and 52, respectively. The adaptive filters 41 and 51, as is well known to those skilled in the art, produce echo replicas or estimated echo signals on the basis of the signals B0 and B1, and the subtractors 42 and 52 subtract the estimated echo signals from the receive signal. The transmission characteristics of the adaptive filters 41 and 51 are adaptively corrected according to the signals B0 and B1 and residual echo signals.
As hitherto described, the present invention, dispensing with a D/A converter by using a converting circuit including amplifiers and adders, makes it possible to realize a novel echo canceller system suitable for a 2B1Q code and simple in configuration.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3571725 *||May 22, 1968||Mar 23, 1971||Nippon Electric Co||Multilevel signal transmission system|
|US4117277 *||Jun 16, 1977||Sep 26, 1978||U.S. Philips Corporation||Arrangement for simultaneous two-way data transmission over two-wire circuits|
|US4162378 *||Jan 16, 1978||Jul 24, 1979||Telecommunications Radioelectriques Et Telephoniques Trt||Digital echo canceler for a modem for data transmission by means of modulation of a carrier|
|US4757519 *||Oct 2, 1987||Jul 12, 1988||Hewlett-Packard||Digital premodulation filter|
|US4757527 *||Sep 4, 1985||Jul 12, 1988||Plessey Overseas Limited||Echo canceller|
|US4845746 *||Jun 23, 1987||Jul 4, 1989||Rockwell International Corporation||Echo canceller with relative feedback control|
|US4878232 *||Oct 15, 1986||Oct 31, 1989||Stc Plc||Data transmission system|
|US4896335 *||Jun 3, 1988||Jan 23, 1990||National Semiconductor Corporation||Digital 2B1Q transmitter with high precision and linearity time domain response|
|US4922530 *||May 3, 1989||May 1, 1990||Tellabs, Inc.||Adaptive filter with coefficient averaging and method|
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|1||"A Long Reach Digital Subscriber Loop Transceiver" by P. F. Adams et al., Br Telecom Technol. J. vol. 5, No. 1, Jan. 1987.|
|2||*||A Long Reach Digital Subscriber Loop Transceiver by P. F. Adams et al., Br Telecom Technol. J. vol. 5, No. 1, Jan. 1987.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US5461582 *||Mar 16, 1994||Oct 24, 1995||Industrial Technology Research Institute||Filter for 2B1Q signals|
|US6307864 *||Sep 8, 1998||Oct 23, 2001||Stmicroelectronics S.A.||Process and device for the baseband transcoding of digital information|
|US6463052||May 20, 1998||Oct 8, 2002||Sprint Communications Company L.P.||Method, system and apparatus for telecommunications control|
|U.S. Classification||370/286, 379/406.06, 379/406.08, 375/287, 370/290|
|International Classification||H04L25/49, H04B3/23|
|Cooperative Classification||H04L25/4919, H04B3/23|
|European Classification||H04L25/49M1, H04B3/23|
|Jun 22, 1990||AS||Assignment|
Owner name: NEC CORPORATION, 7-1, SHIBA 5-CHOME, MINATO-KU, TO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:KOYAMA, TETSU;REEL/FRAME:005391/0309
Effective date: 19900524
|May 6, 1997||REMI||Maintenance fee reminder mailed|
|Dec 9, 1997||FP||Expired due to failure to pay maintenance fee|
Effective date: 19971001
|Oct 6, 1998||SULP||Surcharge for late payment|
|Oct 6, 1998||FPAY||Fee payment|
Year of fee payment: 4
|May 11, 1999||PRDP||Patent reinstated due to the acceptance of a late maintenance fee|
Effective date: 19990312
|Mar 8, 2001||FPAY||Fee payment|
Year of fee payment: 8
|Apr 13, 2005||REMI||Maintenance fee reminder mailed|
|Sep 28, 2005||LAPS||Lapse for failure to pay maintenance fees|
|Nov 22, 2005||FP||Expired due to failure to pay maintenance fee|
Effective date: 20050928