|Publication number||US5252850 A|
|Application number||US 07/826,028|
|Publication date||Oct 12, 1993|
|Filing date||Jan 27, 1992|
|Priority date||Jan 27, 1992|
|Publication number||07826028, 826028, US 5252850 A, US 5252850A, US-A-5252850, US5252850 A, US5252850A|
|Inventors||William V. Schempp|
|Original Assignee||Photometrics Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (7), Referenced by (14), Classifications (10), Legal Events (12)|
|External Links: USPTO, USPTO Assignment, Espacenet|
Semiconductor, light responsive arrays such as Charge Coupled Devices (CCDs) or Charge Injection Devices (CIDs) are well known in the art. Such devices include an array of light sensitive cells each of which is responsive to light to store (or deplete) charge in proportion to light incident thereto during an exposure phase of a cycle of operation. The cells are arranged in rows and columns and the charges obtained during the exposure phase are moved along the columns, shift register fashion, to an output buffer between exposure phases. Such devices (CCDs) are well known to be useful as imaging devices in CCD cameras.
Devices of these types are made in various sizes, the manufacturing effort being directed at making ever larger chips with ever increasing numbers of cells. Chips having diameters from one to several centimeters are now commercially available with more than 256,000 cells per chip.
The invention is based on the recognition that semiconductor chips are not flat and the bow to the chips increases with the diameter of the chips. The curvature becomes significant particularly for chips having diameters of one centimeter or more. The curvature in the chips causes loss of resolution and general degradation in the image captured by the array of cells on the chip. Accordingly, the invention is directed at apparatus and a method for imposing a flat geometry to a semiconductor chip. Further, it is recognized that there are advantages to contouring such a semiconductor chip into a prescribed curvature for conforming to the image plane of a lens system.
Specifically, in one embodiment, a semiconductor, CCD imaging device is placed in a package on the surface of a mounting assembly, which has holes to the exterior of the package. The device is mounted over the holes on a bed of adhesive and a vacuum is applied through the holes to pull the (curved) wafer to conform to the flat surface of the mounting assembly. The cement, when dried, retains the chip in the desired planar configuration.
In a second embodiment, the surface of the mounting assembly is formed in a specified curvature. The CCD is again pulled into a shape to conform with the prescribed curvature and maintained in that curvature by the cement when dried.
FIG. 1 is a schematic, cross sectional view of a portion of a semiconductor package in accordance with the principles of this invention;
FIGS. 2 and 3 are schematic, cross sectional views of a semiconductor wafer and substrate of the package of FIG. 1; and
FIG. 4 is a flow diagram of the method for flattening bowed semiconductor wafers in accordance with the principles of this invention.
FIG. 1 shows a cross sectional view of a semiconductor wafer 10 in position on a rigid substrate 11. The wafer is positioned on the top surface 13 of the substrate and can be seen to have a curvilinear profile, shown exaggerated when compared to surface 13 which is shown as flat. Substrate 11 is made of glass or ceramic, or some other material suitable for semiconductor packaging.
The wafer is secured to surface 13 by adhesive or solder. One suitable material is a conductive epoxy. The substrate is secured to a surface 15 of a vacuum chuck 16. The vacuum chuck is equipped with a plurality of conduits 17A, 17B, . . . 17G, which extend between a relatively large conduit 18 and surface 15. Substrate 11 also is equipped with a matching set of conduits 20A, 20B, . . . 20G.
The curvilinear profile of chip 10 is eliminated by the establishment of a vacuum in conduit 18 and in the conduits 17i and 20i (where i is a dummy variable) shown as 17A and 17B, . . . 17G in the Figures. The vacuum is operative to adjust the chip profile to the shape of the surface 15. In the embodiment of FIG. 1, surface 13 is flat. Therefor chip 10 becomes flat. Substrate 11 is stiff enough so that it does not bend to conform to 15 (if that surface is not flat). The wafer is constrained in that shape by adhesive layer 21. the adhesive is set, illustratively, at 80 degrees centigrade in 90 minutes.
FIG. 2 shows chip 10 with the desired flat profile secured to substrate 11. Adhesive layer 21 is shown covering the tops of conduits 20A, 20B . . . 20G. The chip may now be coated with suitable protective coatings and packaged by encapsulation with, for example, a circular ring 25 having a transparent top 26.
FIG. 3 illustrates an embodiment in which the curvilinear profile of a chip 30 (having a curvilinear profile) is to be secured to the surface 31 of a substrate 32 where the surface 31 also has a curvilinear surface. But the profile of surface 31 is different from that of the chip. In this embodiment, a vacuum is provided in a manner similar to that described in connection with the embodiment of FIG. 1. The chip is secured to surface 31 by a layer of adhesive 33.
A non-flat profile for a chip is desirable in many instances to conform with a mating optical system and may be used to reduce the constraints on the optical system.
FIG. 4 shows a flow diagram of the method for changing the profile of a semiconductor chip in accordance with principles of this invention. The first step of the method is to place a chip with a nonflat profile on the surface of a substrate having a surface with the desired profile. This step is indicated by block 40 of FIG. 4.
The next step is to create a vacuum in the conduits of the substrate as indicated by block 41. The next step is to set the adhesive to retain the chip in the desired profile corresponding to that of the substrate surface. This step is represented by block 42.
The adhesive, for example, is EPO-TEK, H20E and sets in about 90 minutes at 80 degrees centigrade while under a vacuum of 10-4 TORR. A typical semiconductor chip of about two centimeters on a side has a non-linear profile of 30 micrometers and is made to conform to a contiguous flat (or non-flat) profile by a vacuum of about 10-4 TORR. A typical chip is 500 micrometers thick and can have its profile changed by as much as 30 micrometers without causing significant strain.
The conduits 17i and 20i have diameters of, for example, fifty thousandths and are formed by laser drilling. The substrates typically have dimensions of two centimeters on a side by one millimeter thick.
The adhesive enters the top of conduits 20i during the vacuum adjustment of the chip profile where it may remain without significant affect.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3588018 *||Sep 19, 1969||Jun 28, 1971||Fedders Corp||Mounting assembly|
|US4884124 *||Aug 17, 1987||Nov 28, 1989||Mitsubishi Denki Kabushiki Kaisha||Resin-encapsulated semiconductor device|
|US4942454 *||Aug 2, 1988||Jul 17, 1990||Mitsubishi Denki Kabushiki Kaisha||Resin sealed semiconductor device|
|US4962416 *||Apr 18, 1988||Oct 9, 1990||International Business Machines Corporation||Electronic package with a device positioned above a substrate by suction force between the device and heat sink|
|US4975765 *||Jul 7, 1989||Dec 4, 1990||Contraves Ag||Highly integrated circuit and method for the production thereof|
|US5072289 *||Nov 8, 1989||Dec 10, 1991||Nitto Denko Corporation||Wiring substrate, film carrier, semiconductor device made by using the film carrier, and mounting structure comprising the semiconductor device|
|US5172301 *||Oct 8, 1991||Dec 15, 1992||Lsi Logic Corporation||Heatsink for board-mounted semiconductor devices and semiconductor device assembly employing same|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US5614763 *||Mar 13, 1995||Mar 25, 1997||Zetetic Institute||Methods for improving performance and temperature robustness of optical coupling between solid state light sensors and optical systems|
|US5818035 *||Sep 16, 1996||Oct 6, 1998||Gatan, Inc.||Optically coupled large-format solid state imaging apparatus having edges of an imaging device|
|US5883778 *||Jul 18, 1995||Mar 16, 1999||Applied Materials, Inc.||Electrostatic chuck with fluid flow regulator|
|US6753208 *||Aug 19, 2002||Jun 22, 2004||Mcsp, Llc||Wafer scale method of packaging integrated circuit die|
|US7462943||Jun 13, 2007||Dec 9, 2008||Texas Instruments Incorporated||Semiconductor assembly for improved device warpage and solder ball coplanarity|
|US8809083 *||Mar 6, 2013||Aug 19, 2014||Advanced Optoelectronics Technology, Inc.||Method of manufacturing light emitting diode|
|US8987040||Jun 1, 2011||Mar 24, 2015||Kuka Systems Gmbh||Manufacturing means and process|
|US9490285 *||Nov 18, 2011||Nov 8, 2016||Sony Corporation||Solid-state imaging device and manufacturing method thereof, and electronic apparatus|
|US20080142949 *||Jun 13, 2007||Jun 19, 2008||Texas Instruments Incorporated||Semiconductor Assembly for Improved Device Warpage and Solder Ball Coplanarity|
|US20120147207 *||Nov 18, 2011||Jun 14, 2012||Sony Corporation||Solid-state imaging device and manufacturing method thereof, and electronic apparatus|
|US20130244358 *||Mar 6, 2013||Sep 19, 2013||Advanced Optoelectronic Technology, Inc.||Method of manufacturing light emitting diode|
|WO1997010672A1 *||Aug 27, 1996||Mar 20, 1997||Gatan, Inc.||Optically coupled large-format solid state imaging device|
|WO2007048090A3 *||Oct 17, 2006||Nov 20, 2008||Texas Instruments Inc||Semiconductor assembly for improved device warpage and solder ball coplanarity|
|WO2011151430A3 *||Jun 1, 2011||Apr 26, 2012||Kuka Systems Gmbh||Production device and method|
|U.S. Classification||257/433, 257/698, 257/783|
|International Classification||H01L21/683, H01L21/68|
|Cooperative Classification||H01L21/6838, H01L2924/3511, H01L21/6835|
|European Classification||H01L21/683T, H01L21/683V|
|Jun 15, 1992||AS||Assignment|
Owner name: PHOTOMETRICS LTD., ARIZONA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:SCHEMPP, WILLIAM V.;REEL/FRAME:006159/0956
Effective date: 19911216
|Apr 10, 1997||FPAY||Fee payment|
Year of fee payment: 4
|Jun 16, 1999||AS||Assignment|
Owner name: ROPER HOLDINGS, INC., DELAWARE
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ROPER SCIENTIFIC, INC.;REEL/FRAME:010024/0211
Effective date: 19990609
Owner name: ROPER SCIENTIFIC, INC., ARKANSAS
Free format text: MERGER;ASSIGNORS:PHOTOMETRICS, LTD.;PRINCETON INSTRUMENTS, INC.;REEL/FRAME:010024/0217
Effective date: 19980513
|Apr 12, 2001||FPAY||Fee payment|
Year of fee payment: 8
|Dec 23, 2003||AS||Assignment|
Owner name: ROPINTASSCO HOLDINGS, L.P., GEORGIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ROPER HOLDINGS, INC.;REEL/FRAME:014805/0957
Effective date: 20031128
|Feb 24, 2004||AS||Assignment|
Owner name: JPMORGAN CHASE BANK, TEXAS
Free format text: SECURITY AGREEMENT;ASSIGNOR:ROPINTASSCO HOLDINGS, L.P.;REEL/FRAME:014981/0256
Effective date: 20040206
|Apr 27, 2005||REMI||Maintenance fee reminder mailed|
|Oct 12, 2005||LAPS||Lapse for failure to pay maintenance fees|
|Dec 6, 2005||FP||Expired due to failure to pay maintenance fee|
Effective date: 20051012
|Mar 17, 2006||AS||Assignment|
Owner name: ROPER HOLDINGS, INC., DELAWARE
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ROPINTASSCO HOLDINGS, L.P.;REEL/FRAME:017314/0868
Effective date: 20060306
|Jul 25, 2008||AS||Assignment|
Owner name: ROPINTASSCO HOLDINGS, L.P., FLORIDA
Free format text: TERMINATION AND RELEASE OF SECURITY;ASSIGNOR:JPMORGAN CHASE BANK, N.A.;REEL/FRAME:021281/0956
Effective date: 20080701
|Dec 16, 2009||AS||Assignment|
Owner name: ROPER SCIENTIFIC, INC., ARIZONA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ROPER HOLDINGS, INC.;REEL/FRAME:023660/0040
Effective date: 20091203