Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS5270983 A
Publication typeGrant
Application numberUS 07/582,705
Publication dateDec 14, 1993
Filing dateSep 13, 1990
Priority dateSep 13, 1990
Fee statusPaid
Also published asUS5309394
Publication number07582705, 582705, US 5270983 A, US 5270983A, US-A-5270983, US5270983 A, US5270983A
InventorsWilliam J. Wuertz, Steven K. Stefek, William W. McKinley
Original AssigneeNcr Corporation
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Single element security fusible link
US 5270983 A
Abstract
An I/O circuit including first and second I/O pads, a fuse connected between the first pad and a RAM write enable line, and a diode-connected transistor connected between the RAM write enable line and second pad. Data is written to the RAM by applying a voltage potential to the pads after which the fuse is blown by increasing the potential difference. Other forms of the invention include a resistor connected between the RAM write enable line and ground, and I/O lines connected between the pads, respectively, and a logic circuit.
Images(1)
Previous page
Next page
Claims(15)
What is claimed is:
1. In an integrated circuit, an I/O circuit comprising:
first and second I/O pads;
a fuse connected between said first pad and a signal line; and
a diode connected between said signal line and second pad;
wherein said fuse and diode are series connected between said first and second I/O pads and the anode of said diode is connected to said fuse, and
wherein said signal line is a write enable line connected to a RAM.
2. In an integrated circuit, an I/O circuit comprising:
first and second I/O pads;
a fuse connected between said first pad and a signal line;
a diode connected between said signal line and second pad; and
a resistor connected between said signal line and a reference voltage terminal,
wherein said fuse and diode are series connected between said first and second I/O pads and the anode of said diode is connected to said fuse.
3. The circuit of claim 2 wherein said reference voltage terminal is ground.
4. The circuit of claim 3 further comprising:
an I/O line connected from said first pad to a logic circuit.
5. The circuit of claim 4 further comprising:
an I/O line connected from said second pad to a logic circuit.
6. In an integrated circuit, an I/O circuit comprising:
first and second I/O pads;
a fuse connected between said first pad and a signal line;
a first diode connected between said signal line and second pad; and
a second diode connected from said first pad to a reference voltage terminal,
wherein said fuse and first diode are series connected between said first and second I/O pads and the anode of said first diode is connected to said fuse.
7. The circuit of claim 6 wherein said second diode is an N channel transistor having its control electrode connected to said reference voltage terminal, and wherein said reference voltage terminal is ground.
8. In an integrated circuit, an I/O circuit comprising:
first and second I/O pads;
a fuse connected between said first pad and a signal line;
a first diode connected between said signal line and second pad;
a second diode connected from said second pad to a first reference voltage terminal, and
a third diode connected from said second pad to a second reference voltage terminal,
wherein said fuse and first diode are series connected between said first and second I/O pads and the anode of said first diode is connected to said fuse.
9. The circuit of claim 8 wherein said second diode is an N channel transistor having its control electrode connected to said first reference voltage terminal, and wherein said third diode is a P channel transistor having its control electrode connected to said second reference voltage terminal.
10. The circuit of claim 9 wherein said first reference voltage terminal is ground and said second reference voltage terminal is about 5 volts.
11. An I/O circuit comprising:
first and second I/O pads;
a fuse connected between said first pad and a signal line;
a first diode connected between said signal line and second pad;
a resistor connected between said signal line and a first reference voltage terminal;
a first I/O line connected from said first fuse pad to a logic circuit;
a second I/O line connected from said second fuse pad to said logic circuit;
a second diode connected from said first pad to said first reference voltage terminal;
a third diode connected from said second pad to said first reference voltage terminal; and
a fourth diode connected from said second pad to a second reference voltage terminal.
12. The circuit of claim 11 wherein said first diode is an N channel transistor having its control electrode connected to said signal line.
13. The circuit of claim 12 wherein said second diode is an N channel transistor having its control electrode connected to said first reference voltage terminal, wherein said third diode is an N channel transistor having its control electrode connected to said first reference voltage terminal, wherein said fourth diode is a P channel transistor having its control electrode connected to said second reference voltage terminal, and wherein said first reference voltage terminal is ground and said second reference voltage terminal is about 5 volts.
14. The circuit of claim 13 wherein each of said transistors is MOSFET.
15. The circuit of claim 14 wherein said signal line is a write enable line connected to a RAM.
Description

The present invention relates generally to integrated circuits (ICs). More particularly, it relates to input/output (I/O) circuits for ICs and to fusible links which provide security for ICs.

BACKGROUND OF THE INVENTION

Integrated circuit chips are used in a multitude of different applications, many requiring some form of security for data stored on the chip. Typically, a means is provided to prevent data stored on the chip from being read by an external agent. Under certain circumstances it may also be desirable to prevent data from being written onto the chip. For example, data stored on the chip may be used as a key to decipher or decode a public signal such a scrambled satellite video signal. Even if the stored data can not be read, if the stored data can be overwritten by an external agent, the code may be broken by a systematic overwriting of the data and iterative comparisons to the scrambled signal.

A read only memory (ROM) is a typical memory device which can not be overwritten. However, ROMs are programmed during manufacture which can create security problems for the end user who may desire to keep its code confidential. A programmable read only memory (PROM) may be programmed by the end user, thereby avoiding confidentiality problems. However, a PROM is less secure since it maintains its contents when voltage is removed, allowing the contents to be microprobed. The code in a PROM can also be read with an electron beam. Furthermore, a PROM is more expensive to produce than a RAM.

To the extent that previous security measures include the use of I/O pads on the chip, such pads are most likely dedicated exclusively to the security function. As the need to provide additional signal lines to a chip increases, the use of I/O pads for limited or one-time security functions is undesirable. This is particularly true if the pads are needed only to initially secure the data on the chip and are not required for normal operations.

OBJECTS OF THE INVENTION

It is therefore an object of the present invention to provide a new and improved I/O circuit.

It is another object of the present invention to provide a circuit for securing data on an integrated circuit.

It is a further object of the present invention to provide a circuit for preventing stored data on a chip from being overwritten.

It is yet another object of the present invention to provide single element security fusible link for an I/O circuit.

It is yet a further object of the present invention to provide an I/O circuit with multifunction I/O pads.

It is still another object of the present invention to provide an I/O circuit having a fusible link and increased resistance to voltage spikes on the I/O pads.

SUMMARY OF THE INVENTION

The present invention is an I/O circuit comprising first and second I/O pads, a fuse connected between the first pad and a signal line, and a diode connected between the signal line and second pad. In a preferred embodiment, the diode is a diode connected transistor. Other forms of the invention include a resistor connected between the signal line and ground, and I/O lines connected between the pads, respectively and a logic circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of an I/O circuit according to one form of the present invention.

FIG. 2 shows the physical layout of the fuse F in FIG. 1.

DESCRIPTION OF A PREFERRED EMBODIMENT

FIG. 1 shows an I/O circuit 10 which may be embodied in an integrated circuit logic chip. Circuit 10 includes I/O pads 12 and 14 which are typically located on the periphery of a chip together with a plurality of other I/O pads for transmitting signals to and receiving signals from the chip. Circuit 10 also includes a fuse F and a diode connected transistor Q1. Fuse F and transistor Q1 are series connected between I/O pad 12 and I/O pad 14 with fuse F connected between a signal line 16 and pad 12, and transistor Q1 connected between signal line 16 and pad 14.

In a preferred embodiment, fuse F is made of Al, 1% Si, and 0.05% Cu, and has a range of cross-sectional areas from 1.10 to 1.52 (micrometers)2. Current pulse requirements is about 460 mA for the minimum cross-sectional area, and about 540 mA for the maximum cross-sectional area. FIG. 2 shows a more detail view of fuse F with exemplary dimensions provided. For additional security, fuse F when implemented in an integrated circuit may be covered with a dielectric which is overlayed with another metalization layer. This arrangement should deter access by microprobing of the circuit.

Referring again to FIG. 1, diode connected transistor Q1 is arranged so that the equivalent diode anode is connected to signal line 16. For transistor Q1, this means that its control electrode is connected to signal line 16. Preferably, transistor Q1 is an N-type MOSFET with gate and drain connected to signal line 16. I/O circuit 10 also includes a resistor R connected between signal line 16 and a reference voltage terminal 18. For a CMOS implementation of the present invention, reference voltage terminal 18 is ground.

Another feature of I/O circuit 10 is I/O lines 20 and 22. I/O line 20 is connected from fuse pad 12 to other elements of the logic circuit sharing the chip with circuit 10. Similarly, I/O line 22 is connected from fuse pad 14 to other elements of the logic circuit.

A further feature of I/O circuit 10 is diode connected transistors Q2, Q3 and Q4. Diode connected transistor Q2 is connected from I/O pad 12 to reference voltage terminal 18. Preferably, transistor Q2 is an N channel MOSFET having its control electrode connected to terminal 18. Diode connected transistor Q3 is connected from pad 14 to reference voltage terminal 18, and diode connected transistor Q4 is connected from pad 14 to reference voltage terminal VDD. Preferably, transistor Q3 is an N channel MOSFET having its control electrode connected to terminal 18, and transistor Q4 is a P channel MOSFET having its control electrode connected to terminal VDD. For a CMOS implementation of the present invention, VDD is about 5 volts and, as noted above, reference voltage terminal 18 is ground. In a preferred embodiment, the width/length of transistor Q1 is 4310 microns/1.5 microns, transistor Q2 is 2200 microns/1.5 microns, transistors Q3 and Q4 are each 1100 microns/1.5 microns, and the resistance of R is 7K ohms.

The various forms of the present invention will have many applications, as will be evident to those skilled in the art. However, an important application of the present invention is to prevent write access to a RAM after its initial loading with data. In such an application, signal line 16 is the write enable line of the RAM. The following discussion will assume signal line 16 is a RAM write enable line.

In operation, write enable line 16 is pulled active high by applying a voltage potential of about 5.0 volts to I/O pad 12. Data can then be written to the RAM. After data is stored in the RAM, fuse F is blown by applying about 7.0 volts to I/O pad 12 while grounding I/O pad 14. Thereafter, write enable line 16 can not be accessed through I/O pad 12 because of the open circuit. Nor can line 16 be pulled high by a voltage applied to I/O pad 14, because transistor Q1 is always off by virtue of its gate being grounded through resistor R. Thus, the present invention provides a simple yet effective design for preventing write accesses to the RAM.

After fuse F is blown, I/O pads 12 and 14 can operate as normal I/O pads with access to logic circuitry through I/O lines 20 and 22. Accordingly, I/O pads 12 and 14 are multifunctional, thereby reducing the required number of pads on the integrated circuit chip.

Voltage transient protection is provided by transistors Q2, Q3 and Q4. Transistors Q2, Q3 and Q4 either forward bias or breakdown in the presence of voltage spikes. In this manner, they prevent damage to the logic circuit when subjected to large voltage, low amperage spikes such as caused by electrostatic discharge. For example, in the presence of a voltage spike greater than VDD +0.6 volts, diode connected transistor Q4 is activated thereby shunting harmful current and voltage build-up to the VDD supply.

It will be clear to those skilled in the art that the present invention is not limited to the specific embodiment disclosed and illustrated herein. It will be understood that the dimensions shown in FIG. 2 are exemplary and are not intended to be limiting. Numerous modifications, variations, and full and partial equivalents can be undertaken without departing from the invention as limited only by the spirit and scope of the appended claims.

What is desired to be secured by Letters Patent of the United States is as follows.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US4157480 *Jul 22, 1977Jun 5, 1979National Research Development CorporationInverters and logic gates employing inverters
US4417154 *Feb 8, 1982Nov 22, 1983Motorola, Inc.Circuit for applying a high voltage signal to a fusible link
US4446534 *Dec 8, 1980May 1, 1984National Semiconductor CorporationProgrammable fuse circuit
US4480199 *Mar 19, 1982Oct 30, 1984Fairchild Camera & Instrument Corp.Identification of repaired integrated circuits
US4903111 *Oct 25, 1988Feb 20, 1990Fujitsu LimitedIntegrated circuit device
US4933898 *Jan 12, 1989Jun 12, 1990General Instrument CorporationSecure integrated circuit chip with conductive shield
US4935645 *Mar 2, 1988Jun 19, 1990Dallas Semiconductor CorporationFusing and detection circuit
US5065057 *Jan 17, 1990Nov 12, 1991Kabushiki Kaisha ToshibaAnalog signal input circuit
JPH02189799A * Title not available
JPH02192093A * Title not available
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US5448199 *Jan 3, 1994Sep 5, 1995Samsung Electronics Co., Ltd.Internal supply voltage generation circuit
US5617366 *Dec 12, 1995Apr 1, 1997Samsung Electronics Co., Ltd.Method and apparatus for a test control circuit of a semiconductor memory device
US6518823Aug 24, 2000Feb 11, 2003Sony Computer Entertainment Inc.One-time programmable logic device
US7335957 *Aug 12, 2004Feb 26, 2008Samsung Electronics Co., Ltd.Semiconductor memory integrated circuit and layout method of the same
US7583554Mar 2, 2007Sep 1, 2009Freescale Semiconductor, Inc.Integrated circuit fuse array
US7787323Apr 27, 2007Aug 31, 2010Freescale Semiconductor, Inc.Level detect circuit
US8157178Oct 19, 2007Apr 17, 2012First Data CorporationManufacturing system to produce contactless devices with switches
WO2001016961A1 *Aug 29, 2000Mar 8, 2001Sony Comp Entertainment IncElectric/electronic circuit device
Classifications
U.S. Classification365/225.7, 326/37, 365/175, 327/546, 365/52, 365/189.14, 711/104, 365/63, 327/525, 365/148
International ClassificationG11C7/24
Cooperative ClassificationG11C7/24
European ClassificationG11C7/24
Legal Events
DateCodeEventDescription
Aug 19, 2008ASAssignment
Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TAIW
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:NCR CORPORATION;MAGNACHIP SEMICONDUCTOR, LTD.;REEL/FRAME:021398/0702;SIGNING DATES FROM 20071114 TO 20071115
May 17, 2005FPAYFee payment
Year of fee payment: 12
Apr 28, 2005ASAssignment
Owner name: HYUNDAI ELECTRONICS AMERICA, CALIFORNIA
Free format text: RELEASE OF SECURITY INTEREST;ASSIGNOR:LEHMAN COMMERICAL PAPER INC.;REEL/FRAME:016602/0895
Effective date: 20050107
Owner name: SYMBIOS, INC., COLORADO
Free format text: RELEASE OF SECURITY INTEREST;ASSIGNOR:LEHMAN COMMERICAL PAPER INC.;REEL/FRAME:016602/0895
Effective date: 20050107
Owner name: SYMBIOS, INC. 2001 DANFIELD CT.FORT COLLINS, COLOR
Free format text: RELEASE OF SECURITY INTEREST;ASSIGNOR:LEHMAN COMMERICAL PAPER INC. /AR;REEL/FRAME:016602/0895
Mar 25, 2005ASAssignment
Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL TRUS
Free format text: SECURITY INTEREST;ASSIGNOR:MAGNACHIP SEMICONDUCTOR, LTD.;REEL/FRAME:016470/0530
Effective date: 20041223
Free format text: SECURITY INTEREST;ASSIGNOR:MAGNACHIP SEMICONDUCTOR, LTD. /AR;REEL/FRAME:016470/0530
Jan 10, 2005ASAssignment
Owner name: MAGNACHIP SEMICONDUCTOR, LTD., KOREA, REPUBLIC OF
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HYNIX SEMICONDUCTOR, INC.;REEL/FRAME:016216/0649
Effective date: 20041004
Owner name: MAGNACHIP SEMICONDUCTOR, LTD. 1 HYANGJEONG-DONG, H
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HYNIX SEMICONDUCTOR, INC. /AR;REEL/FRAME:016216/0649
Oct 12, 2004ASAssignment
Owner name: HYNIX SEMICONDUCTOR AMERICA INC., CALIFORNIA
Free format text: CHANGE OF NAME;ASSIGNOR:HYUNDAI ELECTRONICS AMERICA;REEL/FRAME:015246/0599
Effective date: 20010412
Owner name: HYNIX SEMICONDUCTOR INC., KOREA, REPUBLIC OF
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HYNIX SEMICONDUCTOR AMERICA, INC.;REEL/FRAME:015279/0556
Effective date: 20040920
Owner name: HYNIX SEMICONDUCTOR AMERICA INC. 510 COTTONWOOD DR
Free format text: CHANGE OF NAME;ASSIGNOR:HYUNDAI ELECTRONICS AMERICA /AR;REEL/FRAME:015246/0599
Owner name: HYNIX SEMICONDUCTOR INC. SAN 136-1, AMI-RI, BUBAL-
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HYNIX SEMICONDUCTOR AMERICA, INC. /AR;REEL/FRAME:015279/0556
Jun 13, 2001FPAYFee payment
Year of fee payment: 8
Dec 4, 1998ASAssignment
Owner name: HYUNDAI ELECTRONICS AMERICA, CALIFORNIA
Free format text: TERMINATION AND LICENSE AGREEMENT;ASSIGNOR:SYMBIOS, INC.;REEL/FRAME:009596/0539
Effective date: 19980806
Nov 27, 1998ASAssignment
Owner name: LEHMAN COMMERCIAL PAPER INC., AS ADMINISTRATIVE AG
Free format text: SECURITY AGREEMENT;ASSIGNORS:HYUNDAI ELECTRONICS AMERICA, A CORP. OF CALIFORNIA;SYMBIOS, INC., A CORP. OF DELAWARE;REEL/FRAME:009396/0441
Effective date: 19980226
Mar 10, 1998ASAssignment
Owner name: SYMBIOS, INC ., COLORADO
Free format text: CHANGE OF NAME;ASSIGNOR:SYMBIOS LOGIC INC.;REEL/FRAME:009089/0936
Effective date: 19971210
Apr 17, 1997FPAYFee payment
Year of fee payment: 4
Aug 28, 1995ASAssignment
Owner name: SYMBIOS LOGIC INC., COLORADO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HYUNDAI ELECTRONICS AMERICA;REEL/FRAME:007629/0431
Effective date: 19950818
Mar 14, 1995ASAssignment
Owner name: HYUNDAI ELECTRONICS AMERICA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AT&T GLOBAL INFORMATION SOLUTIONS COMPANY (FORMERLY KNOWN AS NCR CORPORATION);REEL/FRAME:007408/0104
Effective date: 19950215
Sep 13, 1990ASAssignment
Owner name: NCR CORPORATION, A CORP. OF MD, OHIO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:WUERTZ, WILLIAM J.;STEFEK, STEVEN K.;MCKINLEY, WILLIAM W.;REEL/FRAME:005442/0349
Effective date: 19900907