|Publication number||US5289426 A|
|Application number||US 07/711,800|
|Publication date||Feb 22, 1994|
|Filing date||Jun 7, 1991|
|Priority date||Jun 11, 1990|
|Publication number||07711800, 711800, US 5289426 A, US 5289426A, US-A-5289426, US5289426 A, US5289426A|
|Inventors||Keiji Namimoto, Hiromasa Hayashi|
|Original Assignee||Kabushiki Kaisha Toshiba|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (5), Referenced by (4), Classifications (7), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates to a random access memory, and particularly to a dual port memory having an address conversion function.
2. Description of the Prior Art
As VLSI technology develops, various memory systems have been proposed. One of such memory systems used in the microprocessor technology is a dual port memory which has two data reading/writing systems (ports). For example, a Transputer-type CPU employs two microprocessors connected to a common memory to simultaneously access it to exchange data. This technique is useful in forming a parallel processing system.
The dual port memory has quite different configuration from a single port memory and it has a possibility of being applied for various fields. This possibility, however, has not been developed yet.
The inventor opened up the possibility of the dual port memory and devised this invention.
An object of the invention is to provide a memory which can handle data according to a plurality of coordinate systems.
Another object of the invention is to provide a high-speed dual port memory.
Still another object of the invention is to provide a high-speed memory which is appropriate for graphics processing.
In order to accomplish the objects, the invention provides a dual port memory comprising a memory array and two ports for writing and reading data to and from the memory array. Each of the ports has an address circuit for outputting an access signal for accessing an address of the memory array, an input/output circuit for sending and receiving data to and from the address of the memory array specified by the address circuit, and a control circuit for controlling the address circuit and input/output circuit. Each of the address circuits of the ports has a function of receiving addressing information based on a different coordinate system and converting the information into an access signal for accessing the memory array.
This dual port memory can handle data at high speed according to a plurality of coordinate systems.
FIG. 1 is a block diagram showing a dual port memory according to a first embodiment of the invention;
FIGS. 2 and 3 are views showing examples of coordinate systems according to the invention; and
FIG. 4 is a block diagram showing a dual port memory according to a second embodiment of the invention.
FIG. 1 shows a dual port memory according to the first embodiment of the invention. The dual port memory comprises a memory array (RAM) 5 and two ports 10 and 20 for writing and reading data to and from the memory array 5. The port 10 (20) has an address circuit 13 (23) for outputting an access signal A for accessing a physical address in the memory array 5, an input/output circuit 15 (25) for sending and receiving data D(P) to and from an address of the memory array 5 specified by the address circuit 13 (23), and a control circuit 17 (27) for controlling the address circuit 13 (23) and input/output circuit 15 (25) in accordance with control signals C(P) or C(Q). The address circuit 13 (23) of the port 10 (20) receives addressing information A(P) or A(Q) based on different coordinate systems and converts the information into an access signal A for accessing the memory array 5.
The address circuit 13 (23) receives, in addition to the address based on the coordinate system, a signal for specifying coordinate conversion. According to the coordinate conversion specifying signal, a conversion table expressing internal coordinate conversion can be rewritten by the use of the A(P), C(P), D(P) or A(Q), C(Q), D(Q) signals. The address conversion circuit 13(23) may be provided with address conversion functions. PLA, ROM and PROM are simple examples suitable for storing such functions. If such functions are stored in a RAM, the address conversion functions, i.e. corresponding cordinate conversion table, can be rewritten by rewriting the content of the RAM.
Examples of the coordinate systems of the dual port memory are shown in FIGS. 2 and 3. FIG. 2 shows first and second coordinate systems, i.e., a rectangular coordinate system with an original point Q and a polar coordinate system with an original point P, and FIG. 3 shows first and second coordinate systems, i.e., a polar coordinate system with an original point Q and a polar coordinate system with an original point P.
In any one of the polar coordinate systems, a distance R from the original point to a point to be accessed, and an elongation with respect to a predetermined straight line are given as A(P), which is converted by the address circuit 13 into an internal address A. Generally, an original point may properly be set, and a proper straight or curved line and a rectangular or oblique coordinate system may properly be selected.
Supposing the internal address is A and coordinate variables X and Y, conversion of the first coordinate system will be A1=f1(X, Y) and that of the second coordinate system will be A2=f2(X, Y). In FIGS. 2 and 3, data in the memory array addressed with these addresses is expressed as S=M(X, Y).
FIG. 4 shows the second embodiment of the invention. In this embodiment, an address switching circuit 31 supplies an addressing signal A to a memory array 5. The address switching circuit 31 is connected to a first address circuit 33 and a second address circuit 35, and accesses the memory array 5 according to a signal from one of the address circuits 33 and 35. In this embodiment, two systems (ports) 10 and 20 cannot simultaneously access the memory array 5 but access it in a time-sharing manner. Input/output circuits 37 and 39 are connected to the memory array 5 through a data switching circuit 41 so that data accessed by the first system 10 may be handled by the first system 10, and data accessed by the second system 20 may be handled by the second system 20. Control circuits 43 and 45 are the same as the control circuits 17 and 27 of the first embodiment.
In summary, the present invention provides a dual port memory which can handle data at high speed with use of addresses expressed on a plurality of coordinate systems. When employed for graphics processing, the dual port memory demonstrates a remarkable effect.
Various modifications will become possible for those skilled in the art after receiving the teachings of the present disclosure without departing from the scope thereof.
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|U.S. Classification||365/230.05, 365/230.08|
|International Classification||G11C11/401, G11C7/10, G11C11/41|
|Jun 7, 1991||AS||Assignment|
Owner name: KABUSHIKI KAISHA TOSHIBA, JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:NAMIMOTO, KEIJI;HAYASHI, HIROMASA;REEL/FRAME:005737/0255
Effective date: 19910517
|Aug 11, 1997||FPAY||Fee payment|
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