|Publication number||US5307300 A|
|Application number||US 07/825,976|
|Publication date||Apr 26, 1994|
|Filing date||Jan 27, 1992|
|Priority date||Jan 30, 1991|
|Publication number||07825976, 825976, US 5307300 A, US 5307300A, US-A-5307300, US5307300 A, US5307300A|
|Inventors||Eiji Komoto, Kazuhiko Maki|
|Original Assignee||Oki Electric Industry Co., Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (5), Non-Patent Citations (2), Referenced by (21), Classifications (9), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention relates to a processing unit such as the integer unit of a reduced-instruction-set-computer (referred to below as a RISC processor), more particularly to a processing unit that can execute machine-language instructions comprising both an arithmetic or logic operation and a data transfer.
Statements involving both an arithmetic operation and a data transfer abound in, for example, the widely used C programming language. Two examples follow:
Example (1) includes a prefix increment operation: first the value of y is incremented, then the incremented value is assigned to x. In example (2) incrementation is a suffix operation: first the value of y is assigned to x, then y itself is incremented.
When these statements are executed by, for example, a prior-art RISC processor, the values of x and y are stored in registers. Execution of the statement requires two machine-language instructions: one to increment the register containing the value of y, and one to transfer the original or incremented value to the register containing the value of x. Each machine-language instruction executes in one clock cycle, so the entire operation takes two clock cycles.
Data transfers preceded or followed by arithmetic and logic operations like these are extremely common in computer programs. It would be desirable to have a processing unit capable of executing such transfer-and-operation combinations more rapidly: in just one clock cycle, for example.
It is accordingly an object of the present invention to execute a data transfer simultaneously with a prefix operation.
Another object of the invention is to execute a data transfer simultaneously with a suffix operation.
Yet another object of the invention is to execute two data transfers simultaneously.
The invented processing unit comprises a register file with a plurality of registers, a first data bus that receives first data from a first register in the register file, and a second data bus that receives second data from a second register in the register file. An arithmetic-logic unit performs arithmetic and logic operations on the first data and second data to produce third data. A third data bus receives the third data from the arithmetic-logic unit.
A selection means coupled to the first data bus and the third data bus selects either the first data or the third data for input to a third register in the register file, and selects either the first data or the third data for input to a fourth register in the register file. A control means selects the first, second, third, and fourth registers.
FIG. 1 is a block diagram illustrating a preferred embodiment of a processing unit according to the present invention.
FIG. 2 is an instruction diagram illustrating the structure of a machine-language instruction executed by the processing unit of FIG. 1.
An embodiment of the invention will be described with reference to the drawings. The drawings are shown for illustrative purposes; they do not restrict the scope of the invention, which should be determined solely from the appended claims.
Referring to FIG. 1, the processing unit has a control unit 101, part of which is an instruction decoding circuit 103. The control unit 101 reads machine-language instructions from a memory 105 and decodes each instruction to a set of control signals. Two of these control signals are register address signals carried on signal lines 107 and 109, shown for simplicity in the drawing as one line each but actually consisting of a plurality of signal lines each. Other control signals will be described later.
The processing unit also has a register file 110 comprising a plurality of registers r0, r1, r2, . . . , rn, designated by reference numerals 111, 113, 115, . . . , 119. Each of these registers is coupled to two buses: an A bus 121 and a B bus 123. The A bus 121 receives first data from a first source register selected by the register address on the signal line 107 and conveys the data to an arithmetic-logic unit 125. The B bus 123 receives second data from a second source register selected by the register address on the signal line 109 and conveys the data to the arithmetic-logic unit 125. The first source register and the second source register may be different registers, or they may be the same register.
In response to control signals received from the control unit 101 via a signal line 127 (shown for convenience as a single line in the drawing but actually comprising a plurality of signal lines), the arithmetic-logic unit 125 performs an arithmetic or logic operation on the first data and second data to produce third data, which it places on a C bus 129.
Corresponding to the registers 111, 113, . . . , 119, the control unit 101 has signal lines 131, 133, . . . , 139 that control a selection unit 140 comprising data selectors 141, 143, . . . , 149. Each data selector is coupled to the C bus 129 and to an extension 151 which is part of the A bus. Responding independently to signals on the signal lines 131, 133, . . . , 139, the data selectors 141, 143, . . . , select either the data from the C bus 129 or the data from the A bus extension 151 and provide the selected data to the corresponding registers 111, 113, . . . , 119.
The signal line 153 from the control unit 101 to the register file 110 (shown as a single line in the drawings but actually comprising a plurality of signal lines) selects two destination registers in the register file 110. Data provided from the data selectors 141, 143, . . . , 149 can be written only into the two selected destination registers; the contents of other registers remain unchanged. The two destination registers may be different registers or the same register, and may be different from or the same as either of the source registers.
FIG. 2 shows the configuration of a machine-language instruction as stored in an instruction register in the control unit 101. The instruction comprises an op-code field 401, a first source register field 403, a second source register field 405, a first destination register field 407, and a second destination register field 409.
The first source register field 403 selects the register that is to provide data to the A bus. The second source register field 405 selects the register that is to provide data to the B bus. The first destination register field 407 selects a register that may receive data from the selection unit 140. The second destination register field 409 selects another register that may receive data from the selection unit 140. The op-code field 401 specifies an arithmetic or logic operation to be performed by the arithmetic-logic unit 125, specifies whether the registers selected by the first destination register field 407 and the second destination register field 409 are to receive data from the C bus 129 or the A bus extension 151 via the selection unit 140, and enables or disables data input to these registers.
The invention is not restricted to this particular configuration of instruction fields. For example, the fields may be arranged in a different order, or the op-code field 401 may be broken up and distributed at two or more locations in the instruction word.
Next the operation will be described by explaining how the invented processing unit executes three instructions: one performing a data transfer with a suffix operation, one performing a data transfer with prefix operation, and one performing only an arithmetic operation with no additional data transfer.
The first instruction performs, for example, the following data transfer and suffix-type addition operation:
r.sub.0 +r.sub.1 →r.sub.3
That is, it transfers the contents of register r0 to register r2, adds the contents of register r0 to register r1, and writes the sum in register r3.
Referring to FIGS. 1 and 2, the instruction decoding circuit 103 decodes the first source register field 403 and second source register field 405 of this instruction to a pair of control signals on the signal lines 107 and 109 that cause the A bus to receive the contents of register r0 111 and the B bus to receive the contents of register r1 113. The op-code field 401 is decoded to a control signal on the signal line 127 that causes the arithmetic-logic unit 125 to add the data on the A bus to the data on the B bus and place the sum on the C bus. The op-code field 401 and the first destination register field 407 are decoded to a signal on the signal line 135 that causes the data selector 145 to select the A bus extension 151. The op-code field 401 and the second destination register field 409 are decoded to a signal on the signal line 137 that causes the data selector 147 to select the C bus 129. The op-code field 401, the first destination register field 407, and the second destination register field 409 are decoded to signals on the signal line 153 that enable input to register r2 115 and register r3 117.
Thus the contents of register r0 111 are transferred via the A bus 121, the A bus extension 151, and the data selector 145 to register r2 115. At the same time, the contents of registers r0 and r1 are both sent to the arithmetic-logic unit 125 which adds them together, and the sum is input via the C bus 129 and the data selector 147 to register r3 117. All these operations are completed in one clock cycle.
A prior-art processing unit with only three operands would require two clock cycles. One clock cycle would be spent transferring the contents of register r0 to register r2, then a second clock cycle would be needed to add the contents of registers r0 and r1 and place the sum in register r3.
The second instruction performs, for example, the following data transfer and prefix-type addition operation:
r.sub.0 +r.sub.1 →r.sub.2
r.sub.0 +r.sub.1 →r.sub.3
That is, it adds the contents of register r0 to register r1, and writes the sum in both register r2 and register r3.
Referring to FIG. 1, this second instruction is executed in exactly the same way as the first instruction except that the signal on the signal line 135 causes the data selector 145 to select the C bus 129. The sum is thus input simultaneously to both register r2 115 and register r3 117. Neither register receives data from the A bus extension 151.
This second instruction also performs in one clock cycle an operation that would have taken two clock cycles in the prior art. In the prior art, for example, a first machine instruction would assign the sum of r0 and r1 to r2, then a second machine instruction would copy the contents of r2 to r3.
The third instruction performs, for example, only the following addition operation:
r.sub.0 +r.sub.1 →r.sub.2
That is, it adds the contents of register r0 to register r1, and writes the sum only in register r2.
Referring to FIG. 1, this third instruction is executed like the second instruction except that the signal line 153 carries a signal enabling input only to register r2 115. The data selector 135 selects the C bus 129. Thus the sum r1 +r2 is written in register r2 115, but nothing is written in any other register. This third instruction is similar to instructions executed in the prior art.
Since this third instruction has only a single destination register, the address of register r2 may be placed in both the first and second destination register fields 407 and 409 in FIG. 2. Alternatively, one of the two destination register fields 407 and 409 may be ignored, or used for another purpose.
In the preceding three examples the arithmetic-logic unit 125 performed an addition operation, but other arithmetic and logic operations are of course possible. The prefix and suffix incrementing operations (1) and (2) discussed in the background of the invention, for example, can be performed by having the arithmetic-logic unit 125 ignore the data on the A bus 121, increment the data on the B bus 123, and place the incremented value on the C bus 129. In this case the second source register and second destination register are the same register.
Another useful operation can be performed by having the arithmetic-logic unit 125 simply transfer the contents of the B bus 123 to the C bus 129. If this operation is performed as a prefix operation, two data transfers are accomplished simultaneously: the contents of the first source register are transferred via the A bus 121 and the A bus extension 151 to the first destination register, while the contents of the second source register are transferred via the B bus 123, the arithmetic-logic unit 125, and the C bus 129 to the second destination register. If this operation is performed as a suffix operation, the contents of a single source register can be simultaneously transferred to two destination registers.
The ability of the invented processing unit to carry out both an arithmetic or logic operation and a data transfer at once, or to carry out two data transfers at once, leads to significant gains in software execution speed. Programs coded in high-level languages such as C language can be compiled into machine-language programs that run considerably faster than in the prior art.
Applications of this invention are not limited to the integer unit of a RISC processor, and no restriction is placed on the number of registers in the register file in FIG. 1, the bit length of the registers, the types of operations performed by the arithmetic-logic unit, or the length of the instruction word in FIG. 2.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4773006 *||Dec 24, 1985||Sep 20, 1988||Hitachi, Ltd.||Vector operation designator|
|US4922418 *||Jan 15, 1988||May 1, 1990||The Johns Hopkins University||Method for controlling propogation of data and transform through memory-linked wavefront array processor|
|US4949292 *||May 14, 1988||Aug 14, 1990||Fujitsu Limited||Vector processor for processing recurrent equations at a high speed|
|US4967343 *||Sep 9, 1983||Oct 30, 1990||International Business Machines Corp.||Pipelined parallel vector processor including parallel configured element processors for processing vector elements in parallel fashion|
|US5073970 *||Jan 24, 1990||Dec 17, 1991||Hitachi, Ltd.||Vector processing apparatus allowing succeeding vector instruction chain processing upon completion of decoding of a preceding vector instruction chain|
|1||*||Glenford J. Myers and David L. Budde, The 80960 Microprocessor Architecture, pp. 195 199 of Japanese translation published by Maruzen.|
|2||Glenford J. Myers and David L. Budde, The 80960 Microprocessor Architecture, pp. 195-199 of Japanese translation published by Maruzen.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US5459682 *||Apr 26, 1994||Oct 17, 1995||Kabushiki Kaisha Toshiba||Microcomputer with plural registers and function for selecting them|
|US5473557 *||Jun 9, 1994||Dec 5, 1995||Motorola, Inc.||Complex arithmetic processor and method|
|US5532938 *||Sep 15, 1994||Jul 2, 1996||Mitsubishi Denki Kabushiki Kaisha||Numerical arithmetic processing unit|
|US5636150 *||Apr 3, 1995||Jun 3, 1997||Sharp Kabushiki Kaisha||Data driven type digital filter unit and data driven type information processor including the same|
|US5636153 *||Oct 19, 1994||Jun 3, 1997||Yamaha Corporation||Digital signal processing circuit|
|US5778416 *||Apr 3, 1997||Jul 7, 1998||Motorola, Inc.||Parallel process address generator and method|
|US5909572 *||Dec 2, 1996||Jun 1, 1999||Compaq Computer Corp.||System and method for conditionally moving an operand from a source register to a destination register|
|US5941938 *||Dec 2, 1996||Aug 24, 1999||Compaq Computer Corp.||System and method for performing an accumulate operation on one or more operands within a partitioned register|
|US6009505 *||Dec 2, 1996||Dec 28, 1999||Compaq Computer Corp.||System and method for routing one operand to arithmetic logic units from fixed register slots and another operand from any register slot|
|US6047372 *||Apr 13, 1999||Apr 4, 2000||Compaq Computer Corp.||Apparatus for routing one operand to an arithmetic logic unit from a fixed register slot and another operand from any register slot|
|US6061521 *||Dec 2, 1996||May 9, 2000||Compaq Computer Corp.||Computer having multimedia operations executable as two distinct sets of operations within a single instruction cycle|
|US6073155 *||Jul 28, 1997||Jun 6, 2000||Fuji Xerox Co., Ltd.||Floating-point accumulator|
|US6141673 *||May 25, 1999||Oct 31, 2000||Advanced Micro Devices, Inc.||Microprocessor modified to perform inverse discrete cosine transform operations on a one-dimensional matrix of numbers within a minimal number of instructions|
|US6154831 *||Apr 22, 1999||Nov 28, 2000||Advanced Micro Devices, Inc.||Decoding operands for multimedia applications instruction coded with less number of bits than combination of register slots and selectable specific values|
|US6173366||Dec 2, 1996||Jan 9, 2001||Compaq Computer Corp.||Load and store instructions which perform unpacking and packing of data bits in separate vector and integer cache storage|
|US6209013 *||Dec 13, 1999||Mar 27, 2001||Altocom, Inc.||Efficient implementation of a filter|
|US6298438||May 3, 1999||Oct 2, 2001||Advanced Micro Devices, Inc.||System and method for conditional moving an operand from a source register to destination register|
|US6446193 *||Sep 8, 1997||Sep 3, 2002||Agere Systems Guardian Corp.||Method and apparatus for single cycle processing of data associated with separate accumulators in a dual multiply-accumulate architecture|
|US6618739 *||Feb 22, 2001||Sep 9, 2003||Altocom, Inc.||Digital filter implementation suitable for execution, together with application code, on a same processor|
|US7398288||Aug 29, 2003||Jul 8, 2008||Broadcom Corporation||Efficient implementation of a filter|
|US20050038842 *||Feb 4, 2004||Feb 17, 2005||Stoye Robert William||Processor for FIR filtering|
|U.S. Classification||708/490, 712/E09.017|
|International Classification||G06F9/302, G06F7/00, G06F9/38, G06F9/30, G06F13/38|
|Jan 27, 1992||AS||Assignment|
Owner name: OKI ELECTRIC INDUSTRY CO., LTD.
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:KOMOTO, EIJI;MAKI, KAZUHIKO;REEL/FRAME:006001/0412
Effective date: 19920110
|Sep 22, 1997||FPAY||Fee payment|
Year of fee payment: 4
|Sep 26, 2001||FPAY||Fee payment|
Year of fee payment: 8
|Sep 30, 2005||FPAY||Fee payment|
Year of fee payment: 12
|Feb 4, 2009||AS||Assignment|
Owner name: OKI SEMICONDUCTOR CO., LTD., JAPAN
Free format text: CHANGE OF NAME;ASSIGNOR:OKI ELECTRIC INDUSTRY CO., LTD.;REEL/FRAME:022240/0984
Effective date: 20081001