US5361185A - Distributed VCC/VSS ESD clamp structure - Google Patents

Distributed VCC/VSS ESD clamp structure Download PDF

Info

Publication number
US5361185A
US5361185A US08/019,937 US1993793A US5361185A US 5361185 A US5361185 A US 5361185A US 1993793 A US1993793 A US 1993793A US 5361185 A US5361185 A US 5361185A
Authority
US
United States
Prior art keywords
power supply
vcc
supply bus
esd protection
vss
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US08/019,937
Inventor
James Yu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Priority to US08/019,937 priority Critical patent/US5361185A/en
Assigned to ADVANCED MICRO DEVICES, INC. reassignment ADVANCED MICRO DEVICES, INC. ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: YU, JAMES
Application granted granted Critical
Publication of US5361185A publication Critical patent/US5361185A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02HEMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/02Details
    • H02H3/05Details with means for increasing reliability, e.g. redundancy arrangements

Definitions

  • This invention relates generally to semiconductor protection circuitry and more particularly, it relates to a distributed VCC/VSS ESD clamp structure for producing a local and immediate, indirect discharging path so as to prevent inadvertent damage caused by an electrostatic discharge (ESD) or electrical overstress (EOS) event occurring between any two of the external pins of an integrated circuit package when the direct clamp discharging paths are not forming a complete path.
  • ESD electrostatic discharge
  • EOS electrical overstress
  • VCC/VSS clamp structure which is local to every ESD protection circuitry associated with each of the input and output pins of the integrated circuit package and which is distributed with respect to the bonding pads thereof. This is achieved in the present invention by the provision of local, distributed VCC/VSS clamp structures connected to each ESD structure associated with the input and output pins so as to produce a secondary discharging path in the event that the primary discharging path (through the ESD structure) is incomplete.
  • the present invention is concerned with the provision of a distributed VCC/VSS clamp structure for preventing inadvertent damage to semiconductor integrated circuits caused by an electrostatic discharge event occurring between any two external pins thereof which includes a VCC power supply bus, a VSS power supply bus, and a clamp transistor.
  • the clamp transistor is disposed locally to every ESD protection circuitry associated with each input and output pin of the semiconductor integrated circuit.
  • the clamp transistor is formed of an N-channel MOS transistor having its drain connected to the VCC power supply bus, its source connected to the VSS power supply bus, and its gate connected to a first internal node coupled to the ESD protection circuitry.
  • the clamp transistor is activated only when the ESD protection circuitry is unable to supply a primary discharging path in order to produce a secondary discharging path from a zapped pin through its source-drain conduction path to a grounded pin, thereby protecting the internal circuits of the semiconductor integrated circuit.
  • FIG. 1 is an equivalent circuit diagram of a local, distributed VCC/VSS clamp structure, constructed in accordance with the principles of the present invention
  • FIG. 2 is a top plan layout representation of the clamp structure of FIG. 1;
  • FIG. 3 is a cross-sectional view of the VCC/VSS clamp structure which implements the circuit of FIG. 1 when the pad 14 is functioning as an output pad and an excessive positive voltage is applied thereto;
  • FIG. 4 is a cross-sectional view of the VCC/VSS clamp structure which implements the circuit of FIG. 1 when the pad 14 is functioning as an input or output pad and an excessive negative voltage is applied thereto.
  • FIG. 1 an equivalent schematic circuit diagram of a local, distributed VCC/VSS clamp structure 10, constructed in accordance with the principles of the present invention.
  • the clamp structure 10 provides a local and immediate, indirect discharging path so as to prevent inadvertent damage caused by an electrostatic discharge (ESD) or electrical overstress (EOS) event occurring between any two of the external pins of an semiconductor integrated circuit package (not shown), when the direct clamp discharging paths are not forming a complete path.
  • ESD electrostatic discharge
  • EOS electrical overstress
  • the clamp structure 10 is connected in parallel to every ESD structure 12 associated with the input and/or output pad 14. It should be understood that the pad 14 is connected to the external pins of the integrated circuit by a bonding wire (also not shown).
  • a top plan layout representation of the clamp structure of FIG. 1 is illustrated in FIG. 2.
  • the input or output pad 14 is coupled to an internal circuit 16 to be protected via an internal node A.
  • the ESD structure 12 for example, includes a first N-channel MOS transistor Q1 and a second N-channel MOS transistor Q2.
  • the transistor Q1 has its drain connected to a VCC power supply bus 18 and its source connected to the internal node A.
  • the transistor Q2 has its drain also connected to the internal node A and its source connected to a VSS power supply bus 20.
  • the gates of the transistors Q1 and Q2 are connected together and to another internal node B.
  • the sizes of the transistors Q1 and Q2 is given by the relationship between the channel width W1 and the channel length L1, where W1 has a dimension between 170-340 microns and L1 has a dimension of approximately 1.6 microns.
  • the ESD structure 12 further includes a third N-channel MOS transistor Q3 having its drain connected to the internal node B and to the gates of the first and second MOS transistors Q1 and Q2.
  • the third transistor Q3 has its source connected to the VSS power supply bus 20 and its gate connected to the VCC power supply bus 18.
  • the channel width W3 of the transistor Q3 has a dimension of 20 microns, and the channel length L3 thereof has a dimension of approximately 2.0 microns.
  • a diffusion-type resistor R N-W is connected in series between the input/output pad 14 and the internal node A, which is connected to the internal circuit of the integrated circuit for limiting and absorbing the peak discharging current (energy).
  • the local, distributed VCC/VSS clamp structure 10 of the present invention is comprised of a fourth N-channel MOS transistor Q4.
  • the transistor Q4 has its drain connected to the VCC power supply bus 18 and its source connected to the VSS power supply bus 20.
  • the gate of the transistor Q4 is connected to the gates of the transistors Q1 and Q2 at the internal node B.
  • the channel width W1 of the transistor Q4 is the same range as the transistors Q1 and Q2, but the channel length L2 has a dimension of approximately 1.0 microns. This channel length L2 is maintained to be at the minimal value of technology so as to provide an earlier response time due to a lower breakdown voltage.
  • FIG. 3 there is shown a cross-sectional view of the VCC/VSS clamp structure which implements the circuit of FIG. 1 when the pad is functioning as an output pad and an excessive positive voltage is applied thereto.
  • the pad 14 When the pad 14 is used as the output pad, there is typically a P-channel pull-up output transistor P1 associated with it.
  • the transistor P1 is formed by an N-well region 22 diffused in a p- substrate 24.
  • a first p+ contact diffusion 26 is formed in the N-well region 22 and defines the source of the transistor P1.
  • a second p+ contact diffusion 28 is also formed in the N-well region 22 and defines the drain of the transistor P1.
  • a thin oxide 30 is used for the gate insulation and is disposed over the N-well region 22 between the p+ diffusions 26 and 28.
  • a polysilicon layer 32 is disposed on top of the thin oxide 30 to form the gate of the transistor P1 which is connected to the internal circuit.
  • the source region 26 is coupled to the VCC power supply bus 18, and the drain region 28 is coupled to the output pad 14. It will be noted that a N+ contact diffusion 34 is also formed in the N-well region 22, which is coupled to the VCC power supply bus 18.
  • the VCC/VSS clamp transistor Q4 is formed in the p-substrate 24.
  • a first N+ contact diffusion 36 is formed in the substrate 24 and defines the drain of the transistor Q4.
  • a second N+ contact diffusion 38 is formed in the substrate 24 and defines the source of the transistor Q4.
  • a thin oxide 40 is used for the gate insulation and is disposed over the substrate 24 between the N+ contact diffusions 36 and 38.
  • a polysilicon layer 42 is disposed on top of the thin oxide 40 to form the gate of the clamp transistor Q4 which is connected to the internal node B.
  • the drain region 36 is coupled to the VCC power supply bus 18, and the source region 38 is coupled to the VSS power supply bus 20.
  • the diode formed by the p+ diffusion 28 and the N+ diffusion 34 will become forward biased so as to raise the VCC power supply bus 18 to a more positive potential.
  • the VCC power supply bus potential will follow the rise on the output node 14 by one diode drop (i.e., 0.6 volts). Thus, if the output node 14 rises to +15 volts, the VCC power supply bus potential will be at +14.4 volts. This causes an overstress condition to exist between the VCC power supply bus 18 and the VSS power supply bus 20.
  • the transistor Q2 in the ESD structure does not react quickly enough due to a longer channel length to provide a discharging path, the internal circuit 16 may be damaged or destroyed but for the clamping transistor Q4.
  • the transistor Q4 of the present invention it can be seen that it will be turned on quickly so as to create a secondary discharging path from the N+ diffusion 36, through the p- substrate 24, N+ diffusion 38, and the VSS power supply bus 20.
  • FIG. 4 there is shown a cross-sectional view of the VCC/VSS clamp structure which implements the circuit of FIG. 1 when the pad 14 is functioning either as an input or output pad and an excessive negative voltage is applied thereto.
  • the transistors Q1 and Q2 are formed in the p-substrate 24.
  • the VCC/VSS clamp transistor Q4 is formed in the p- substrate 24 as previously discussed in FIG. 3.
  • the N+ diffusion 36 forming the drain of the transistor Q4 is a shared region and also forms the drain of the transistor Q1.
  • a N+ diffusion 44 is formed in the p- substrate 24 and defines the source of the transistor Q1.
  • a thin oxide 46 is used for the gate insulation and is disposed over the p- substrate 24 between the N+ diffusions 36 and 44.
  • a polysilicon layer 48 is disposed on top of the thin oxide 46 to form the gate of the transistor Q1, which is connected to the internal node B.
  • the N+ diffusion 44 is also a shared region and thus forms the drain of the transistor Q2.
  • a N+ diffusion 50 is formed in the p- substrate 24 and forms the source of the transistor Q2.
  • a thin oxide 52 is used for the gate insulation and is disposed over the p- substrate 24 between the N+ diffusions 44 and 50. It will be noted that a p+ diffusion 56 is also formed in the p- substrate 24, which is coupled to the VSS power supply bus 20.
  • the diode formed by the p+ diffusion 56 and the N+ diffusion 50 will become forward biased so as to lower the VSS power supply bus 20 to a more negative potential.
  • the VSS power supply bus potential will follow the drop on the output node 14 by one diode drop, (i.e., 0.6 volts). Thus, if the output node drops to -15 volts, the VSS power supply bus potential will be at -14.4 volts. This causes an overstress condition to exist between the VCC power supply bus 18 and the VSS power supply bus 20.
  • the transistor Q1 in the ESD structure does not react quick enough due to a longer channel length to provide a discharging path, the internal circuit 16 may be damaged or destroyed but for the clamp transistor Q4. With the provision of the transistor Q4, it will be noted again that it turns on quickly so as to create a secondary discharging path from the VSS power supply bus, N+ diffusion 38, through the p-substrate 24, N+ diffusion 36, and the VCC power supply bus.
  • the primary discharging path is provided by direct clamps in the ESD structure 12.
  • the localized VCC/VSS clamps are used to provide a secondary discharging path in the event that the direct clamps do not function properly to form a complete path.
  • the localized VCC/VSS clamp structures are designed to provide a back-up protection since they are placed close to the ESD event and thus will respond faster than the remote prior art power supply clamps.
  • the localized VCC/VSS clamps are formed of minimum geometry rather than the robust layout (not minimal dimensions) of the ESD structures.
  • the present invention provides a distributed VCC/VSS clamp structure for producing a local and immediate, indirect discharging path so as to prevent inadvertent damage caused by electrostatic discharge which includes a clamp transistor.
  • the clamp transistor is disposed locally to every ESD protection circuitry associated with each input and output pin of the semiconductor integrated circuit.

Abstract

A distributed VCC/VSS clamp structure (10) for preventing inadvertent damage to semiconductor integrated circuits caused by an electrostatic discharging event occurring between any two external pins thereof includes a clamp transistor (Q4) which is disposed locally to every ESD protection circuitry associated with each input and output pin of a semiconductor integrated circuit. The clamp transistor is activated so as to provide a secondary discharging path when the direct clamp discharging paths of the ESD protection circuitry are not forming a complete path.

Description

BACKGROUND OF THE INVENTION
This invention relates generally to semiconductor protection circuitry and more particularly, it relates to a distributed VCC/VSS ESD clamp structure for producing a local and immediate, indirect discharging path so as to prevent inadvertent damage caused by an electrostatic discharge (ESD) or electrical overstress (EOS) event occurring between any two of the external pins of an integrated circuit package when the direct clamp discharging paths are not forming a complete path.
It is generally well-known in the prior art that the magnitude of an electric voltage allowed to be applied to an integrated circuit package is rather limited since the physical size of the integrated circuit package is fairly small and the internal circuitry thereof are tightly packed together with minimum geometries for the merit of performance and integration. When the integrated circuit package is not being used, for example, in storage or handling, the external leads or pins thereof are susceptible to being exposed to a static charge thereon. Such static discharges can be of a catastrophic nature with sufficient energy to cause melting, short circuiting, physical damage, or even destruction of the semiconductor element or chip mounted within the integrated circuit package.
In order to protect the semiconductor chip in the integrated circuit package from being destroyed when such static discharges occur, there has been provided in the prior art ESD protection circuitry which have taken the form of a small diode, a Zener diode, or a transistor connected between either an input pin or an output pin and VCC and VSS power supply pins. These protection circuits break down when the semiconductor chip encounters an unexpectedly high voltage so as to protect the semiconductor chip and to thereby prevent its destruction. However, these prior art protection devices suffer from the drawback that they only offer protection either between the input or output pin and a power supply pin. Thus, in such protection devices, the charges accumulated on either the input pins or the output pins were discharged only when the power supply pin was made to come in contact with the ground potential. Accordingly, the prior art protection devices offer no protection when another input pin or output pin was the one being referenced to ground. Also, no immediate discharge path was provided when the charges were accumulated on a floating power supply pin through an input or output pin.
There has also been provided heretofore power supply clamps, such as VCC/VSS clamp structures, in an attempt to overcome problems associated with the prior art ESD protection circuitry. However, these prior art power supply clamps, either single or multiple, were usually a separate structure that were located at a different part of the semiconductor chip or die, i.e., top, bottom or side peripheral portions thereof. Accordingly, upon the occurrence of an ESD or EOS event, the time constant between the pin on which electrostatic charges are applied (zapped pin) and the power supply clamp may prevent the desired early or timingly discharging through the remote VCC/VSS clamp structure, thereby resulting in an ESD failure.
It would therefore be desirable to provide a VCC/VSS clamp structure which is local to every ESD protection circuitry associated with each of the input and output pins of the integrated circuit package and which is distributed with respect to the bonding pads thereof. This is achieved in the present invention by the provision of local, distributed VCC/VSS clamp structures connected to each ESD structure associated with the input and output pins so as to produce a secondary discharging path in the event that the primary discharging path (through the ESD structure) is incomplete.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a distributed VCC/VSS clamp structure for producing a local and immediate, indirect discharging path so as to prevent inadvertent damage caused by an ESD or EOS event which is relatively simple and economical to manufacture and assembly, but yet overcomes the disadvantages of the prior art ESD protection circuitry.
It is an object of the present invention to provide a distributed VCC/VSS clamp structure for producing a local and immediate, indirect discharging path so as to prevent inadvertent damage caused by an electrostatic discharge or electrical overstress event occurring between any two of the external pins of an integrated circuit package when the direct clamp discharging paths are not forming a complete path.
It is another object of the present invention to provide a distributed VCC/VSS clamp structure which includes a clamp transistor being disposed locally to every ESD protection circuitry associated with each input and output pin of the semiconductor integrated circuit.
In accordance with these aims and objectives, the present invention is concerned with the provision of a distributed VCC/VSS clamp structure for preventing inadvertent damage to semiconductor integrated circuits caused by an electrostatic discharge event occurring between any two external pins thereof which includes a VCC power supply bus, a VSS power supply bus, and a clamp transistor. The clamp transistor is disposed locally to every ESD protection circuitry associated with each input and output pin of the semiconductor integrated circuit.
The clamp transistor is formed of an N-channel MOS transistor having its drain connected to the VCC power supply bus, its source connected to the VSS power supply bus, and its gate connected to a first internal node coupled to the ESD protection circuitry. The clamp transistor is activated only when the ESD protection circuitry is unable to supply a primary discharging path in order to produce a secondary discharging path from a zapped pin through its source-drain conduction path to a grounded pin, thereby protecting the internal circuits of the semiconductor integrated circuit.
BRIEF DESCRIPTION OF THE DRAWINGS
These and other objects and advantages of the present invention will become more fully apparent from the following detailed description when read in conjunction with the accompanying drawings with like reference numerals indicating corresponding parts throughout, wherein:
FIG. 1 is an equivalent circuit diagram of a local, distributed VCC/VSS clamp structure, constructed in accordance with the principles of the present invention;
FIG. 2 is a top plan layout representation of the clamp structure of FIG. 1;
FIG. 3 is a cross-sectional view of the VCC/VSS clamp structure which implements the circuit of FIG. 1 when the pad 14 is functioning as an output pad and an excessive positive voltage is applied thereto; and
FIG. 4 is a cross-sectional view of the VCC/VSS clamp structure which implements the circuit of FIG. 1 when the pad 14 is functioning as an input or output pad and an excessive negative voltage is applied thereto.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring now in detail to the drawings, there is shown in FIG. 1 an equivalent schematic circuit diagram of a local, distributed VCC/VSS clamp structure 10, constructed in accordance with the principles of the present invention. The clamp structure 10 provides a local and immediate, indirect discharging path so as to prevent inadvertent damage caused by an electrostatic discharge (ESD) or electrical overstress (EOS) event occurring between any two of the external pins of an semiconductor integrated circuit package (not shown), when the direct clamp discharging paths are not forming a complete path. In order to prevent the semiconductor integrated circuit package from being damaged or destroyed, the clamp structure 10 is connected in parallel to every ESD structure 12 associated with the input and/or output pad 14. It should be understood that the pad 14 is connected to the external pins of the integrated circuit by a bonding wire (also not shown). A top plan layout representation of the clamp structure of FIG. 1 is illustrated in FIG. 2.
The input or output pad 14 is coupled to an internal circuit 16 to be protected via an internal node A. The ESD structure 12, for example, includes a first N-channel MOS transistor Q1 and a second N-channel MOS transistor Q2. The transistor Q1 has its drain connected to a VCC power supply bus 18 and its source connected to the internal node A. The transistor Q2 has its drain also connected to the internal node A and its source connected to a VSS power supply bus 20. The gates of the transistors Q1 and Q2 are connected together and to another internal node B. The sizes of the transistors Q1 and Q2 is given by the relationship between the channel width W1 and the channel length L1, where W1 has a dimension between 170-340 microns and L1 has a dimension of approximately 1.6 microns.
The ESD structure 12 further includes a third N-channel MOS transistor Q3 having its drain connected to the internal node B and to the gates of the first and second MOS transistors Q1 and Q2. The third transistor Q3 has its source connected to the VSS power supply bus 20 and its gate connected to the VCC power supply bus 18. The channel width W3 of the transistor Q3 has a dimension of 20 microns, and the channel length L3 thereof has a dimension of approximately 2.0 microns. A diffusion-type resistor RN-W is connected in series between the input/output pad 14 and the internal node A, which is connected to the internal circuit of the integrated circuit for limiting and absorbing the peak discharging current (energy). The ESD structure described thus far is quite conventional and does not form a part of the present invention.
The local, distributed VCC/VSS clamp structure 10 of the present invention is comprised of a fourth N-channel MOS transistor Q4. The transistor Q4 has its drain connected to the VCC power supply bus 18 and its source connected to the VSS power supply bus 20. The gate of the transistor Q4 is connected to the gates of the transistors Q1 and Q2 at the internal node B. The channel width W1 of the transistor Q4 is the same range as the transistors Q1 and Q2, but the channel length L2 has a dimension of approximately 1.0 microns. This channel length L2 is maintained to be at the minimal value of technology so as to provide an earlier response time due to a lower breakdown voltage.
In order to explain the operation of the local, distributed clamp structure 10, it is needed to illustrate initially how the overstress is created between the VCC power supply bus 18 and the VSS power supply bus 20. In a first case, it will be assumed that the pin zapped is connected to the pad 14 functioning as the output pin and the pin grounded is either the VSS power supply pin or all of the input and output pins tied together.
In FIG. 3, there is shown a cross-sectional view of the VCC/VSS clamp structure which implements the circuit of FIG. 1 when the pad is functioning as an output pad and an excessive positive voltage is applied thereto. When the pad 14 is used as the output pad, there is typically a P-channel pull-up output transistor P1 associated with it. The transistor P1 is formed by an N-well region 22 diffused in a p- substrate 24. A first p+ contact diffusion 26 is formed in the N-well region 22 and defines the source of the transistor P1. A second p+ contact diffusion 28 is also formed in the N-well region 22 and defines the drain of the transistor P1. A thin oxide 30 is used for the gate insulation and is disposed over the N-well region 22 between the p+ diffusions 26 and 28. A polysilicon layer 32 is disposed on top of the thin oxide 30 to form the gate of the transistor P1 which is connected to the internal circuit. The source region 26 is coupled to the VCC power supply bus 18, and the drain region 28 is coupled to the output pad 14. It will be noted that a N+ contact diffusion 34 is also formed in the N-well region 22, which is coupled to the VCC power supply bus 18.
The VCC/VSS clamp transistor Q4 is formed in the p-substrate 24. A first N+ contact diffusion 36 is formed in the substrate 24 and defines the drain of the transistor Q4. A second N+ contact diffusion 38 is formed in the substrate 24 and defines the source of the transistor Q4. A thin oxide 40 is used for the gate insulation and is disposed over the substrate 24 between the N+ contact diffusions 36 and 38. A polysilicon layer 42 is disposed on top of the thin oxide 40 to form the gate of the clamp transistor Q4 which is connected to the internal node B. The drain region 36 is coupled to the VCC power supply bus 18, and the source region 38 is coupled to the VSS power supply bus 20.
When an excessive positive voltage appears at the output pad 14, the diode formed by the p+ diffusion 28 and the N+ diffusion 34 will become forward biased so as to raise the VCC power supply bus 18 to a more positive potential. The VCC power supply bus potential will follow the rise on the output node 14 by one diode drop (i.e., 0.6 volts). Thus, if the output node 14 rises to +15 volts, the VCC power supply bus potential will be at +14.4 volts. This causes an overstress condition to exist between the VCC power supply bus 18 and the VSS power supply bus 20. If the transistor Q2 in the ESD structure does not react quickly enough due to a longer channel length to provide a discharging path, the internal circuit 16 may be damaged or destroyed but for the clamping transistor Q4. With the provision of the transistor Q4 of the present invention, it can be seen that it will be turned on quickly so as to create a secondary discharging path from the N+ diffusion 36, through the p- substrate 24, N+ diffusion 38, and the VSS power supply bus 20.
In a second case, it will be assumed that the pin zapped is connected to the pad 14 functioning either as an output or input pad and the pin grounded is either the VCC power supply pin or all of the input and output pins tied together. In FIG. 4, there is shown a cross-sectional view of the VCC/VSS clamp structure which implements the circuit of FIG. 1 when the pad 14 is functioning either as an input or output pad and an excessive negative voltage is applied thereto.
The transistors Q1 and Q2 are formed in the p-substrate 24. The VCC/VSS clamp transistor Q4 is formed in the p- substrate 24 as previously discussed in FIG. 3. The N+ diffusion 36 forming the drain of the transistor Q4 is a shared region and also forms the drain of the transistor Q1. A N+ diffusion 44 is formed in the p- substrate 24 and defines the source of the transistor Q1. A thin oxide 46 is used for the gate insulation and is disposed over the p- substrate 24 between the N+ diffusions 36 and 44. A polysilicon layer 48 is disposed on top of the thin oxide 46 to form the gate of the transistor Q1, which is connected to the internal node B. The N+ diffusion 44 is also a shared region and thus forms the drain of the transistor Q2. A N+ diffusion 50 is formed in the p- substrate 24 and forms the source of the transistor Q2. A thin oxide 52 is used for the gate insulation and is disposed over the p- substrate 24 between the N+ diffusions 44 and 50. It will be noted that a p+ diffusion 56 is also formed in the p- substrate 24, which is coupled to the VSS power supply bus 20.
When an excessive negative voltage appears at the input/output pad 14, the diode formed by the p+ diffusion 56 and the N+ diffusion 50 will become forward biased so as to lower the VSS power supply bus 20 to a more negative potential. The VSS power supply bus potential will follow the drop on the output node 14 by one diode drop, (i.e., 0.6 volts). Thus, if the output node drops to -15 volts, the VSS power supply bus potential will be at -14.4 volts. This causes an overstress condition to exist between the VCC power supply bus 18 and the VSS power supply bus 20. If the transistor Q1 in the ESD structure does not react quick enough due to a longer channel length to provide a discharging path, the internal circuit 16 may be damaged or destroyed but for the clamp transistor Q4. With the provision of the transistor Q4, it will be noted again that it turns on quickly so as to create a secondary discharging path from the VSS power supply bus, N+ diffusion 38, through the p-substrate 24, N+ diffusion 36, and the VCC power supply bus.
As can be seen from the operation thus described, the primary discharging path is provided by direct clamps in the ESD structure 12. The localized VCC/VSS clamps are used to provide a secondary discharging path in the event that the direct clamps do not function properly to form a complete path. As a result, it will be understood that the localized VCC/VSS clamp structures are designed to provide a back-up protection since they are placed close to the ESD event and thus will respond faster than the remote prior art power supply clamps. Further, the localized VCC/VSS clamps are formed of minimum geometry rather than the robust layout (not minimal dimensions) of the ESD structures.
From the foregoing detailed description, it can thus be seen that the present invention provides a distributed VCC/VSS clamp structure for producing a local and immediate, indirect discharging path so as to prevent inadvertent damage caused by electrostatic discharge which includes a clamp transistor. The clamp transistor is disposed locally to every ESD protection circuitry associated with each input and output pin of the semiconductor integrated circuit.
While there has been illustrated and described what is at present considered to be a preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made, and equivalents may be substituted for elements thereof without departing from the true scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the central scope thereof. Therefore, it is intended that this invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out the invention, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims (3)

What is claimed is:
1. A distributed VCC/VSS clamp structure for preventing inadvertent damage to internal circuits of semiconductor integrated circuit packages caused by an electrostatic discharge event occurring between any two external pins thereof, said external pins being formed of either an input pin, an output pin, a VCC power supply pin, or a VSS power supply pin, comprising:
a VCC power supply bus (18);
a VSS power supply bus (20);
a plurality of ESD protection circuitry interconnected between said VCC power supply bus and said VSS power supply bus, each one of said plurality of ESD protection circuitry being operatively connected to a corresponding one of external pins of the semiconductor integrated circuit so as to provide primary discharging paths when an electrostatic discharge is applied to one of the external pins defining a zapped pin and another remaining one of the external pins is referenced to ground;
a plurality of clamp transistors (Q4) each being connected in parallel to and disposed in close proximity to a corresponding one of said plurality of ESD protection circuitry associated with each input and output pin of the semiconductor integrated circuit;
each of said plurality of clamp transistors being formed of an N-channel MOS transistor, said N-channel MOS transistor having its drain connected to the VCC power supply bus, its source connected to the VSS power supply bus, and its gate connected to a first internal node coupled to the corresponding one of said plurality of ESD protection circuitry;
each of said plurality of ESD protection circuitry including a first N-channel MOS transistor (Q1) having its drain connected to the VCC power supply bus, its source connected to a second internal node to which the internal circuit to be protected is connected, and its gate connected to the first internal node;
each of said plurality of ESD protection circuitry further including a second N-channel MOS transistor (Q2) having its drain connected to the second internal node, its source connected to the VSS power supply bus, and its gate connected to the first internal node; and
each of said plurality of clamp transistors being activated only when the corresponding one of said plurality of ESD protection circuitry is unable to supply the primary discharging path in order to produce a secondary discharging path from the zapped pin through its source/drain conduction path to the external pin referenced to ground, thereby protecting the internal circuits of the semiconductor integrated circuit.
2. A clamp structure as claimed in claim 1, wherein each of said plurality of clamp transistors is formed of a minimum channel length so as to insure a relatively short response time due to a lower breakdown voltage.
3. A clamp structure as claimed in claim 1, wherein each of said plurality of clamp transistors is formed of dimensions relatively smaller than that of the ESD protection circuitry to facilitate its operation.
US08/019,937 1993-02-19 1993-02-19 Distributed VCC/VSS ESD clamp structure Expired - Lifetime US5361185A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US08/019,937 US5361185A (en) 1993-02-19 1993-02-19 Distributed VCC/VSS ESD clamp structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/019,937 US5361185A (en) 1993-02-19 1993-02-19 Distributed VCC/VSS ESD clamp structure

Publications (1)

Publication Number Publication Date
US5361185A true US5361185A (en) 1994-11-01

Family

ID=21795873

Family Applications (1)

Application Number Title Priority Date Filing Date
US08/019,937 Expired - Lifetime US5361185A (en) 1993-02-19 1993-02-19 Distributed VCC/VSS ESD clamp structure

Country Status (1)

Country Link
US (1) US5361185A (en)

Cited By (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2295049A (en) * 1994-11-08 1996-05-15 Hyundai Electronics Ind Overvoltage protection for integrated circuits
US5548135A (en) * 1995-05-12 1996-08-20 David Sarnoff Research Center, Inc. Electrostatic discharge protection for an array of macro cells
US5596474A (en) * 1994-09-28 1997-01-21 Nittetsu Semiconductor Co., Ltd. Power protection circuitry for a semiconductor integrated circuit
US5638296A (en) * 1994-04-11 1997-06-10 Abb Power T&D Company Inc. Intelligent circuit breaker providing synchronous switching and condition monitoring
US5841619A (en) * 1994-12-06 1998-11-24 Kabushiki Kaisha Toshiba Interface circuit for use in a semiconductor integrated circuit
US5923202A (en) * 1997-03-03 1999-07-13 National Semiconductor Corporation Input/output overvoltage containment circuit for improved latchup protection
US6069782A (en) * 1998-08-26 2000-05-30 Integrated Device Technology, Inc. ESD damage protection using a clamp circuit
WO2001020678A1 (en) * 1999-09-16 2001-03-22 Infineon Technologies Ag Esd-protective arrangement for signal inputs and outputs in semiconductor devices with substrate separation
US6301177B1 (en) * 1997-11-25 2001-10-09 Samsung Electronics Co., Ltd. Internal power supply voltage generating circuit and the method for controlling thereof
US6351364B1 (en) * 2000-03-17 2002-02-26 United Microelectronics Corp. Electrostatic discharge protection circuit
US6385021B1 (en) 2000-04-10 2002-05-07 Motorola, Inc. Electrostatic discharge (ESD) protection circuit
US20020105512A1 (en) * 2000-12-06 2002-08-08 Samsung Electronics Co., Ltd. Liquid crystal device driver circuit for electrostatic discharge protection
US20020195663A1 (en) * 2001-06-26 2002-12-26 Ramsbey Mark T. ESD implant following spacer deposition
FR2831328A1 (en) * 2001-10-23 2003-04-25 St Microelectronics Sa Integrated circuit has metal oxide semiconductor transistors which are integrated in supply rail and below supply conductors, to short-circuit conductors for protection against electrostatic discharge and overvoltage
US20040027742A1 (en) * 2002-08-09 2004-02-12 Miller James W. Electrostatic discharge protection circuitry and method of operation
US20040041168A1 (en) * 2002-08-29 2004-03-04 Hembree David R Test insert with electrostatic discharge structures and associated methods
US20040141267A1 (en) * 2003-01-22 2004-07-22 Khazhinsky Michael G. Electrostatic discharge circuit and method therefor
US20040141268A1 (en) * 2003-01-22 2004-07-22 Miller James W. Electrostatic discharge circuit and method therefor
US20050063111A1 (en) * 2003-09-24 2005-03-24 Broadcom Corporation System and method to relieve ESD requirements of NMOS transistors
US20050083620A1 (en) * 2003-10-15 2005-04-21 Yung-Hao Lin Esd protection circuit with a stack-coupling device
US6927956B1 (en) * 1999-07-28 2005-08-09 Rohm Co., Ltd. Semiconductor integrated circuit device with enhanced resistance to electrostatic breakdown
US20060181823A1 (en) * 2005-02-11 2006-08-17 Miller James W I/O cell ESD system
US20060262469A1 (en) * 2005-05-17 2006-11-23 Freescale Semiconductor, Inc. Integrated circuit with multiple independent gate field effect transistor (MIGFET) rail clamp circuit
US20070097581A1 (en) * 2005-11-01 2007-05-03 Freescale Semiconductor, Inc. Electrostatic discharge (ESD) protection circuit for multiple power domain integrated circuit
US20070267755A1 (en) * 2006-05-16 2007-11-22 Vo Nhat D Integrated circuit having pads and input/output (i/o) cells
US20080062596A1 (en) * 2006-08-31 2008-03-13 Freescale Semiconductor, Inc. Distributed electrostatic discharge protection circuit with varying clamp size
US20090174973A1 (en) * 2008-01-09 2009-07-09 Khazhinsky Michael G Migfet circuit with esd protection
US7777998B2 (en) 2007-09-10 2010-08-17 Freescale Semiconductor, Inc. Electrostatic discharge circuit and method therefor
US7943958B1 (en) * 2001-08-30 2011-05-17 National Semiconductor Corporation High holding voltage LVTSCR-like structure
CN112332392A (en) * 2019-08-05 2021-02-05 珠海格力电器股份有限公司 Protection circuit and integrated circuit chip

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4730129A (en) * 1984-02-29 1988-03-08 Fujitsu Limited Integrated circuit having fuse circuit
US5237395A (en) * 1991-05-28 1993-08-17 Western Digital Corporation Power rail ESD protection circuit
US5255146A (en) * 1991-08-29 1993-10-19 National Semiconductor Corporation Electrostatic discharge detection and clamp control circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4730129A (en) * 1984-02-29 1988-03-08 Fujitsu Limited Integrated circuit having fuse circuit
US5237395A (en) * 1991-05-28 1993-08-17 Western Digital Corporation Power rail ESD protection circuit
US5255146A (en) * 1991-08-29 1993-10-19 National Semiconductor Corporation Electrostatic discharge detection and clamp control circuit

Cited By (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5638296A (en) * 1994-04-11 1997-06-10 Abb Power T&D Company Inc. Intelligent circuit breaker providing synchronous switching and condition monitoring
US5596474A (en) * 1994-09-28 1997-01-21 Nittetsu Semiconductor Co., Ltd. Power protection circuitry for a semiconductor integrated circuit
GB2295049A (en) * 1994-11-08 1996-05-15 Hyundai Electronics Ind Overvoltage protection for integrated circuits
GB2295049B (en) * 1994-11-08 1998-11-11 Hyundai Electronics Ind Semiconductor cut-off device and method of manufacture
US5841619A (en) * 1994-12-06 1998-11-24 Kabushiki Kaisha Toshiba Interface circuit for use in a semiconductor integrated circuit
US5548135A (en) * 1995-05-12 1996-08-20 David Sarnoff Research Center, Inc. Electrostatic discharge protection for an array of macro cells
WO1996036988A2 (en) * 1995-05-12 1996-11-21 David Sarnoff Research Center, Inc. Electrostatic discharge protection for an array of macro cells
WO1996036988A3 (en) * 1995-05-12 1997-01-16 Sarnoff David Res Center Electrostatic discharge protection for an array of macro cells
US5923202A (en) * 1997-03-03 1999-07-13 National Semiconductor Corporation Input/output overvoltage containment circuit for improved latchup protection
DE19738181C2 (en) * 1997-03-03 2003-04-10 Nat Semiconductor Corp Protection circuit for integrated circuits
US6301177B1 (en) * 1997-11-25 2001-10-09 Samsung Electronics Co., Ltd. Internal power supply voltage generating circuit and the method for controlling thereof
US6069782A (en) * 1998-08-26 2000-05-30 Integrated Device Technology, Inc. ESD damage protection using a clamp circuit
US6927956B1 (en) * 1999-07-28 2005-08-09 Rohm Co., Ltd. Semiconductor integrated circuit device with enhanced resistance to electrostatic breakdown
WO2001020678A1 (en) * 1999-09-16 2001-03-22 Infineon Technologies Ag Esd-protective arrangement for signal inputs and outputs in semiconductor devices with substrate separation
US6590263B2 (en) 1999-09-16 2003-07-08 Infineon Technologies Ag ESD protection configuration for signal inputs and outputs in semiconductor devices with substrate isolation
US6351364B1 (en) * 2000-03-17 2002-02-26 United Microelectronics Corp. Electrostatic discharge protection circuit
US6385021B1 (en) 2000-04-10 2002-05-07 Motorola, Inc. Electrostatic discharge (ESD) protection circuit
US20020105512A1 (en) * 2000-12-06 2002-08-08 Samsung Electronics Co., Ltd. Liquid crystal device driver circuit for electrostatic discharge protection
US6753836B2 (en) * 2000-12-06 2004-06-22 Samsung Electronics Co., Ltd. Liquid crystal device driver circuit for electrostatic discharge protection
US6900085B2 (en) 2001-06-26 2005-05-31 Advanced Micro Devices, Inc. ESD implant following spacer deposition
US20020195663A1 (en) * 2001-06-26 2002-12-26 Ramsbey Mark T. ESD implant following spacer deposition
US7943958B1 (en) * 2001-08-30 2011-05-17 National Semiconductor Corporation High holding voltage LVTSCR-like structure
US6818953B2 (en) 2001-10-23 2004-11-16 Stmicroelectronics S.A. Protection of an integrated circuit against electrostatic discharges and other overvoltages
EP1309005A1 (en) * 2001-10-23 2003-05-07 STMicroelectronics S.A. Protection of an integrated circuit against ESD and other overvoltages
FR2831328A1 (en) * 2001-10-23 2003-04-25 St Microelectronics Sa Integrated circuit has metal oxide semiconductor transistors which are integrated in supply rail and below supply conductors, to short-circuit conductors for protection against electrostatic discharge and overvoltage
US6724603B2 (en) 2002-08-09 2004-04-20 Motorola, Inc. Electrostatic discharge protection circuitry and method of operation
US20040027742A1 (en) * 2002-08-09 2004-02-12 Miller James W. Electrostatic discharge protection circuitry and method of operation
US20040041168A1 (en) * 2002-08-29 2004-03-04 Hembree David R Test insert with electrostatic discharge structures and associated methods
US7709279B2 (en) 2002-08-29 2010-05-04 Micron Technology, Inc. Methods for testing semiconductor devices methods for protecting the same from electrostatic discharge events during testing, and methods for fabricating inserts for use in testing semiconductor devices
US20040195584A1 (en) * 2002-08-29 2004-10-07 Hembree David R Test insert with electrostatic discharge structures and associated methods
US7705349B2 (en) 2002-08-29 2010-04-27 Micron Technology, Inc. Test inserts and interconnects with electrostatic discharge structures
US6879476B2 (en) 2003-01-22 2005-04-12 Freescale Semiconductor, Inc. Electrostatic discharge circuit and method therefor
US20040141268A1 (en) * 2003-01-22 2004-07-22 Miller James W. Electrostatic discharge circuit and method therefor
US20040141267A1 (en) * 2003-01-22 2004-07-22 Khazhinsky Michael G. Electrostatic discharge circuit and method therefor
US20050185351A1 (en) * 2003-01-22 2005-08-25 Miller James W. Electrostatic discharge circuit and method therefor
US6900970B2 (en) 2003-01-22 2005-05-31 Freescale Semiconductor, Inc. Electrostatic discharge circuit and method therefor
US7236339B2 (en) 2003-01-22 2007-06-26 Freescale Semiconductor, Inc. Electrostatic discharge circuit and method therefor
US7940501B2 (en) 2003-09-24 2011-05-10 Broadcom Corporation System and method to relieve ESD requirements of NMOS transistors
US20050063111A1 (en) * 2003-09-24 2005-03-24 Broadcom Corporation System and method to relieve ESD requirements of NMOS transistors
US7515390B2 (en) * 2003-09-24 2009-04-07 Broadcom Corporation System and method to relieve ESD requirements of NMOS transistors
US20090185318A1 (en) * 2003-09-24 2009-07-23 Hongwei Wang System and method to relieve esd requirements of nmos transistors
US20050083620A1 (en) * 2003-10-15 2005-04-21 Yung-Hao Lin Esd protection circuit with a stack-coupling device
US20060181823A1 (en) * 2005-02-11 2006-08-17 Miller James W I/O cell ESD system
US7446990B2 (en) 2005-02-11 2008-11-04 Freescale Semiconductor, Inc. I/O cell ESD system
US20060262469A1 (en) * 2005-05-17 2006-11-23 Freescale Semiconductor, Inc. Integrated circuit with multiple independent gate field effect transistor (MIGFET) rail clamp circuit
US7301741B2 (en) 2005-05-17 2007-11-27 Freescale Semiconductor, Inc. Integrated circuit with multiple independent gate field effect transistor (MIGFET) rail clamp circuit
US20070097581A1 (en) * 2005-11-01 2007-05-03 Freescale Semiconductor, Inc. Electrostatic discharge (ESD) protection circuit for multiple power domain integrated circuit
US7593202B2 (en) 2005-11-01 2009-09-22 Freescale Semiconductor, Inc. Electrostatic discharge (ESD) protection circuit for multiple power domain integrated circuit
US20070267755A1 (en) * 2006-05-16 2007-11-22 Vo Nhat D Integrated circuit having pads and input/output (i/o) cells
US7808117B2 (en) 2006-05-16 2010-10-05 Freescale Semiconductor, Inc. Integrated circuit having pads and input/output (I/O) cells
US7589945B2 (en) 2006-08-31 2009-09-15 Freescale Semiconductor, Inc. Distributed electrostatic discharge protection circuit with varying clamp size
US20080062596A1 (en) * 2006-08-31 2008-03-13 Freescale Semiconductor, Inc. Distributed electrostatic discharge protection circuit with varying clamp size
US7777998B2 (en) 2007-09-10 2010-08-17 Freescale Semiconductor, Inc. Electrostatic discharge circuit and method therefor
US7817387B2 (en) 2008-01-09 2010-10-19 Freescale Semiconductor, Inc. MIGFET circuit with ESD protection
US20090174973A1 (en) * 2008-01-09 2009-07-09 Khazhinsky Michael G Migfet circuit with esd protection
CN112332392A (en) * 2019-08-05 2021-02-05 珠海格力电器股份有限公司 Protection circuit and integrated circuit chip

Similar Documents

Publication Publication Date Title
US5361185A (en) Distributed VCC/VSS ESD clamp structure
EP0723706B1 (en) Electrostatic discharge protection circuit
US5237395A (en) Power rail ESD protection circuit
JP3174636B2 (en) Electrostatic discharge protection for CMOS integrated circuits
US7907373B2 (en) Electrostatic discharge circuit
US7123054B2 (en) Semiconductor integrated circuit device having an ESD protection unit
US5898205A (en) Enhanced ESD protection circuitry
US5986307A (en) Silicon-controlled rectifier integral with output buffer
US6756642B2 (en) Integrated circuit having improved ESD protection
US7323752B2 (en) ESD protection circuit with floating diffusion regions
US5656967A (en) Two-stage fusible electrostatic discharge protection circuit
US7217980B2 (en) CMOS silicon-control-rectifier (SCR) structure for electrostatic discharge (ESD) protection
US5909347A (en) Electrostatic discharge protection circuit having P-type flash memory cell
US5910675A (en) Semiconductor device and method of making the same
US5561312A (en) Protection device for a CMOS integrated circuit apparatus
US6317306B1 (en) Electrostatic discharge protection circuit
US20180083440A1 (en) Integrated circuit electrostatic discharge protection with disable-enable
US7911751B2 (en) Electrostatic discharge device with metal option ensuring a pin capacitance
US6538288B2 (en) ESD protection device with island-like distributed p+ diffusion regions
US7843009B2 (en) Electrostatic discharge protection device for an integrated circuit
US6291964B1 (en) Multiple power source electrostatic discharge protection circuit
JP2839624B2 (en) Semiconductor integrated circuit
US20020060345A1 (en) Esd protection circuit triggered by low voltage
US5513064A (en) Method and device for improving I/O ESD tolerance
KR0172231B1 (en) Electrostatic protection circuit for semiconductor device

Legal Events

Date Code Title Description
AS Assignment

Owner name: ADVANCED MICRO DEVICES, INC., CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:YU, JAMES;REEL/FRAME:006438/0410

Effective date: 19930218

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

REMI Maintenance fee reminder mailed
FPAY Fee payment

Year of fee payment: 12