Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS5361375 A
Publication typeGrant
Application numberUS 08/065,685
Publication dateNov 1, 1994
Filing dateMay 24, 1993
Priority dateFeb 9, 1989
Fee statusPaid
Also published asCA2009555A1, CA2009555C, DE69032334D1, DE69032334T2, EP0382505A2, EP0382505A3, EP0382505B1
Publication number065685, 08065685, US 5361375 A, US 5361375A, US-A-5361375, US5361375 A, US5361375A
InventorsYoshifumi Ogi
Original AssigneeFujitsu Limited
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Virtual computer system having input/output interrupt control of virtual machines
US 5361375 A
Abstract
A virtual computer system including a plurality of virtual machines running in a central processing unit with time shared, an input/output unit generating an input/output interrupt request, and a specific instruction generating part for generating a specific instruction indicating a priority to one of the virtual machines which is running. The system further includes a decision part for determining whether the input/output interrupt request addressed to one of the virtual machines has a priority equal to that indicated by the specific instruction and for generating an interrupt accepting signal when the decision result is affirmative. Moreover, the system includes a monitor part for transferring a right to use the central processing unit from the one of the virtual machines which is running to the one of the virtual machines which is addressed by the input/output interrupt request when the interrupt accepting signal from the decision part is supplied to the monitor part.
Images(5)
Previous page
Next page
Claims(11)
What is claimed is:
1. A virtual computer system, comprising:
at least one central processing unit executing at least one of a plurality of virtual machines on a time shared basis;
input/output means for generating an input/output interrupt request addressed to one of the virtual machines;
specific instruction generating means for setting an interrupt priority of a currently unexecuting virtual machine over each currently executing virtual machine and for generating a specific instruction indicating the interrupt priority to dynamically change interrupt priorities of the virtual machines;
decision means, operatively connected to said input/output means and said specific instruction generating means, for determining whether the input/output interrupt request addressed to the one of the virtual machines is addressed to the currently unexecuting virtual machine, said decision means including;
an interrupt pending register having areas individually provided for each of the virtual machines, at least one of the areas including an identifier indicating the one of the virtual machines to which the input/output interrupt request will be output;
a mask register having areas individually provided for each of the virtual machines and storing mask information indicating whether each of the virtual machines will accept the input/output interrupt request in a corresponding one of the areas for each of the virtual machines, the specific instruction being written into a corresponding one of the areas related to the priority indicated by the specific instruction;
first logic means, operatively connected to said interrupt pending register and said mask register, for determining the one of the virtual machines requested by the input/output interrupt request by comparing the identifier stored in said interrupt pending register and the mask information stored in said mask register in each of the corresponding areas for each of the virtual machines and for outputting the identifier corresponding to the one of the virtual machines requested;
an inner register storing an identifier for each of the currently executing virtual machines; and
second logic means, operatively connected to said first logic means and said inner register, for determining whether the identifier supplied from said first logic means coincides with the identifier supplied from said inner register and for generating an interrupt accepting signal when it is determined that the identifier supplied from said first logic means does not coincide with the identifier supplied from said inner register; and
monitor means, operatively connected to said decision means and said at least one central processing unit executing the virtual machines, for causing said at least one central processing unit to initiate the currently unexecuting virtual machine when said decision means determines that said input/output interrupt request is addressed to the currently unexecuting virtual machine.
2. A virtual computer system as claimed in claim 1, wherein said specific instruction generating means generates the specific instruction before said monitor means causes said at least one central processing unit to initiate the currently unexecuting virtual machine.
3. A virtual computer system as claimed in claim 1, wherein said inner register is provided in said at least one central processing unit, and said second logic means is implemented by said at least one central processing unit.
4. A virtual computer system as claimed in claim 1, further comprising:
memory means for storing the mask information to be stored in said mask register; and
readout means, operatively connected to said memory means and said mask register, for reading out the mask information from said memory means and writing the same into a corresponding one of the areas of said mask register.
5. A virtual computer system as claimed in claim 1, further comprising storage means for storing control data relating to the currently executing virtual machines and for updating the control data when the right to use said at least one central processing unit is transferred to the one of the virtual machines addressed by the input/output interrupt request.
6. A virtual computer system as claimed in claim 1, wherein the virtual machines run in a plurality of central processing units.
7. A virtual computer system as claimed in claim 1, wherein the specific instruction generating means writes the identifier of the one of the virtual machines associated with the specific instruction into a corresponding one of the areas of said mask register when said specific instruction generating means generates the specific instruction.
8. A virtual computer system as claimed in claim 1, wherein said interrupt decision means, said comparison means of said control processing unit, and the one of the virtual machines currently running in said control processing unit operate concurrently.
9. A virtual computer system as claimed in claim 8,
wherein said virtual machine monitor means is executed by said control processing unit,
wherein said main storage means stores data corresponding to said virtual machine monitor means, and
wherein said virtual machine monitor means causes said control processing unit to run the at least one of the first and second virtual machines identified by the interrupt request domain identifier in accordance with the interrupt acceptance signal.
10. A virtual computer system as claimed in claim 1,
wherein at least said virtual machine monitor means and said specific instruction generating means form an input/output processor operatively connected to said main storage means, and
wherein said input/output processor comprises a microprocessor.
11. A virtual computer system as claimed in claim 10, wherein said input/output processor further includes said interrupt decision means.
Description

This application is a continuation of application Ser. No. 07/477,547, filed Feb. 9, 1990, now abandoned.

BACKGROUND OF THE INVENTION

a. Field of the Invention

The present invention generally relates to a virtual computer system, and more particularly to a virtual computer system in which a plurality of guest programs (virtual machines) run in a time shared manner in a central processing unit under the control of a virtual machine monitor. The present invention is specifically concerned with an improvement in input/output interrupt control.

b. Description of the Related Art

Conventionally, there are known various computer systems directed to improving the rate of operation. For example, there is known a virtual computer system in which a plurality of guest programs share time and run in a central processing unit under the control of a virtual machine monitor (host). Currently, such a virtual computer system is required to handle a variety of users' programs. Particularly, a guest program which needs real-time processing, such as a process control, may be required by users.

In such a case, an input/output interrupt event generated by process control mechanism must be handled with high priority. When such an input/output interrupt event is generated while a guest program for processing the process control mechanism does not run in the physical central processing unit, it is necessary to keep the input/output interrupt event waiting until the requested guest program runs in the central processing unit. Thus, there is a need for a procedure for effectively controlling priority of input/output interrupt events among the guest programs.

In a virtual computer system, it is very difficult to control input/output processing which is asynchronous to the operation of the central processing unit. Referring to FIG. 1A, there is illustrated a conventional input/output interrupt control. A plurality of virtual machines (guests) #A, #B, . . . , #D run in a central processing unit 1b with time shared. All input/output instructions and interrupts directed to the virtual machines are input to a virtual machine monitor (VMM, also called host) 1a without exception. The virtual machine monitor subjects the input instructions and interrupts to a scheduling process, and then determines which one of the virtual machines should be accessed for each instruction/interrupt. Then the virtual machine monitor 1a executes interrupt processing by emulation (software interrupt). Thus, the overhead of the system shown in FIG. 1A is large.

Another conventional virtual computer system directed to overcoming the above-mentioned shortcoming has been proposed. The proposed system handles input/output interrupts addressed to the virtual machines without intervention of the virtual machine monitor. In the proposed virtual computer system, the virtual machines are assigned different priorities. Thus, in a state where one of the virtual machines is running in the CPU, when an input/output interrupt directed to another one of the virtual machines having higher priority occurs, the right to exclusively use the CPU should be assigned to the virtual machine having higher priority instead of the virtual machine currently running. In the system shown in FIG. 1A, it is easy to assign the right to use the CPU to the higher-priority virtual machine because all input/output processings are reported to the virtual machine monitor 1a and it is sufficient for the lower-priority virtual machine to return the right to use the CPU to the virtual machine monitor 1a.

FIG. 1B illustrates a virtual computer system which handles input/output interrupts addressed to the virtual machines without intervention of the virtual machine monitor. In the configuration shown in FIG. 1B, it is impossible to discriminate only input/output interrupts directed to virtual machines having priority over the virtual machine which is running from other input/output interrupts and to inform the virtual machine monitor of only the input/output interrupts addressed to the higher-priority virtual machines. This is further described with reference to FIG. 1B.

It is now assumed that an input/output event #1 addressed to virtual machine #D occurs in an input/output unit 5. A channel processor (CHP) 4 discriminates the input/output event #1 and accesses a corresponding sub-channel (SCH) area 22 provided in a main storage device (MS) 2. A domain identification (DMID) data 22a indicating the virtual machine #D is read out from a specific area of the sub-channel area 22 related to the virtual machine #D, and is then transferred to an interrupt pending register 30b of an interrupt hardware (IHW) 30 formed in a memory control unit (MCU) 3. The transferred domain identification data 22a is written into an area corresponding to the domain identification data 22a (virtual machine #D). As will be described later, a virtual machine monitor (VMM) 20 runs in the CPU 10 in a time shared manner with the virtual machines. Thus, the virtual machine monitor 20 is also identified by a corresponding domain information data. Hereafter, the domain identification data is referred to as a domain identifier.

On the other hand, when the virtual machine monitor (VMM) 20 dispatches the virtual machine #D by a predetermined instruction, it accesses a control block 23 corresponding to the domain identifier (DMID) indicative of the virtual machine #D. Then mask information 23b stored in a specific area of the control bock 23 is read out therefrom and transferred to an interrupt mask register 30a formed in the interrupt hardware 30. Then the transferred mask information 23b is written into a corresponding area of the interrupt mask register 30a. At this time, `0` is written into the areas of the interrupt mask register 30a which correspond to virtual machines that are not dispatched. When the domain identifier indicating the virtual machine #D is written into the interrupt mask register 30a, the interrupt hardware 30 compares the mask information relating to the virtual machine #D with the corresponding pending information of the interrupt pending register 30b. When the information coincides, the virtual machine #D is immediately made active.

It can be seen from the above description that it is impossible to initiate a non-running virtual machine until an input/output instruction addressed to this virtual machine is dispatched from the virtual machine monitor 20, even when the requested virtual machine which is not running has priority over a virtual machine which is currently running.

SUMMARY OF THE INVENTION

It is a general object of the present invention to provide an improved virtual computer system in which the aforementioned disadvantage is eliminated.

A more specific object of the present invention is to provide a virtual computer system capable of preferentially accepting an input/output interrupt addressed to a virtual machine having priority over a virtual machine which is running.

The above-mentioned objects of the present invention are achieved by a virtual computer system comprising a plurality of virtual machines running in at least one central processing unit with time shared; an input/output unit generating an input/output interrupt request; and a specific instruction generating unit for generating a specific instruction indicating a priority over one of the virtual machines which is running. The system further comprises a decision unit coupled to the input/output unit and the specific instruction generating unit, for determining whether the input/output interrupt request addressed to one of the virtual machines has a priority equal to that indicated by the specific instruction and for generating an interrupt accepting signal when it is determined that it does. Moreover, the system comprises a monitor unit operatively coupled to the plurality of virtual machines and the decision unit, for transferring a right to use the central processing unit from the one of the virtual machines which is running to the one of the virtual machines which is addressed by the input/output interrupt request when the interrupt accepting signal from the decision unit is supplied to the monitor means.

Further objects, features and advantages of the present invention will become apparent from the following detailed description when read in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a block diagram of a conventional virtual computer system;

FIG. 1B is a block diagram of another conventional virtual computer system;

FIG. 2 is a block diagram of a virtual computer system according to a first preferred embodiment of the present invention;

FIG. 3 is a diagram illustrating a format of a specific instruction;

FIG. 4 is a diagram illustrating a format of a control block; and

FIG. 5 is a block diagram of a second preferred embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A description is given of a preferred embodiment of the present invention with reference to FIGS. 2, 3 and 4, in which those parts which are the same as those shown in FIG. 1B are given the same reference numerals. Before running a virtual machine (#A for example), the virtual machine monitor 20 executes a specific instruction (MGPRT) having an operand indicative of a virtual machine (#A) having priority over a virtual machine (#B) which is running in a CPU 10. Thereby, the virtual machine monitor 20 lets the interrupt hardware 30 know the priority relationship between the virtual machines #A and #B. Thereby, the area of the mask register 30a corresponding to the virtual machine #A is made "open". That is, the virtual machine #A is placed in an interrupt acceptable state. It is noted that in the conventional system shown in FIG. 1B, all the mask register areas except the mask register area relating to a virtual machine currently running are made closed (in a state where any interrupts are not acceptable).

When an input/output interrupt addressed to the virtual machine #A is supplied to the channel processor 4 while the virtual machine #B is running, the domain identifier (interrupt event #1) indicative of the virtual machine #A is transmitted to the interrupt pending register 30b. Then, the interrupt event #1 is written into a corresponding area of the interrupt pending register 30b. The contents of the areas of the interrupt pending register 30b and the mask register 30a corresponding to the virtual machine #A are read out therefrom and then compared with each other by a related arithmetic logic unit (ALU) provided in an ALU group 31. Each ALU of the ALU group 31 functions as an AND gate. When data in each area of the interrupt pending register 30b coincides with data in each corresponding area of the mask register 30a, the corresponding ALU outputs the data stored in each area of the interrupt pending register 30b. The outputs from the ALUs are subjected to a wired-OR operation so that a resultant signal INS (domain identifier) from the ALU group 31 is supplied to an ALU 11b provided in a CPU 10, which has an inner register 11a. The domain identifier of the virtual machine which is currently running is stored in the inner register 11a of the CPU 10. The ALU 11b generates an interrupt accepting signal IAS when the domain identifier from the ALU group 31 does not coincide with data from the inner register 11a. It is noted that when the signal INS is supplied from the ALU group 31, the corresponding input/output interrupt given by the specific instruction MGPRT always has priority to the virtual machine which is running. Then the interrupt accepting signal INS is sent to the virtual machine monitor 20.

A further description is given of the embodiment shown in FIG. 2. Each virtual machine #A and #B runs in the CPU 10 with time shared, and data relating thereto is stored in the main storage device 2. Similarly, the virtual machine monitor 20 runs in the CPU 10 with time shared with the virtual machines #A and #B, and data relating thereto is stored in the main storage device 2. As described previously, when an input/output interrupt is supplied to the channel processor 4, it automatically accesses a corresponding sub-channel (not shown for the sake of simplicity) formed in the main storage device 2 and writes the domain identifier stored therein into a corresponding area of the interrupt pending register 30b. Thereby, the request for interrupt to the addressed virtual machine is generated.

It is now assumed that the virtual machine #B is running in the CPU 10. For the sake of simplicity, two virtual machines #A and #B are described. As described previously, the virtual machine monitor 20 dispatches the virtual machine #B, and accesses a corresponding one of the control blocks 23. Then the virtual machine monitor 20 reads out mask information 23b of the virtual machine #B and writes the same into the corresponding bit area of the mask register 30a.

When the aforementioned specific instruction has not yet been issued from the virtual machine monitor 20, data `0` has been written into the area of the mask register 30a corresponding to the virtual machine #A. That is, any input/output interrupt event directed to the virtual machine #A is not accepted. When an input/output interrupt event addressed to the virtual machine #A is requested while the virtual machine #B is running, this request is held in the corresponding area of the interrupt pending register 30b provided in the interrupt hardware 30.

As described previously, the specific instruction MGPRT having priority to the virtual machine which is running is defined. A format of the specific instruction is shown in FIG. 3. The specific instruction is composed of 31 bits, for example, and has an operand consisting of address bits B2 and D2. The virtual machine monitor 20 executes the specific instruction, and accesses a control block 23 indicated by the operand of the specific instruction. A control block 23 is provided for each virtual machine.

FIG. 4 illustrates a format of each control block 23. The control block 23 has the aforementioned domain identifier 23`a. When the illustrated control block 23 relates to the virtual machine #A, domain identifier 23a indicates the virtual machine #A. Further, the control block 23 includes a general purpose register (GR) 23c, a control register (CR) 23dand a floating-point register (FPR) 23e. The mask information 23b is provided in the control register 23d.

When the control block 23 is accessed by the specific instruction MGPRT, the mask information is read out therefrom and then written into the area of the mask register 30a indicated by the domain identifier 23a written into the control block 23. Once the mask information is written into the mask register 30a, it is held until the designated virtual machine is given the right to use the CPU 10, or the specific instruction MGPRT is issued to another virtual machine. It is noted that the mask register 30a and the interrupt pending register 30b each have areas equal in number to the number of virtual machines. For example, when five virtual machines are provided, each of the registers 30a and 30b has five areas. In this case, it is possible to write mask information relating to more than one virtual machine into the corresponding areas of the mask register 30a by the specific instruction MGPRT. As described later, each of the registers 30a and 30b further has an area assigned to the virtual machine monitor 20.

It is now assumed that the specific instruction MGPRT directed to the control block 23 associated with the virtual machine #A is generated by the virtual machine monitor 20. The mask information is read out from the control block 23 and is then written into the corresponding area of the mask register 30a. It is noted that it is possible to write the mask information into the area of the mask register 30a corresponding to the virtual machine #A even when the virtual machine #B is running. In the aforementioned conventional system, such writing of the mask information relating to the virtual machine #A is inhibited.

The contents of the mask register 30a and the interrupt pending register 30b are always compared with each other independently of the status of the CPU 10. That is, the bits written into the areas of the registers 30a and 30b relating to the virtual machine #A are compared with each other, and similarly the bits written into the areas of the registers 30a and 30b relating to the virtual machine #B are compared with each other. Comparing is done by a logic AND operation on the compared bits. When the result of the comparison (logic AND operation) has a value other than zero, the interrupt hardware 30 generates the signal INS indicative of the domain identifier, which instructs the CPU 10 to execute an interrupt sequence.

It is noted that the virtual machine monitor 20 is formed by a program which is executed by the CPU 10, and is controlled in common with the virtual machines #A and #B. Thus, the mask register 30a and the interrupt pending register 30b each have an area provided for the virtual machine monitor 20.

As described previously, the CPU 10 has inner register 11a and ALU 11b. The inner register 11a has information on which one of the virtual machines #A and #B and the virtual machine monitor 20 is running. When the interrupt sequence is made active in response to the signal INS, the ALU 11b of the CPU 10 compares the content of the inner register 11a with the signal INS supplied from the interrupt hardware 30. When the signals (domain identifiers) coincide, the request for interrupt written in the interrupt pending register 30b is handled in the conventional manner. That is, this interrupt becomes acceptable when the virtual machine monitor 20 dispatches the requested virtual machine.

On the other hand, when the domain identifier from the inner register 11a does not coincide with the domain identifier from the interrupt hardware 30, the CPU 10 concludes that the request for input/output interrupt from a virtual machine (#A in this case) having priority over the virtual machine which is running (#B in this case) is acceptable. Then the CPU 10 saves operation environments of virtual machine #B in the general purpose register 23c, the control register 23d and the floating-point register 23e of the control block 23 related to the virtual machine #B. Thereafter, the CPU 10 assigns the right to use the CPU 10 to the virtual machine monitor 20.

Then, the virtual machine monitor 20 immediately assigns the right to use the CPU 10 to the virtual machine #A so that the virtual machine #A can execute the requested input/output interrupt processing.

A description is given of a second embodiment of the present invention with reference to FIG. 5. According to the second embodiment, the function of the interrupt hardware 30 is provided in an input/output processor. The second embodiment includes a physical CPU 50 and an input/output processor 60. The CPU 50 includes a register 51, a comparator 52, a latch 53, a register 54, signal lines 55 and 56, and a CPU control circuit 57. The register 51 stores the domain identifier of a virtual machine/virtual machine monitor currently running in the physical CPU 50. When the CPU 50 generates a state transition (transfer of the right to use the CPU 50) between the virtual machine monitor and one of the virtual machines formed in the CPU 50, the domain identifier of the virtual machine monitor/virtual machine is written into the register 51. The value written into the register 51 serves as an input to the comparator 52. The latch circuit 53 stores an input/output interrupt signal 53a from the input/output processor 60. The input/output interrupt signal 53a from the input/output processor 60 is supplied to a signal line connected to a corresponding CPU (CPU 50 in the illustrated case). That is, when the input/output interrupt signal 53a is made active, it is set to a logical value `1`. The register 54 stores the domain identifier of a virtual machine/virtual machine monitor, which is sent together with the input/output interrupt signal 53a so that the input/output processor 60 lets the CPU 50 know which one of the virtual machines is related to the generated input/output interrupt signal 53a. For example, another input/output interrupt event is connected to another interrupt line 53b. The input/output processor 60 sends the domain identifier to the register 54 only when an interrupt event addressed to one of the virtual machines that is running (specified by registers 62 and 63 described later) occurs, or an input/output interrupt event which is caused by the specific instruction MGPRT and addressed to a higher-priority virtual machine (specified by a register 69) occurs. The virtual machine which is declared beforehand to have priority over the virtual machine currently running does not run in parallel with the currently running virtual machine. Thus, information such as stored in the register 63 for designating the correspondence to the physical CPU 50 is unnecessary as will be described later.

The comparator 52 compares the domain identifier from the register 54 with the domain identifier from the register 51. When the values of the supplied domain identifiers are equal, the comparator 52 activates the signal line 55 connected to he CPU control circuit 57 so that a normal input/output interrupt is generated. On the other hand, when the values of the domain identifiers are not equal, the comparator 52 makes the signal line 56 active so that an input/output interrupt caused by the specific instruction MGPRT is generated. The comparator 52 performs the comparison operation only when the signal from the latch 53 is `1`. The CPU control circuit 57 provides a CPU operation, particularly a control procedure for handling input/output interrupt.

The input/output processor 60 includes registers 61, 62, 63 and 64, a register stack 65, an address circuit 66, a data register 67, an input/output control microprocessor (hereafter simply referred to as a microprocessor) 68 and a register 69. A modified value of the mask information obtained by executing a mask information changing instruction in the CPU 50 is written into the register 61. The domain identifier used for a virtual machine or virtual machine monitor which is to run after the current time, is written into the register 62 in a case where the right to use the CPU 50 is transferred from the virtual machine monitor to one of the virtual machines, the mask changing instruction is executed by the CPU 50, or the right to use the CPU 50 is transferred from a currently running virtual machine to the virtual machine monitor. Information written into the register 62 indicates which mask information stored in the register stack 65 should be used for input/output interrupt control in the CPU 50 and which one of the areas the mask information stored in the register 61 is to be written into.

A logical CPU number of a virtual machine or virtual machine monitor which is to run after the current time, is written into the register 62 in a case where the right to use the CPU 50 is transferred from the virtual machine monitor to one of the virtual machines, the mask changing instruction is executed by the CPU 50, or the right to use the CPU 50 is transferred from a currently running virtual machine to the virtual machine monitor. "Logical CPU" is a unit of operation of the virtual machine monitor or each virtual machine. It is noted that each virtual machine is not informed beforehand of which one of the logical CPUs is used because the virtual machine monitor is free to dynamically determine beforehand which one of the logical CPUs should be run in which one of the physical CPUs. The interrupt signal 53a from the input/output processor 60 is supplied together with information on designation of one of the physical CPUs. Thus, it is necessary for the input/output processor 60 to known which one of the virtual machines relating to which one of the logical CPUs is running in which one of the physical CPUs. Information written into the register 63 indicates which mask information stored in the register stack 65 should be used for input/output interrupt control in the CPU 50 and which one of the areas the mask information stored in the register 61 is to be written into.

The register 64 stores information indicating whether the right to use the CPU 50 has been transferred between the virtual machine monitor and one of the virtual machines, or whether the input/output interrupt mask information changing instruction has been executed. When the right to use the CPU 50 has been transferred between the virtual machine monitor and one of the virtual machines, the contents of the registers 62 and 63 are read out therefrom by the microprocessor 68, and then written into a local area of the microprocessor 68 provided for a corresponding one of the physical CPUs. When the input/output processor 60 tries to issue an input/output interrupt to the corresponding one of the physical CPUs, the microprocessor 68 reads out the data stored in the corresponding local area thereof, and supplies the address generator 66 with the readout data. Thereby the corresponding mask information is read out from the corresponding area of the register stack 65, and then supplied to the microprocessor 68 through the register 67. After that, the microprocessor 68 determines whether the interrupt signal 53a should be turned ON (made active). When the input/output interrupt changing instruction is executed, the contents of the registers 62 and 63 at the same time the mask information is written into the register 61 are supplied to the address circuit 66 by the control of the microprocessor 68. Then the content of the register 61 is stored in a corresponding area of the register stack 65 which is associated with the logical CPU of the running guest on the physical CPU 50.

The register stack 65 stores values of mask information for all the logical CPUs relating to all the virtual machines/monitors. The address circuit 66 supplies the register stack 65 with an address signal. The data register 67 stores data read out from the register stack 65. The microprocessor 68 actually executes the operation of the input/output processor 60, and has a memory in which a microprogram is stored, and the aforementioned local area in which the domain identifier of the virtual machine/monitor which is operating and the logical CPU number thereof. The register 69 stores the domain identifier of the virtual machine which has been declared by the CPU 50 so as to have priority to the virtual machine which is running. The domain identifier is written into the register 69 when the specific instruction MGPRT is executed by the CPU controller 57. Registers each identical to the register 69 are provided individually for the physical CPUs. Even when the same virtual machine is declared by a plurality of physical CPUs so as to have a higher priority, a certain input/output interrupt request is not supplied to more than one of the virtual machines. That is, the microprocessor 68 selects a corresponding one of the virtual machines, and supplies the same with the input/output interrupt request.

The present invention is not limited to the specifically described embodiments, and variations and modifications may be made without departing from the scope of the present invention.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US4001783 *Mar 26, 1975Jan 4, 1977Honeywell Information Systems, Inc.Priority interrupt mechanism
US4400769 *Feb 20, 1980Aug 23, 1983Fujitsu LimitedVirtual machine system
US4524415 *Dec 7, 1982Jun 18, 1985Motorola, Inc.Virtual machine data processor
US4564903 *Oct 5, 1983Jan 14, 1986International Business Machines CorporationPartitioned multiprocessor programming system
US4658351 *Oct 9, 1984Apr 14, 1987Wang Laboratories, Inc.Task control means for a multi-tasking data processing system
US4689739 *Mar 28, 1983Aug 25, 1987Xerox CorporationMethod for providing priority interrupts in an electrophotographic machine
US4734882 *Apr 1, 1985Mar 29, 1988Harris Corp.For use with a data processing system
US4835685 *May 6, 1985May 30, 1989Computer X, Inc.Virtual single machine with message-like hardware interrupts and processor exceptions
US4837674 *Feb 9, 1987Jun 6, 1989Nec CorporationCircuit arrangement capable of quickly processing an interrupt in a virtual machine operated by a plurality of operating systems
US4843541 *Jul 29, 1987Jun 27, 1989International Business Machines CorporationLogical resource partitioning of a data processing system
US4860190 *Sep 2, 1986Aug 22, 1989Fujitsu LimitedComputer system for controlling virtual machines
US4885681 *Jan 16, 1985Dec 5, 1989Hitachi, Ltd.I/O Execution method for a virtual machine system and system therefor
US4887202 *Jul 30, 1986Dec 12, 1989Hitachi, Ltd.Input-output control method in a virtual machine system
US4908750 *Dec 11, 1985Mar 13, 1990Wang Laboratories, Inc.Data processing system having tunable operating system means
US4912628 *Mar 15, 1988Mar 27, 1990International Business Machines Corp.Suspending and resuming processing of tasks running in a virtual machine data processing system
US4914583 *Apr 13, 1988Apr 3, 1990Motorola, Inc.Method of indicating processes resident within a cell of a data processing system
US4985831 *Oct 31, 1988Jan 15, 1991Evans & Sutherland Computer Corp.Multiprocessor task scheduling system
US5023771 *Sep 7, 1990Jun 11, 1991Nec CorporationController for two timers of a virtual machine system, one updated only in the VMOS mode
US5109489 *Jun 21, 1989Apr 28, 1992Hitachi, Ltd.I/o execution method for a virtual machine system and system therefor
US5129064 *Aug 27, 1990Jul 7, 1992International Business Machines CorporationSystem and method for simulating the I/O of a processing system
EP0210640A2 *Jul 29, 1986Feb 4, 1987Hitachi, Ltd.Input-output control system in a virtual machine system
EP0213952A2 *Sep 1, 1986Mar 11, 1987Fujitsu LimitedComputer system for controlling virtual machines
Non-Patent Citations
Reference
1 *Patent Abstracts of Japan, vol. 13, No. 91, May 9, 1989 for Japanese Published Patent Application, 1 17129, published Jan. 20, 1989.
2Patent Abstracts of Japan, vol. 13, No. 91, May 9, 1989 for Japanese Published Patent Application, 1-17129, published Jan. 20, 1989.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US5506975 *Dec 14, 1993Apr 9, 1996Hitachi, Ltd.Virtual machine I/O interrupt control method compares number of pending I/O interrupt conditions for non-running virtual machines with predetermined number
US5572694 *Nov 26, 1993Nov 5, 1996Fujitsu LimitedVirtual system for detecting access paths belonging to same group from plurality of access paths to reach device designated by command with reference to table
US5805867 *May 27, 1997Sep 8, 1998Fujitsu LimitedMulti-processor simulation apparatus and method
US5812823 *Jan 2, 1996Sep 22, 1998International Business Machines CorporationMethod and system for performing an emulation context save and restore that is transparent to the operating system
US5898855 *Sep 20, 1994Apr 27, 1999Hitachi, Ltd.Control method for virtual machine running time in virtual machine system
US5923900 *Mar 10, 1997Jul 13, 1999International Business Machines CorporationCircular buffer with n sequential real and virtual entry positions for selectively inhibiting n adjacent entry positions including the virtual entry positions
US5940607 *Jan 27, 1997Aug 17, 1999Samsung Electronics Co., Ltd.Device and method for automatically selecting a central processing unit driving frequency
US5987537 *Apr 30, 1997Nov 16, 1999Compaq Computer CorporationFunction selector with external hard wired button array on computer chassis that generates interrupt to system processor
US6212678 *Jul 27, 1998Apr 3, 2001Microapl LimitedMethod of carrying out computer operations
US6728746 *Dec 15, 1995Apr 27, 2004Fujitsu LimitedComputer system comprising a plurality of machines connected to a shared memory, and control method for a computer system comprising a plurality of machines connected to a shared memory
US6813766 *Feb 5, 2001Nov 2, 2004Interland, Inc.Method and apparatus for scheduling processes based upon virtual server identifiers
US6820177Jun 12, 2002Nov 16, 2004Intel CorporationProtected configuration space in a protected environment
US6907600Dec 27, 2000Jun 14, 2005Intel CorporationVirtual translation lookaside buffer
US6934817Oct 10, 2003Aug 23, 2005Intel CorporationControlling access to multiple memory zones in an isolated execution environment
US6941458Sep 22, 2000Sep 6, 2005Intel CorporationManaging a secure platform using a hierarchical executive architecture in isolated execution mode
US6957332Mar 31, 2000Oct 18, 2005Intel CorporationManaging a secure platform using a hierarchical executive architecture in isolated execution mode
US6976162Jun 28, 2000Dec 13, 2005Intel CorporationPlatform and method for establishing provable identities while maintaining privacy
US6990579Mar 31, 2000Jan 24, 2006Intel CorporationPlatform and method for remote attestation of a platform
US6996710Mar 31, 2000Feb 7, 2006Intel CorporationPlatform and method for issuing and certifying a hardware-protected attestation key
US6996748Jun 29, 2002Feb 7, 2006Intel CorporationHandling faults associated with operation of guest software in the virtual-machine architecture
US7000051 *Mar 31, 2003Feb 14, 2006International Business Machines CorporationApparatus and method for virtualizing interrupts in a logically partitioned computer system
US7013484Mar 31, 2000Mar 14, 2006Intel CorporationManaging a secure environment using a chipset in isolated execution mode
US7020738Sep 30, 2003Mar 28, 2006Intel CorporationMethod for resolving address space conflicts between a virtual machine monitor and a guest operating system
US7024555Nov 1, 2001Apr 4, 2006Intel CorporationApparatus and method for unilaterally loading a secure operating system within a multiprocessor environment
US7028149Mar 29, 2002Apr 11, 2006Intel CorporationSystem and method for resetting a platform configuration register
US7035963Dec 27, 2000Apr 25, 2006Intel CorporationMethod for resolving address space conflicts between a virtual machine monitor and a guest operating system
US7058807Apr 15, 2002Jun 6, 2006Intel CorporationValidation of inclusion of a platform within a data center
US7069442Mar 29, 2002Jun 27, 2006Intel CorporationSystem and method for execution of a secured environment initialization instruction
US7073042Dec 12, 2002Jul 4, 2006Intel CorporationReclaiming existing fields in address translation data structures to extend control over memory accesses
US7076669Apr 15, 2002Jul 11, 2006Intel CorporationMethod and apparatus for communicating securely with a token
US7076802Dec 31, 2002Jul 11, 2006Intel CorporationTrusted system clock
US7082615Sep 22, 2000Jul 25, 2006Intel CorporationProtecting software environment in isolated execution
US7089418Mar 31, 2000Aug 8, 2006Intel CorporationManaging accesses in a processor for isolated execution
US7096497Mar 30, 2001Aug 22, 2006Intel CorporationFile checking using remote signing authority via a network
US7103771Dec 17, 2001Sep 5, 2006Intel CorporationConnecting a virtual token to a physical token
US7111176Mar 31, 2000Sep 19, 2006Intel CorporationGenerating isolated bus cycles for isolated execution
US7117376Dec 28, 2000Oct 3, 2006Intel CorporationPlatform and method of creating a secure boot that enforces proper user authentication and enforces hardware configurations
US7124273Feb 25, 2002Oct 17, 2006Intel CorporationMethod and apparatus for translating guest physical addresses in a virtual machine environment
US7124327Jun 29, 2002Oct 17, 2006Intel CorporationControl over faults occurring during the operation of guest software in the virtual-machine architecture
US7127548 *Apr 16, 2002Oct 24, 2006Intel CorporationControl register access virtualization performance improvement in the virtual-machine architecture
US7130949 *May 12, 2003Oct 31, 2006International Business Machines CorporationManaging input/output interruptions in non-dedicated interruption hardware environments
US7139890Apr 30, 2002Nov 21, 2006Intel CorporationMethods and arrangements to interface memory
US7142674Jun 18, 2002Nov 28, 2006Intel CorporationMethod of confirming a secure key exchange
US7165181Nov 27, 2002Jan 16, 2007Intel CorporationSystem and method for establishing trust without revealing identity
US7177967Sep 30, 2003Feb 13, 2007Intel CorporationChipset support for managing hardware interrupts in a virtual machine system
US7191440Aug 15, 2001Mar 13, 2007Intel CorporationTracking operating system process and thread execution and virtual machine execution in hardware or in a virtual machine monitor
US7215781Dec 22, 2000May 8, 2007Intel CorporationCreation and distribution of a secret value between two devices
US7222203 *Dec 8, 2003May 22, 2007Intel CorporationInterrupt redirection for virtual partitioning
US7225441Dec 27, 2000May 29, 2007Intel CorporationMechanism for providing power management through virtualization
US7237051Sep 30, 2003Jun 26, 2007Intel CorporationMechanism to control hardware interrupt acknowledgement in a virtual machine system
US7251814Aug 24, 2001Jul 31, 2007International Business Machines CorporationYield on multithreaded processors
US7272831Mar 30, 2001Sep 18, 2007Intel CorporationMethod and apparatus for constructing host processor soft devices independent of the host processor operating system
US7281075Apr 24, 2003Oct 9, 2007International Business Machines CorporationVirtualization of a global interrupt queue
US7287197Sep 15, 2003Oct 23, 2007Intel CorporationVectoring an interrupt or exception upon resuming operation of a virtual machine
US7296267Jul 12, 2002Nov 13, 2007Intel CorporationSystem and method for binding virtual machines to hardware contexts
US7302511Oct 13, 2005Nov 27, 2007Intel CorporationChipset support for managing hardware interrupts in a virtual machine system
US7305592Jun 30, 2004Dec 4, 2007Intel CorporationSupport for nested fault in a virtual machine environment
US7308576Dec 31, 2001Dec 11, 2007Intel CorporationAuthenticated code module
US7313669Feb 28, 2005Dec 25, 2007Intel CorporationVirtual translation lookaside buffer
US7318235Dec 16, 2002Jan 8, 2008Intel CorporationAttestation using both fixed token and portable token
US7356735Mar 30, 2004Apr 8, 2008Intel CorporationProviding support for single stepping a virtual machine in a virtual machine environment
US7356817Mar 31, 2000Apr 8, 2008Intel CorporationReal-time scheduling of virtual machines
US7366305Sep 30, 2003Apr 29, 2008Intel CorporationPlatform and method for establishing trust without revealing identity
US7380041 *Jun 30, 2006May 27, 2008International Business Machines CorporationManaging input/output interruptions in non-dedicated interruption hardware environments
US7389427Sep 28, 2000Jun 17, 2008Intel CorporationMechanism to secure computer output from software attack using isolated execution
US7392415Jun 26, 2002Jun 24, 2008Intel CorporationSleep protection
US7395405Jan 28, 2005Jul 1, 2008Intel CorporationMethod and apparatus for supporting address translation in a virtual machine environment
US7418584 *Feb 25, 2005Aug 26, 2008Advanced Micro Devices, Inc.Executing system management mode code as virtual machine guest
US7424709Sep 15, 2003Sep 9, 2008Intel CorporationUse of multiple virtual machine monitors to handle privileged events
US7428485Aug 24, 2001Sep 23, 2008International Business Machines CorporationSystem for yielding to a processor
US7454548Sep 7, 2007Nov 18, 2008International Business Machines CorporationManaging input/output interruptions in non-dedicated interruption hardware environments, and methods therefor
US7454611Jan 11, 2007Nov 18, 2008Intel CorporationSystem and method for establishing trust without revealing identity
US7480806Feb 22, 2002Jan 20, 2009Intel CorporationMulti-token seal and unseal
US7490070Jun 10, 2004Feb 10, 2009Intel CorporationApparatus and method for proving the denial of a direct proof signature
US7516330Nov 29, 2005Apr 7, 2009Intel CorporationPlatform and method for establishing provable identities while maintaining privacy
US7543095May 23, 2008Jun 2, 2009International Business Machines CorporationManaging input/output interruptions in non-dedicated interruption hardware environments
US7546406 *Jul 20, 2007Jun 9, 2009International Business Machines CorporationVirtualization of a global interrupt queue
US7546457Mar 31, 2005Jun 9, 2009Intel CorporationSystem and method for execution of a secured environment initialization instruction
US7581219 *Mar 30, 2005Aug 25, 2009Intel CorporationTransitioning between virtual machine monitor domains in a virtual machine environment
US7610611Sep 19, 2003Oct 27, 2009Moran Douglas RPrioritized address decoder
US7620949Mar 31, 2004Nov 17, 2009Intel CorporationMethod and apparatus for facilitating recognition of an open event window during operation of guest software in a virtual machine environment
US7631196Feb 25, 2002Dec 8, 2009Intel CorporationMethod and apparatus for loading a trustable operating system
US7636844Nov 17, 2003Dec 22, 2009Intel CorporationMethod and system to provide a trusted channel within a computer system for a SIM device
US7694301 *Jun 27, 2003Apr 6, 2010Nathan LaredoMethod and system for supporting input/output for a virtual machine
US7707341 *Feb 25, 2005Apr 27, 2010Advanced Micro Devices, Inc.Virtualizing an interrupt controller
US7739521Sep 18, 2003Jun 15, 2010Intel CorporationMethod of obscuring cryptographic computations
US7783779 *Sep 19, 2003Aug 24, 2010Vmware, IncStorage multipath management in a virtual computer system
US7793111Sep 28, 2000Sep 7, 2010Intel CorporationMechanism to handle events in a machine with isolated execution
US7797699 *Sep 23, 2004Sep 14, 2010Intel CorporationMethod and apparatus for scheduling virtual machine access to shared resources
US7802085Feb 18, 2004Sep 21, 2010Intel CorporationApparatus and method for distributing private keys to an entity with minimal secret, unique information
US7809957Sep 29, 2005Oct 5, 2010Intel CorporationTrusted platform module for generating sealed data
US7818808Dec 27, 2000Oct 19, 2010Intel CorporationProcessor mode for limiting the operation of guest software running on a virtual machine supported by a virtual machine monitor
US7836275May 22, 2008Nov 16, 2010Intel CorporationMethod and apparatus for supporting address translation in a virtual machine environment
US7840962Sep 30, 2004Nov 23, 2010Intel CorporationSystem and method for controlling switching between VMM and VM using enabling value of VMM timer indicator and VMM timer value having a specified time
US7861245Jun 29, 2009Dec 28, 2010Intel CorporationMethod and apparatus for facilitating recognition of an open event window during operation of guest software in a virtual machine environment
US7900017Dec 27, 2002Mar 1, 2011Intel CorporationMechanism for remapping post virtual machine memory pages
US7921293Jan 24, 2006Apr 5, 2011Intel CorporationApparatus and method for unilaterally loading a secure operating system within a multiprocessor environment
US7958506 *Jun 22, 2006Jun 7, 2011Intel CorporationTime sliced interrupt processing on virtualized platform
US7987464 *Jul 25, 2006Jul 26, 2011International Business Machines CorporationLogical partitioning and virtualization in a heterogeneous architecture
US7992143Feb 13, 2008Aug 2, 2011Applianz Technologies, Inc.Systems and methods of creating and accessing software simulated computers
US8014530Mar 22, 2006Sep 6, 2011Intel CorporationMethod and apparatus for authenticated, recoverable key distribution with no database secrets
US8037314Dec 22, 2003Oct 11, 2011Intel CorporationReplacing blinded authentication authority
US8079034Sep 15, 2003Dec 13, 2011Intel CorporationOptimizing processor-managed resources based on the behavior of a virtual machine monitor
US8104083 *Mar 31, 2008Jan 24, 2012Symantec CorporationVirtual machine file system content protection system and method
US8108196Jul 17, 2008Jan 31, 2012International Business Machines CorporationSystem for yielding to a processor
US8131901Jun 4, 2009Mar 6, 2012Arm LimitedInterrupt control for virtual processing apparatus
US8146078Oct 29, 2004Mar 27, 2012Intel CorporationTimer offsetting mechanism in a virtual machine environment
US8156343Nov 26, 2003Apr 10, 2012Intel CorporationAccessing private data about the state of a data processing machine from storage that is publicly accessible
US8185734Jun 8, 2009May 22, 2012Intel CorporationSystem and method for execution of a secured environment initialization instruction
US8195914Feb 3, 2011Jun 5, 2012Intel CorporationMechanism for remapping post virtual machine memory pages
US8234429 *Nov 5, 2009Jul 31, 2012Advanced Micro Devices, Inc.Monitoring interrupt acceptances in guests
US8386788Nov 10, 2009Feb 26, 2013Intel CorporationMethod and apparatus for loading a trustable operating system
US8392918May 13, 2011Mar 5, 2013Intel CorporationInterrupt processing on virtualized platform during periods which virtual machines are enabled to get interrupts according to scheduling policy
US8407476Nov 10, 2009Mar 26, 2013Intel CorporationMethod and apparatus for loading a trustable operating system
US8490080Jun 24, 2011Jul 16, 2013Applianz Technologies, Inc.Systems and methods of creating and accessing software simulated computers
US8504752 *Jun 23, 2009Aug 6, 2013Panasonic CorporationVirtual machine control device, virtual machine control program, and virtual machine control circuit for managing interrupts of plural virtual machines
US8522044Aug 26, 2010Aug 27, 2013Intel CorporationMechanism to handle events in a machine with isolated execution
US8533777Dec 29, 2004Sep 10, 2013Intel CorporationMechanism to determine trust of out-of-band management agents
US8543772Dec 2, 2010Sep 24, 2013Intel CorporationInvalidating translation lookaside buffer entries in a virtual machine (VM) system
US8639915Mar 30, 2010Jan 28, 2014Intel CorporationApparatus and method for distributing private keys to an entity with minimal secret, unique information
US8645688Apr 11, 2012Feb 4, 2014Intel CorporationSystem and method for execution of a secured environment initialization instruction
US8671275Aug 26, 2010Mar 11, 2014Intel CorporationMechanism to handle events in a machine with isolated execution
US8739156 *Jul 23, 2008May 27, 2014Red Hat Israel, Ltd.Method for securing the execution of virtual machines
US8751752Mar 15, 2013Jun 10, 2014Intel CorporationInvalidating translation lookaside buffer entries in a virtual machine system
US20100191887 *Nov 5, 2009Jul 29, 2010Serebrin Benjamin CMonitoring Interrupt Acceptances in Guests
US20110106993 *Jun 23, 2009May 5, 2011Katsuhiro ArinobuVirtual machine control device, virtual machine control program, and virtual machine control circuit
Classifications
U.S. Classification718/1, 710/48, 700/2, 710/40, 718/103, 710/264
International ClassificationG06F9/455, G06F9/48, G06F9/46, G06F13/10, G06F13/24
Cooperative ClassificationG06F13/24, G06F9/45533, G06F9/4812, G06F13/10
European ClassificationG06F9/48C2, G06F9/455H, G06F13/10, G06F13/24
Legal Events
DateCodeEventDescription
Apr 7, 2006FPAYFee payment
Year of fee payment: 12
Apr 4, 2002FPAYFee payment
Year of fee payment: 8
Apr 20, 1998FPAYFee payment
Year of fee payment: 4