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Publication numberUS5382549 A
Publication typeGrant
Application numberUS 08/085,139
Publication dateJan 17, 1995
Filing dateJul 2, 1993
Priority dateNov 10, 1989
Fee statusPaid
Publication number08085139, 085139, US 5382549 A, US 5382549A, US-A-5382549, US5382549 A, US5382549A
InventorsJiro Ohshima, Toshiyo Motozima
Original AssigneeKabushiki Kaisha Toshiba
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method of manufacturing polycrystalline silicon having columnar orientation
US 5382549 A
Abstract
In a semiconductor device, the polysilicon resistor or electrode formed of a polysilicon film has a columnar crystalline orientation vertical to the surface of the semiconductor substrate. Thus, the variation in grain size due to the subsequent heat treatment is small, and therefore, the polysilicon resistor or electrode has a high uniformity of resistance value. In addition, since the polysilicon film is formed in the groove in the insulating film formed on the semiconductor substrate, a polysilicon pattern surface which is flush with the surface of the insulating film can be obtained. Thus, unevenness does not occur on the surface of a passivation CVD film coated in the subsequent step, and metal wires formed thereon are not cut.
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Claims(2)
What is claimed is:
1. A method of manufacturing a semiconductor device, said method comprising the steps of:
forming an insulating film made of a single composition on a semiconductor substrate;
ion-implanting silicon in a given area of said insulating film, thereby forming a silicon nucleus; and
forming a polysilicon film only on the area of the silicon nucleus by means of vapor-phase growth, said polysilicon film having a columnar crystalline orientation vertical to the surface of the semiconductor substrate.
2. A method of manufacturing a semiconductor device, said method comprising the steps of:
forming an insulating film on a semiconductor substrate:
forming a resist pattern on said insulating film;
etching a given area of said insulating film, using said resist pattern as a mask, to form a groove in said given area of the insulating film;
ion-implanting silicon in said given area of the insulating film, using said resist pattern as a mask, to form a silicon nucleus on the bottom of said groove;
forming a polysilicon film only on the area of the silicon nucleus by means of vapor-phase growth, said polysilicon film having a columnar crystalline orientation vertical to the surface of the semiconductor substrate.
Description

This application is a division of application Ser. No. 07/883,244 filed May 7, 1992, which is a continuation of application Ser. No. 07/610,228, filed Nov. 9, 1990 both abandoned.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to a semiconductor device and a method of manufacturing the semiconductor device, and particularly to a technique of forming a polysilicon film of which a polysiliccn resistor, an electrode, etc. are made.

2. Description of the Related Art

FIG. 1 shows a structure of a conventional semiconductor device having, for example, a polysilicon resistor.

An insulating film 12 is formed on a semiconductor substrate 11. A polysilicon resistor 13 is formed on the insulating film 12 in a mesa shape. A passivation CVD film 14, for example, is formed on the polysilicon resistor 13.

This semiconductor device is formed by the following method.

First, the insulating film 12 is formed on the semiconductor substrate 11. Then, using a vacuum CVD device, for example, a polysilicon film having a grain size of 0.01 to 0.1 μm is formed over the entire of a major surface of the substrate 11. The polysilicon film is etched by a selective etching process, thereby obtaining the polysilicon resistor 13 having a desired shape. Further, the passivation CVD film 14, for example, is formed over the entire semiconductor structure.

In the semiconductor device thus manufactured, however, the polysilicon resistor 13 has a mesa shape and therefore the surface of the substrate 11 is uneven. Consequently, metal wires formed on the polysilicon resistor 13 may be cut and the reliability of the product may be degraded.

Further, since the polysilicon resistor 13 is composed of granular crystals, the grain size may vary in a heat treatment step of electrically activating impurities in the polysilicon resistor 13 and in a heat treatment step performed after the formation of the polysilicon resistor 13. As a result, the carrier mobility in the polysilicon resistor 13 varies and the uniformity of the polysilicon resistance is deteriorated.

As has been stated above, in the conventional semiconductor device, since the polysilicon resistor is formed on the insulating film in a mesa shape, metal wires formed on the polysilicon resistor may be cut and the reliability of the product may be degraded. In addition, the grain size may vary in a heat treatment after the formation of the polysilicon resistor, and the uniformity of the resistance is deteriorated.

SUMMARY OF THE INVENTION

The object of the present invention is to provide a semiconductor device and a method of manufacturing the same, wherein a variation in grain size is reduced in a subsequent heat treatment step thereby to obtain a polysilicon resistor having a high uniformity of resistance value, and the surface of a substrate can be flattened.

To achieve this object, this invention provides a semiconductor device wherein a polysilicon resistor or electrode is formed of a polysilicon film having a columnar crystalline orientation vertical to the surface of a semiconductor substrate.

This invention also provides a semiconductor device comprising: a semiconductor substrate; an insulating film formed on the semiconductor substrate; a groove formed in the insulating film; and a polysilicon film formed in the groove and having a columnar crystalline orientation vertical to the surface of the semiconductor substrate.

A method of manufacturing the semiconductor device comprises the steps of: forming an insulating film on a semiconductor substrate; ion-implanting silicon in a predetermined area of the insulating film, thereby forming a silicon nucleus; and forming a polysilicon film only on the area of the silicon nucleus by means of vapor-phase growth, which polysilicon film has a columnar crystalline orientation vertical to the surface of the semiconductor substrate.

According to the above structure, the polysilicon resistor or electrode has a columnar crystalline orientation vertical to the surface of the semiconductor substrate; thus, the variation in grain size due to the subsequent heat treatment is small. Therefore, the polysilicon resistor, electrode, etc. formed of the polysilicon film have a high uniformity of resistance value.

In addition, since the polysilicon film is formed in the groove in the insulating film, a polysilicon pattern surface which is flush with the surface of the insulating film can be obtained. Thus, unevenness does not occur on the surface of a passivation CVD film coated in the subsequent step, and metal wires formed thereon are not cut.

Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.

FIG. 1 is a cross-sectional view showing a conventional semiconductor device;

FIG. 2 is a cross-sectional view showing a semiconductor device according to an embodiment of the invention; and

FIGS. 3A and 3B are cross-sectional views illustrating a method of manufacturing the semiconductor device according to the embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A semiconductor device according to an embodiment of the present invention will now be described with reference to the accompanying drawings.

FIG. 2 shows the semiconductor device according to the embodiment of the invention.

A silicon oxide film 22 is formed on a semiconductor substrate 21. A groove 23 is formed in the silicon oxide film 22. A polysilicon film 24 is formed in the groove 23 such that columnar crystals of the polysilicon film 24 are orientated vertically to the surface of the semiconductor substrate 21. The polysilicon film 24 constitutes a polysilicon resistor, an electrode, etc.

According to this structure, the columnar crystals of the polysilicon film 24 are orientated vertically to the surface of the semiconductor substrate; therefore, the variation of the grain size is reduced in the following heat treatment step. Thus, the resistance values of the polysilicon resistor, electrode, etc., which are constituted by the polysilicon film 24, do not vary greatly among wafers.

Furthermore, since the polysilicon film 24 is formed in the groove 23, the surface of the semiconductor structure is flat. Thus, when a passivation CVD film is coated in a later step, unevenness on the surface of the passivation CVD film does not occur and metal wires formed thereon are not cut.

Referring now to FIGS. 3A and 3B, a method of manufacturing the semiconductor device will now be described in detail.

A silicon oxide film 32 is formed on a semiconductor substrate 31, as shown in FIG. 3A. A resist pattern 33 is formed on the silicon oxide film 32. Then, using the resist pattern 33 as a mask, the silicon oxide film 32 is etched to a depth of about 300 nm by means of RIE (reactive ion etching), thus forming a groove 34. Thereafter, using the same mask, silicon (Si) ions are ion-implanted under the conditions of about 35 kv and 11016 atoms/cm2, thereby forming a silicon nucleus only on the bottom of the groove 34.

Subsequently, as is shown in FIG. 3B, after the resist pattern 33 is removed, a polysilicon film 35 is grown in a gas atmosphere of, e.g. SiH2 Cl2, at a temperature of about 900 C. The polysilicon 35 is grown on the silicon nucleus such that the columnar crystals of the polysilicon film 35 are orientated vertically to the surface of the substrate 31. The polysilicon film 35 does not grow in the area other than the area of the silicon nucleus. In order to form a polysilicon resistor having a polysilicon pattern, which is flush with the surface of the silicon oxide film 32, the polysilicon film 35 is grown to a thickness equal to the depth of the groove 34, i.e. about 300 nm.

The sheet resistance of the polysilicon resistor obtained by the present invention, which has a columnar crystal orientation, was compared with that of a conventional granular polysilicon resistor, after they were subjected to a heat treatment step carried out in an N2 (nitrogen) gas atmosphere for 30 minutes at a temperature of about 950 C. It was found that the sheet resistance of the conventional granular polysilicon resistor varied from about 3 kΩ/□ to about 1.5 kΩ/□, while the sheet resistance of the polysilicon resistor of this invention with the columnar crystalline orientation varied slightly, i.e. from about 1.6 kΩ/□ to about 1.5 kΩ/□ (in the case of a polysilicon film doped with B+ with about 40 kV and 31014 atoms/cm2). It follows that the variation of polysilicon resistors obtained by the present invention is small among wafers.

The above embodiments of the present invention were directed to the polysilicon resistor; however, this invention is applicable to a polysilicon electrode.

As has been described above, the semiconductor device and the method of manufacturing the same according to the present invention can bring about the following advantages.

Since the polysilicon film has a columnar crystalline orientation vertical to the surface of the semiconductor substrate, the variation in grain size due to the subsequent heat treatment is small. Thus, the polysilicon resistor, electrode, etc. formed of the polysilicon film have a high uniformity of resistance value and a low variation among wafers.

In addition, since the polysilicon film is formed in the groove to obtain a flat surface of the resultant structure, unevenness does not occur on the surface of a passivation CVD film coated in the subsequent step, and metal wires formed thereon are not cut.

Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details, representative devices, and illustrated examples shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US4035906 *Nov 1, 1976Jul 19, 1977Texas Instruments IncorporatedSilicon gate CCD structure
US4488162 *Jan 3, 1983Dec 11, 1984International Business Machines CorporationSelf-aligned metal field effect transistor integrated circuits using polycrystalline silicon gate electrodes
US4591893 *May 24, 1983May 27, 1986Semiconductor Energy Laboratory Co., Ltd.Photoelectric conversion device utilizing fibrous silicon
US4746621 *Dec 5, 1986May 24, 1988Cornell Research Foundation, Inc.Planar tungsten interconnect
US4807015 *May 13, 1987Feb 21, 1989Hitachi, Ltd.Semiconductor device having electrodes and or interconnections of refractory metal film containing silicon oxide
JPS5562741A * Title not available
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US5825068 *Mar 17, 1997Oct 20, 1998Integrated Device Technology, Inc.Integrated circuits that include a barrier layer reducing hydrogen diffusion into a polysilicon resistor
US5856702 *Apr 18, 1997Jan 5, 1999Nec CorporationPolysilicon resistor and method of producing same
US6049106 *Jan 14, 1999Apr 11, 2000Micron Technology, Inc.Large grain single crystal vertical thin film polysilicon MOSFETs
US6569715Dec 23, 1999May 27, 2003Micron Technology, Inc.Large grain single crystal vertical thin film polysilicon mosfets
US8236428Jun 23, 2009Aug 7, 2012Jx Nippon Mining & Metals CorporationHybrid silicon wafer and method for manufacturing same
US8252422Jul 8, 2010Aug 28, 2012Jx Nippon Mining & Metals CorporationHybrid silicon wafer and method of producing the same
US8647747 *Jul 8, 2010Feb 11, 2014Jx Nippon Mining & Metals CorporationHybrid silicon wafer and method of producing the same
US20050130384 *Nov 12, 2004Jun 16, 2005Hynix Semiconductor Inc.Method for manufacturing resistor of a semiconductor device
US20110123795 *Jun 23, 2009May 26, 2011Jx Nippon Mining & Metals CorporationHybrid Silicon Wafer and Method for Manufacturing Same
Classifications
U.S. Classification438/677, 438/384, 257/E21.004, 438/684
International ClassificationH01L27/04, H01L21/205, H01L21/822, H01L21/28, H01L21/02
Cooperative ClassificationH01L28/20
European ClassificationH01L28/20
Legal Events
DateCodeEventDescription
Jun 6, 1995CCCertificate of correction
Jul 6, 1998FPAYFee payment
Year of fee payment: 4
Jun 20, 2002FPAYFee payment
Year of fee payment: 8
Jun 23, 2006FPAYFee payment
Year of fee payment: 12