Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS5394405 A
Publication typeGrant
Application numberUS 07/873,131
Publication dateFeb 28, 1995
Filing dateApr 24, 1992
Priority dateApr 24, 1992
Fee statusLapsed
Publication number07873131, 873131, US 5394405 A, US 5394405A, US-A-5394405, US5394405 A, US5394405A
InventorsJacob Savir
Original AssigneeInternational Business Machines Corporation
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Universal weight generator
US 5394405 A
Abstract
A cascaded arrangement of alternating AND gates and Exclusive-OR gates is employed in conjunction with an output from a pseudo-random signal generator to produce a weighted random pattern binary sequence which is granularly controllable in terms of user selected probabilities and for which the granularity level is readily controlled through the selection of a desirable number of cascaded stages.
Images(1)
Previous page
Next page
Claims(1)
The invention claimed is:
1. A circuit for generating a controllably weighted binary sequence, said circuit comprising:
means for generating a first plurality, said first plurality being N, of pseudo-random binary signal sequences; and
a second plurality, said second plurality also being N, of logic circuit stages, wherein each of said stages receives one of said binary sequences from said generating means, and wherein each of said stages also receives a specifiable weighting control signal, said stages being cascaded so that the output of each stage is supplied as input to its subsequent stage; and
wherein each stage includes conjunctive circuit means having as input said preceding stage output and one of said pseudo-random binary signal sequences, with the output of said conjunctive circuit means being supplied to conditional inverter circuit means which also has an input said specifiable weighing control signal and whose output is supplied to the conjunctive circuit means in said subsequent stage.
Description

The present invention is generally directed to random pattern testing for digital integrated circuit chip devices and systems. More particularly, the present invention is directed to a mechanism for producing weighted random bit patterns.

In the paper by J. A. Wacukauski et al, "A Method for Generating Weighted Random Test Patterns" appearing in the March 1989 issue of the IBM Journal of Research and Development (Vol. 33, No. 2) the desirability of employing weighted random test patterns is demonstrated. In particular, FIG. 4 from this paper illustrates a hardware implementation of a weight generator. However, as pointed out on page 156 of the article, the weighting scheme shown is limited in that the design produces weight factors of only 1,3,7 and 15. It is seen that the desired weighted pseudo-random value is produced from a sequence of tapped output signal lines originating from a linear feedback shift register (LFSR). The LFSR signals at the latch outputs are well understood to have pseudo-random characteristics. More particularly, it is known to connect the latch outputs in the LFSR in a feedback arrangement so as to implement maximally long state sequences before repetitions are encountered. In the embodiment shown, output signals from latches L are supplied to a cascaded sequence of AND gates. This cascaded sequence can produce sequences with weight factors 1/2, 1/4, 1/8 and 1/16. However, in the present invention this limitation to certain discrete weighting factor is eliminated.

In effect the cascaded AND gates sequence provides a mechanism for controlling the probabilities for the occurrence of zeroes and ones in the test sequence. By supplying a plurality of these signals to a multiplexer (one out of four circuits in the above paper) one can produce an output sequence whose weighting factor can be chosen from a small set of discrete values. However the degree of resolution in achievable probability selection is limited. Nonetheless, the level sensitive scan design (LSSD) methodology is particularly useful when it is capable of being supplied with granular weighted test quantities. Thus, it is desirable to be able to more precisely control the probabilities associated with the zeroes and ones in an output test sequence. However, conventional weight generators are not capable of providing a universal set of weighting factors. Thus, while the circuit shown in FIG. 4 of the above cited paper by Wacukauski et al is capable of producing an output sequence with a weighting factor of 1/8, the circuit is not capable of effectuating a weighting factor of 0.625, for example.

It is thus seen that it is desirable to employ weight generators for producing weighted test patterns for circuit testing wherein the generation of a highly granular set of weighting factors is made available.

SUMMARY OF THE INVENTION

In accordance with a preferred embodiment of the present invention a pseudo-random sequence generator provides a plurality of pseudo-random binary signal sequences to a staged weight control logic means. The weight control logic means preferably comprises a plurality of stages each of which includes an AND gate and and Exclusive-OR gate (XOR gate). These gates are arranged in alternating order with an AND gate and Exclusive-OR gate in each stage and with each stage supplying a signal to a subsequent stage. The circuit is similar to conventional cascaded AND gates for generating weighted random pattern sequences. However, interposed between each AND gate is an Exclusive-OR gate which is controlled by a weight control signal. Through selection of the weight control signals supplied to the Exclusive OR gates it thus becomes possible to generate all possible weights of the form i/2N for all values of i ranging from 0 through 2N. The resulting universal weight generator has a cascade structure and is readily expandable by the addition of any number of cascaded stages. The resulting circuit is useful in any weighted random pattern architecture that requires a serial input of weighted pseudo-random bits.

Accordingly, it is an object of the present invention to provide a mechanism for weighted random test pattern generation.

It is also an object of the present invention to provide a mechanism in which weighting factors are universally controllable and are not limited to a small set of integer multiples of 2-N.

It is yet another object of the present invention to improve test fault coverage in integrated circuit devices.

It is a still further object of the present invention to provide universal weight factor generation mechanisms requiring a minimal number of additional circuit components, but yet which is flexible and is easily implementable in terms of known weighted random pattern circuits and methods.

Lastly, but not limited hereto, it is an object of the present invention to increase the range of applicability of integrated circuit testing based upon weighted random pattern methods.

DESCRIPTION OF THE DRAWINGS

The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of practice, together with the further objects and advantages thereof, may best be understood by reference to the following description taken in connection with the accompanying drawings in which:

FIG. 1 illustrates, in block diagram form, the overall structure of the present invention; and

FIG. 2 illustrates in detail the staged structure of the staged weight control logic mechanism of the present invention particularly showing the AND and Exclusive-OR gates in each stage.

DETAILED DESCRIPTION OF THE INVENTION

One of the very desirable ways of testing integrated circuit chip devices and systems is through the insertion of a weighted random pattern test signal at various primary input points. The invention shown in FIG. 1 provides a structure for generating such a test signal. In particular, in FIG. 1 there is shown pseudo-random sequence generator (PRSG) 10. This generator preferably comprises a linear feedback shift register. Such devices configured with feedback arrangements to implement multiplication of polynomial elements in a Galois field, are typically employed to produce sequences of states which are representative of random binary sequences. However, it is noted that pseudo-random sequence generator 10 might also comprise a cellular array or any other finite state machine whose state sequences provide a sufficient degree of pseudo-randomness. Typically, sequence generator 10 has a large plurality of stages. However, for purposes of the present invention, it is sufficient to employ only a plurality, say N, of these signal lines. The signal lines are preferably the output lines of widely spaced latches in an LFSR. These N pseudo-random binary sequences are supplied to staged weight control logic mechanism 20 which receives a plurality N+1, of weight control signals. These weight control signals which have not heretofore been present in weighted random pattern generation devices. Instead, such devices have employed multiplexors (MUX units) to select inputs from a small subset of possible outputs which exhibit different weight factors. Now these weight control lines provide the control mechanism for selecting the appropriate weight factor. The output from control mechanism 20 is preferably supplied to a scan string such as one employed in level sensitive scan design (LSSD) circuit methodology.

FIG. 2 provides a more detailed description of weight control logic mechanism 20. In particular, it is seen that weight control mechanism 20 comprises a plurality of cascaded stages 21a, 21b, . . . , 21z labeled in FIG. 2 as stage 0, stage 1 and stage N. In general, N+1 is less than or equal to the number of PRSG signal lines employed. Preferably however, the number of steps, M, in the PRSG is made greater than N. Here there is an inherent design tradeoff between the desire to make M as large as possible to provide uncorrelated input signals and to desire to make M small to preserve chip circuit space. However, it should be kept in mind that if pseudo-random sequence generator 10 comprises a linear feedback shift register, it is preferable that N+1 is significantly less than the number of latches in the shift register.

Each stage includes conjunctive circuit means 22a, 22b or 22z whose output is supplied directly to an Exclusive-OR gate, (23a, 23b or 23z, respectively). Each AND gate receives a control signal, c0 through cN, which acts as a weight control factor. It is the values of zeroes and ones which are assigned to control lines c0 through cN which determine the weighting factor to be applied to the pseudo-random binary sequence emanating from sequence generator 10.

If c0, c1, c2, and c3 are the control signals and W is the generated weight, then W is determined by the central signals as follows for the case where N=3:

______________________________________c0    c1            c2      c3                             W______________________________________0          0     0            0   00          0     0            1   10          0     1            --  1/2--         1     --           0   1/4--         1     --           1   3/41          0     0            0   1/81          0     0            1   7/81          0     1            0   3/81          0     1            1   5/8______________________________________

The (-) is a "don't care" condition. Thus, there are two control patterns that generate a weight of 1/2: 0010, and 0011. There are four control patterns that generate a weight of 1/4: 0100, 0110, 1100, 1110. Similarly, there are four control patterns that generate a weight of 3/4: 0101, 0111, 1101, and 1111.

The control signals applied to Exclusive-OR gates 23a, 23b through 23z act as conditional inverting signals. It is traditional to think of the Exclusive-OR gate as a normal OR gate in which the possibility of both inputs being true precludes a true output. That is, the Exclusive-OR gate is normally thought of as implementing the function "either or but not both". However, in the present context, the Exclusive-OR gates employed are better understood to operate as conditional inverting circuits. That is when any of the control signals ci is a 0, the output of the corresponding AND gate is allowed to pass through unaltered. However, if any of the control signals are turned on, the corresponding Exclusive-OR gate implements an inverting function. Thus, the Exclusive-OR gate can also be considered to be a conditional inverter, the inversion being conditioned upon the value of the control line signal. In this way the inversion of selected bits along the cascaded chain can be made to affect the probabilities at each and every stage.

Thus in each stage (except the first) there is an AND gate which receives an input from the previous stage and a pseudo-random binary signal Si from sequence generator 10. The output of the AND gate in each stage is supplied to an Exclusive-OR gate (conditional inverter) (in each stage) which is controlled by a weight control signal whose value is determined by the tester and/or test programs being run. However, in the first stage the AND gate receives and maybe set up to receive a control signal, c0.

In the design provided above, there may be provided any number of stages, the number of stages only being limited by the number of latches in the LFSR implementation of the PRSG. Also, as indicated above, the number of control signals N+1 is preferably much less than or equal to the number of stages in PRSG 10.

While the circuit illustrated in FIG. 2 in each stage indicates that each stage includes an AND gate and an Exclusive-OR gate, it is also possible to combine these two gates into a combinatorial logic circuit which has only two levels rather than the implicitly three level circuit shown in FIG. 2. In particular, it is noted that the Exclusive-OR gate is typically implementable only in the format a two-level combinatorial circuit. Thus, with the inclusion of the AND gate, the overall logic circuit in each stage includes three levels. It is possible, if desired for purposes of speed and circuit count, to reduce the combinatorial logic to a two-level circuit. However, this two-level circuit requires true and complementary forms of all inputs to each stage. This is not a problem for signals from sequence generator 10 or from circuits which provide weight control signals ci. However, the necessity of providing the negative or complement form for the input to the AND gate from the previous stage poses a requirement that the previous stage generate either the true or complemented output forms in alternating stages. However, at the expense of increasing the number of circuit components this is a possible objective in those circumstances where it is desirable to be able to generate the weighted random pattern as quickly as possible.

For example, if Zi+1 is the output from the XOR gate of stage i and Zi is the input to the AND gate of stage i, then the relationship between these quantities is representable by the following Boolean equation which is manipulated below as shown to illustrate a two-level circuit embodiment having a 3-input OR gate fed by three AND gates, one of these AND gates having three inputs and the other two AND gates having only two inputs each: ##EQU1##

One of the significant advantages of the circuit of the present invention is that its design readily permits extension to any degree of granularity (as measured by 2N) desired, simply by increasing the number of cascaded stages.

While the invention has been described in detail herein in accordance with certain preferred embodiments thereof, many modifications and changes therein may be effected by those skilled in the art. Accordingly, it is intended by the appended claims to cover all such modifications and changes as fall within the true spirit and scope of the invention.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US3719885 *Dec 13, 1971Mar 6, 1973IbmStatistical logic test system having a weighted random test pattern generator
US4688223 *Jun 24, 1985Aug 18, 1987International Business Machines CorporationWeighted random pattern testing apparatus and method
US4801870 *Feb 1, 1988Jan 31, 1989International Business Machines CorporationWeighted random pattern testing apparatus and method
US4862460 *Oct 14, 1986Aug 29, 1989Hitachi, Ltd.Test pattern generator
US4959832 *Dec 9, 1988Sep 25, 1990International Business MachinesParallel pseudorandom pattern generator with varying phase shift
US5043988 *Aug 25, 1989Aug 27, 1991McncMethod and apparatus for high precision weighted random pattern generation
US5239262 *Feb 21, 1992Aug 24, 1993International Business Machines CorporationIntegrated circuit chip with built-in self-test for logic fault detection
Non-Patent Citations
Reference
1 *A Method for Generating Weighted Random Test Patterns by J. A. Waicukauski et al., IBM Journal of Research and Development, vol. 33, No. 2, Mar. 1989, p. 149.
2 *Cellular Automata Circuits for Built In Self Test by P. D. Hortensius et al, IBM Journal of Research and Development, vol. 34 No. 2/3, Mar./May 1990 p. 389.
3Cellular Automata Circuits for Built-In Self-Test by P. D. Hortensius et al, IBM Journal of Research and Development, vol. 34 No. 2/3, Mar./May 1990 p. 389.
4 *Fixed Bias an Variable Bias Random Pattern Generator by A. L. Herman, IBM Technical Disclosure Bulletin, vol. 27, No. 1B, p. 468.
5Fixed-Bias an Variable-Bias Random Pattern Generator by A. L. Herman, IBM Technical Disclosure Bulletin, vol. 27, No. 1B, p. 468.
6 *Hardware Based Weighted Random Pattern Generation for Boundary Scan by F. Brglez et al., IEEE, Paper 13.3, 1989, p. 264.
7Hardware-Based Weighted Random Pattern Generation for Boundary Scan by F. Brglez et al., IEEE, Paper 13.3, 1989, p. 264.
8 *Interfacing to Boundary Scan Chips for System Level Bit by J. Turino, IEEE, 1989, p. 310.
9 *Multiple Distributions for Biased Random Test Patterns by H. Wunderlich, IEEE Transactions on Computer Aided Design, vol. 9, No. 6, Jun. 1990, p. 584.
10Multiple Distributions for Biased Random Test Patterns by H. Wunderlich, IEEE Transactions on Computer-Aided Design, vol. 9, No. 6, Jun. 1990, p. 584.
11 *Random Pattern Testing of LSSD Logic Devices by Multiple Sets of Weights by E. B. Eichelberger et al., IBM Technical Disclosure Bulletin, vol. 31, No. 8, Jan. 1989, p. 467.
12 *The Weighted Random Test Pattern Generator by H. D. Schnurmann et al., IEEE Transactions on Computers, vol. C 24, No. 7, Jul. 1975, p. 695.
13The Weighted Random Test-Pattern Generator by H. D. Schnurmann et al., IEEE Transactions on Computers, vol. C-24, No. 7, Jul. 1975, p. 695.
14 *Weight Random Pattern Geenration for Self Test by M. C. Noecker, IBM Technical Disclosure Bulletin, vol. 32, No. 10A, Mar. 1990, p. 140.
15Weight Random Pattern Geenration for Self-Test by M. C. Noecker, IBM Technical Disclosure Bulletin, vol. 32, No. 10A, Mar. 1990, p. 140.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US5612963 *Jun 7, 1995Mar 18, 1997International Business Machines CorporationHybrid pattern self-testing of integrated circuits
US5737360 *Jun 19, 1995Apr 7, 1998International Business Machines, Corp.System employing continuous-time dissipative pseudorandom dynamics for communications and measurement
US5745522 *Nov 9, 1995Apr 28, 1998General Instrument Corporation Of DelawareRandomizer for byte-wise scrambling of data
US5889796 *Oct 17, 1996Mar 30, 1999Maxtor CorporationMethod of insuring data integrity with a data randomizer
US5983380 *Sep 16, 1997Nov 9, 1999International Business Machines CorporationWeighted random pattern built-in self-test
US6052817 *Dec 30, 1998Apr 18, 2000Maxtor CorporationData storage system including data randomizer responsive to address of selected data storage location
US6097889 *Jun 23, 1997Aug 1, 2000Motorola, Inc.Signal processing apparatus with stages in a signal path operating as LFSR of alternable type and method for processing signals
US6327687Jul 20, 2000Dec 4, 2001Janusz RajskiTest pattern compression for an integrated circuit test environment
US6339781 *May 17, 1999Jan 15, 2002Oki Electric Industry Co., Ltd.M-sequence generator and PN code generator with mask table for obtaining arbitrary phase shift
US6353842Jul 20, 2000Mar 5, 2002Janusz RajskiMethod for synthesizing linear finite state machines
US6430586 *Jun 8, 1999Aug 6, 2002International Business Machines CorporationControllable bit stream generator
US6457147Jun 8, 1999Sep 24, 2002International Business Machines CorporationMethod and system for run-time logic verification of operations in digital systems in response to a plurality of parameters
US6539409Sep 18, 2001Mar 25, 2003Janusz RajskiMethod for synthesizing linear finite state machines
US6543020Sep 4, 2001Apr 1, 2003Janusz RajskiTest pattern compression for an integrated circuit test environment
US6557129Jul 20, 2000Apr 29, 2003Janusz RajskiMethod and apparatus for selectively compacting test responses
US6590929Jun 8, 1999Jul 8, 2003International Business Machines CorporationMethod and system for run-time logic verification of operations in digital systems
US6662327May 13, 1999Dec 9, 2003Janusz RajskiMethod for clustered test pattern generation
US6667665Jul 29, 2002Dec 23, 2003Infioneon Technologies AgRandom number generator
US6684358Nov 15, 2000Jan 27, 2004Janusz RajskiDecompressor/PRPG for applying pseudo-random and deterministic test patterns
US6708192Jan 16, 2003Mar 16, 2004Janusz RajskiMethod for synthesizing linear finite state machines
US6724805Nov 15, 2000Apr 20, 2004Massachusetts Institute Of TechnologyNonlinear dynamic system for spread spectrum code generation and acquisition
US6816876Jan 29, 2001Nov 9, 2004Infineon Technologies AgApparatus and method for modifying an M-sequence with arbitrary phase shift
US6829740Jan 29, 2003Dec 7, 2004Janusz RajskiMethod and apparatus for selectively compacting test responses
US6874109Nov 15, 2000Mar 29, 2005Janusz RajskiPhase shifter with reduced linear dependency
US6983407Jun 11, 2003Jan 3, 2006International Business Machines CorporationRandom pattern weight control by pseudo random bit pattern generator initialization
US7082449 *May 3, 2002Jul 25, 2006Sun Microsystems, Inc.Method and apparatus for generating pseudo-random numbers
US7093175Dec 15, 2003Aug 15, 2006Janusz RajskiDecompressor/PRPG for applying pseudo-random and deterministic test patterns
US7111209Jan 31, 2003Sep 19, 2006Janusz RajskiTest pattern compression for an integrated circuit test environment
US7209867Oct 15, 2003Apr 24, 2007Massachusetts Institute Of TechnologyAnalog continuous time statistical processing
US7260591Feb 17, 2004Aug 21, 2007Janusz RajskiMethod for synthesizing linear finite state machines
US7263641Aug 3, 2004Aug 28, 2007Janusz RajskiPhase shifter with reduced linear dependency
US7478296Jan 29, 2003Jan 13, 2009Janusz RajskiContinuous application and decompression of test patterns to a circuit-under-test
US7493540Jul 20, 2000Feb 17, 2009Jansuz RajskiContinuous application and decompression of test patterns to a circuit-under-test
US7500163Oct 25, 2004Mar 3, 2009Janusz RajskiMethod and apparatus for selectively compacting test responses
US7506232Aug 11, 2006Mar 17, 2009Janusz RajskiDecompressor/PRPG for applying pseudo-random and deterministic test patterns
US7509546Sep 18, 2006Mar 24, 2009Janusz RajskiTest pattern compression for an integrated circuit test environment
US7523372Aug 27, 2007Apr 21, 2009Janusz RajskiPhase shifter with reduced linear dependency
US7653851Mar 26, 2009Jan 26, 2010Janusz RajskiPhase shifter with reduced linear dependency
US7805649Mar 2, 2009Sep 28, 2010Mentor Graphics CorporationMethod and apparatus for selectively compacting test responses
US7805651Dec 8, 2009Sep 28, 2010Mentor Graphics CorporationPhase shifter with reduced linear dependency
US7865794Mar 12, 2009Jan 4, 2011Mentor Graphics CorporationDecompressor/PRPG for applying pseudo-random and deterministic test patterns
US7877656Jan 13, 2009Jan 25, 2011Mentor Graphics CorporationContinuous application and decompression of test patterns to a circuit-under-test
US7900104Mar 17, 2009Mar 1, 2011Mentor Graphics CorporationTest pattern compression for an integrated circuit test environment
US8024387Aug 20, 2007Sep 20, 2011Mentor Graphics CorporationMethod for synthesizing linear finite state machines
US8108743Sep 27, 2010Jan 31, 2012Mentor Graphics CorporationMethod and apparatus for selectively compacting test responses
US8533547Jan 25, 2011Sep 10, 2013Mentor Graphics CorporationContinuous application and decompression of test patterns and selective compaction of test responses
EP2128763A1Nov 15, 2000Dec 2, 2009Mentor Graphics CorporationContinuous application and decompression of test patterns to a circuit-under-test
WO1998016919A1 *Oct 10, 1997Apr 23, 1998Maxtor CorpMethod of insuring data integrity with a data randomizer
WO2001055837A1 *Jan 29, 2001Aug 2, 2001Morphics Tech IncApparatus and method for modifying an m-sequence with arbitrary phase shift
Classifications
U.S. Classification714/739, 714/E11.175, 708/250
International ClassificationG01R31/3181, G06F11/277, G01R31/3183, G06F7/58
Cooperative ClassificationG06F7/582, G06F11/277, G01R31/31813, G01R31/318385
European ClassificationG06F7/58P, G01R31/3183R, G06F11/277, G01R31/3181G
Legal Events
DateCodeEventDescription
Apr 29, 2003FPExpired due to failure to pay maintenance fee
Effective date: 20030228
Feb 28, 2003LAPSLapse for failure to pay maintenance fees
Sep 17, 2002REMIMaintenance fee reminder mailed
Jun 19, 1998FPAYFee payment
Year of fee payment: 4
Apr 24, 1992ASAssignment
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:SAVIR, JACOB;REEL/FRAME:006110/0710
Effective date: 19920417