|Publication number||US5397947 A|
|Application number||US 07/967,415|
|Publication date||Mar 14, 1995|
|Filing date||Oct 28, 1992|
|Priority date||Oct 28, 1992|
|Publication number||07967415, 967415, US 5397947 A, US 5397947A, US-A-5397947, US5397947 A, US5397947A|
|Original Assignee||Samsung Electronics Co., Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (12), Non-Patent Citations (6), Referenced by (4), Classifications (9), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention relates to clipper and rectifying circuitry useful, for example, in signal rectification and, more particularly, to clipper and rectifying circuitry suitable for signals the amplitudes of which may be only fractions of a volt.
A clipper circuit supplies an output signal that, over a prescribed range of an input signal supplied thereto, responds linearly to that input signal. As the input signal swings beyond a boundary of that prescribed range, however, the output signal of the clipper circuit does not change from its value at the boundary. The use of diodes in clipper circuitry is well known. Half-wave and full-wave rectifier circuits are particular examples of clipper circuitry using diodes, which examples are familiar to persons skilled in the electronics art.
Rectifying circuits are generally capable of wide bandwidth operation and are unconditionally stable. However, the use of diodes is problematic when it is necessary and/or desirable to rectify, or otherwise clip, AC signals whose amplitude may be a fraction of a volt since diodes have a forward voltage drop (VF) of approximately 0.6 volt which must be exceeded before they conduct. Also, diodes suffer the disadvantage of being highly non-linear for AC input signal levels near the "knee" of the diode characteristic curve. This limits the usefulness of clipper and rectifying circuits using diodes to relatively high amplitude level signals of relatively limited dynamic range. Therefore, where it is required to rectify an AC signal which may range from a few millivolts to a few volts the diode circuits discussed above, which are also referred to as "feed forward" type circuits, are not suitable.
To overcome the problem with "feed forward" clipper (e.g., diode rectifying) circuits, rectifier or absolute value circuits capable of linear operation down to small AC signal voltages generally employ feedback techniques to reduce the effect of diode nonlinearities. An example of such a circuit is shown in U.S. Pat. No. 4,564,814 issued Jan. 14, 1986 to Miura et alii and titled FULL-WAVE RECTIFIER USING AN OPERATIONAL AMPLIFIER.
Referring specifically to FIGS. 3 and 4 of the Miura et alii reference, there is shown an operational amplifier combined with a transistor and two resistors to form a full-wave rectifier. A problem with the showing in FIGS. 3 and 4 of the Miura et alii reference is that the mechanism for rectifying the positive-going portion of the AC signal is not similar to the mechanism for rectifying the negative-going portion of the AC signal. Consequently, such a circuit, although simple, will have a response which will not be uniform or symmetrical for positive and negative-going portions of the AC input signal, particularly at high frequencies.
Another approach to obtain full-wave rectification, described in U.S. Pat. No. 4,523,105 issued Jun. 11, 1985 to Jose et alii and entitled FULL-WAVE RECTIFIER CIRCUIT FOR SMALL SIGNALS includes an amplifier with a relatively complex degenerative voltage feedback arrangement to produce bidirectional output currents. In Jose et alii additional inversion of a portion of the bidirectional currents is required before the output currents can be combined to produce full-wave rectification. Thus, the mechanism for rectifying the positive-going half cycle is not the same as for the negative-going half cycle.
Therefore, there is still a need for a simple clipper circuit which has the stability and bandwidth advantages of a feedforward clipper, which has the dynamic range and linearity advantages of a feedback clipper, and which is easily reconnected to respond either to positive portions of an input signal or to negative portions of that input signal with the same predictable gain in either connection.
Furthermore, there is a need for circuits which are suitable for rectifying AC signals whose amplitudes may be a fraction of a volt and which can then use the rectified (or detected) signal to produce a direct current (DC) control voltage for controlling, for example, the gain of an amplifier.
A circuit embodying the invention includes a differential-input amplifier having a non-inverting input node, an inverting input node, and an output node. A feedback transistor having first and second electrodes defining the ends of a main conduction path and a control electrode has its control electrode connected to the amplifier output node and has its first electrode connected to the inverting terminal for providing degenerative current feedback between the output node and the inverting input node. A resistive element having a given ohmic value is connected between the inverting input node and an input terminal for conducting a current supplied via the main conduction path of the feedback transistor, the second electrode of which defines a current output terminal of the circuit.
Owing to the degenerative feedback, the voltage at the inverting input node tends to be very nearly equal to the potential at the non-inverting input node. This feature enables two alternative ways of detecting the polarity and the amplitude of a signal applied between the input terminal and the non-inverting input node. In response to the application of a reference potential to the non-inverting input node and an AC input signal varying about the reference potential to the input terminal, during the negative half cycle of the AC signal a current of one polarity flows through the second electrode of the feedback transistor and through the first electrode of the feedback transistor and the resistive element connected thereto, but during the positive half cycle no current flows. In response to the application of the reference potential to the input terminal and the AC input signal to the non-inverting input node, during the positive half cycle a current of the same one polarity flows through the second electrode of the feedback transistor and through the first electrode of the feedback transistor and the resistive element connected thereto, but during the negative half cycle no current flows. In both instances the amplitude of the current is a function of the value of the AC signal divided by the ohmic value of the resistive element.
Thus, a circuit embodying the invention is suitable for use as a half-wave rectifier. For one input signal condition (i.e., when the reference potential is applied to the non-inverting input node and an AC input signal varying about the reference potential is applied to the input terminal), the circuit functions as a negative half-wave rectifier and produces a current of a first polarity at the current output terminal. When the input signal conditions are reversed (i.e., the reference potential is applied to the input terminal and the AC signal is applied to the non-inverting input node), the circuit functions as a positive half-wave rectifier producing a current of the same first polarity at the current output terminal.
Therefore, first and second circuits embodying the invention may be interconnected to form a full-wave rectifier. In this configuration the input terminal of the first circuit and the non-inverting input node of the second circuit are connected to a reference potential, the non-inverting input node of the first circuit and the input terminal of the second circuit are connected to an AC signal varying about the reference potential, and the current output terminals of the first and second circuits are connected in common to produce a full-wave rectified output current proportional to the absolute value of the input AC signal.
In a particular embodiment of the invention, the differential-input amplifier includes first and second transistors, with each transistor, like the feedback transistor, having first and second electrodes defining the ends of a conduction path and a control electrode. The first and second transistors are arranged to form a differential-input amplifier with their first electrodes being connected in common to a first node and with a current source being connected between the first node and a first power terminal. The control electrodes of the first and second transistors define the non-inverting input node and the inverting node, respectively, of the differential-input amplifier and the second electrode of the second transistor defines the output node of the differential-input amplifier. The feedback transistor is connected at its control electrode to the second electrode of the second transistor (which defines the output of the differential amplifier) and its first electrode is connected to the control electrode of the second transistor at the inverting node for providing degenerative feedback therebetween and for supplying current to the resistive element connected between the inverting input node and the input terminal.
In response to the application of a reference voltage to one of the non-inverting input node and the input terminal and to the application of an AC signal which goes positive and negative about the reference voltage to the other one of the non-inverting input node and the input terminal, a unidirectional current flows through the conduction path of the feedback transistor and the resistive element which is proportional to the amplitude of the AC signal divided by the ohmic value of the resistive element.
In a particular embodiment of the invention, the first, second, and feedback transistors are bipolar transistors of the same conductivity type. The first and second transistors are connected in an emitter-coupled differential amplifier; and the feedback transistor has its base-to-emitter path connected across the collector-to-base of the second transistor for providing feedback from the collector (output) of the second transistor to the base (inverting input) of the second transistor.
As is the general case with a bipolar transistor, the feedback transistor is a current amplifier, responding to an input signal current of first polarity flowing into its base (input), to supply a first output signal current of the first polarity from its emitter (noninverting output), and to supply a second output signal current of a second polarity opposite to the first polarity from its collector (inverting output). The feedback transistor functions as a feedback amplifier. It completes a degenerative feedback loop by feeding its collector current back to the base of the first transistor, at the input of the emitter-coupled differential-input amplifier, the collector current of the feedback transistor being an amplified response to a signal current supplied to its base from the collector of the second transistor, at the output of the emitter-coupled differential-input amplifier.
In certain embodiments of the invention, the unidirectional rectified current flowing in the second electrode of the feedback transistor may be converted into a rectified output voltage the amplitude of which is proportional to the absolute value of the AC signal. The rectified output voltage is then applied to a peak detector to produce an output control voltage for controlling the gain of a variable gain amplifier.
FIG. 1 is a schematic diagram of an amplitude peak detector preceded in cascade connection by a full-wave rectifier embodying the invention.
FIG. 2A through 2D are waveform diagrams of signals, sharing a common time scale, associated with the circuit of FIG. 1.
FIG. 3 is block diagram of a playback system for a video cassette recorder (VCR) of the VHS type, which playback system includes a full-wave rectifier embodying the invention.
FIG. 4 is a symbolic representation of a circuit embodying the invention.
FIG. 5 is a detailed schematic diagram of a circuit embodying the invention.
FIG. 1 is a schematic diagram of a gated detection circuit 10 designed for use in a video cassette recorder (VCR) having playback electronics of the type shown in FIG. 3. More particularly, the gated detection circuit 10 of FIG. 1 is designed for use in an automatic color control (ACC) loop for controlling the gain of a variable gain amplifier 301, which amplifies color-under signal recovered during playback from a previously recorded video tape. The gated detection circuit 10 is designed to detect the "BURST" portion of a color-under signal shown in the waveform of FIG. 2A and to produce a DC control voltage for comparison to a fixed DC level. Deriving the ACC signal from the color-under signal taken directly from the output of the variable gain amplifier 301, rather than from the upconverted response to that signal from the upconverter 325, is another invention claimed by the inventor in a concurrently filed application entitled CHROMA BURST DETECTION SYSTEM.
In FIG. 1 the color-under signal, the amplitude and polarity of the "BURST" portion of which is to be detected, is represented as an alternating current (AC) signal VIN produced by a signal source 3 connected between terminals 19 and 23. A reference voltage VREF1, which is preferably a direct current (DC) voltage, is applied between terminals 21 and 17. VREF1 may be assumed to have a value one-half that of an operating potential VCC, which potential VCC may be+5 volts, for example.
The detection circuit 10 of FIG. 1 includes a detector 12 to detect and rectify a negative-going swing of the (AC) signal VIN ; a detector 14 to detect and rectify a positive-going swing of the (AC) signal VIN ; a current-to-voltage converter 16; a peak detector circuit 18; a gating and biasing circuit 20 for controlling the turn-on and turn-off of the rectifiers 12 and 14 and of the current-to-voltage converter 16; and an analog comparator 22.
The components of detector 12, which functions as a negative half-wave rectifier, are identified by reference characters followed by the letter "N". The components of detector 14, which functions as a positive half-wave rectifier, are identified by reference characters followed by the letter "P". Detector 12 includes NPN transistors Q1N and Q2N, which are in emitter-coupled differential amplifier connection. That is, the emitters of Q1N and Q2N are connected in common to a node 45N, the base of Q1N is connected to a "non-inverting" input node 11N, the base of Q2N is connected to an "inverting" input node 13N, the collector of Q1N is connected to a node 53N and the collector of Q2N is connected to a node 51N which defines the output (OAN) of the differential amplifier.
A current mirror amplifier (CMA) is connected to the collectors of Q1N and Q2N. The current mirror amplifier includes PNP transistors Q4N and Q5N. Transistors Q4N and Q5N have their emitters connected to a power terminal 15 to which the operating potential VCC is applied. The collector of Q5N is connected to node 51N. The collector and base of Q4N and the base of Q5N are connected to node 553N. This current mirror amplifier connection is such that the collector current supplied by the PNP transistor Q5N to the output node OAN is similar to the collector current demanded by the NPN transistor Q1N from the CMA input node 53N.
A selectively enabled, relatively constant current source 121N is connected between node 45N and ground. The current source 121N includes an NPN transistor Q18N having its collector connected to node 45N, its emitter connected to terminal 17 to which is applied ground potential, and its base connected to a terminal 201 to which is selectively applied a relatively constant bias voltage VB.
Unidirectional current feedback between output OAN at the collector of Q2N and the "inverting" input at the base of Q2N is provided by the common-collector-amplifier action of an NPN transistor Q3N having its base connected to the collector of Q2N and its emitter connected to the base of Q2N. The collector of Q3N is connected to a summing line 57.
An input resistor R1N is connected between terminal 13N and input terminal 7N. As discussed in detail below, terminal 7N, which defines one input terminal of the rectifier 12, is connected to terminal 19; and node 11N, which defines another input terminal of the rectifier, is connected to terminal 21.
The structure of positive-swing detector 14 is substantially the same as that of negative-swing detector 12. Positive swing detector 14 includes NPN transistors Q1P and Q2P which are in emitter-coupled differential amplifier connection. That is, the emitters of Q1P and Q2P are connected in common to a node 45P, the base of Q1P is connected to input node 11P, the base of Q2P is connected to an inverting input node 13P, the collector of Q2P is connected to node 51P defining the output OAP of the differential amplifier and the collector of Q1P is connected to node 53P.
A current mirror amplifier (CMA) is connected to the collectors of Q1P and Q2P. The CMA includes PNP transistors Q4P and Q5P. Q5P is connected at its emitter to power terminal 15 and at its collector to node 51P. The emitter of Q4P is connected to terminal 15; and its collector and the bases of Q4P and Q5P are connected to node 53P. This current mirror amplifier connection is such that the collector current supplied by the PNP transistor Q5P to the output node OAP is similar to the collector current demanded by the NPN transistor Q1P from the CMA input node 53N.
A selectively enabled relatively constant current source 121P is connected to node 45P. Current source 121P includes an NPN transistor Q18P having its collector connected to node 45P, its emitter connected to ground terminal 17 and a relatively constant bias voltage VB is selectively applied to the base of Q18P.
Unidirectional current feedback is provided between the output OAP at the collector of Q2P and the "inverting" input at the base of Q2P by the common-collector-amplifier action of an NPN transistor Q3P having its base connected to the collector of Q2P, its collector connected to the summing line 57, and its emitter connected to the base of Q2P. An input resistor R1P is connected between terminal 13P and terminal 7P. Terminal 7P which defines one input terminal of the rectifier 14 is connected to terminal 21, and node 11P which defines another input terminal of rectifier 14 is connected to terminal 19.
On the summing output line 57 the half-wave rectification current ION produced by negative-swing detector 12 is summed with the half-wave rectification current IOP produced by positive-swing detector 14 in an analog OR or "wired OR" operation. The resulting full-wave rectification current demand on the summing output line 57 is supplied from the input of a current mirror amplifier (CMA) of the type described by Wilson included in a current-to-voltage converter 16. This CMA includes a PNP transistor Q13 having its common-emitter forward current gain stabilized by emitter-to-base current feedback supplied by a component simpler CMA comprising PNP transistors Q11 and Q12 having their emitters connected to terminal 15. The base of Q11 and the base and collector of diode-connected transistor Q12 are connected at a node 162 to receive Q13 emitter current. The summing line 57 connects to the base of Q13 at a node 160, to which the collector of Q11 is connected to supply a negative feedback current proportional to the Q13 emitter current. The collector of Q13 is connected to a node 164 and produces an output current IC13, the amplitude of which is proportional to the full-wave rectification current demanded from the input of the current-to-voltage converter 16. A resistor R3 is connected between node 164 and terminal 165 to which is applied a potential VREF2. IC13 flows through resistor R3 into reference source VREF2. The voltage, VF, at node 164 is then equal to (IC13 ĚR3)+VREF2. In the discussion to follow it is assumed that VREF2 is the same as VREF1.
The peak detector 18 includes an NPN transistor Q14 connected as an emitter follower for positive-going signals, with its collector connected to terminal 15, its base to node 164 and its emitter to node 182. A storage capacitor C1 is connected between node 182 and ground terminal 17 having a value sufficient to hold the peak voltage (VP) at node 182 relatively constant over at least one horizontal line time interval. A discharging resistor R4 is connected in parallel with C1 between node 182 and ground. The value of R4 is selected to assure a slowly decreasing voltage across C1 when no signal is detected.
The output 182 of the peak detector 18 is applied to an input 225 of an analog comparator 22. The comparator 22 compares the output voltage Vpk of the peak detector circuit 18 against a reference voltage VREF3 to generate output voltages VO1 and VO2 exhibiting differential variation from each other. The comparator 22 includes NPN transistors Q15 and Q16 in emitter-coupled differential amplifier connection, having their emitters connected in common at node 221. A relatively constant current source 222 is connected between node 221 and ground potential. The base of Q15 is connected to terminal 182, and its collector is connected to an output terminal 224. The base of Q16 is connected to a node 226, and its collector is connected to an output terminal 228. A load resistor R20 is connected between terminal 224 and power terminal 15, and a load resistor R22 is connected between terminals 228 and 15. A biasing signal is applied to Q16 by the emitter-follower action of an NPN transistor Q17 connected at its collector to terminal 15 and at its emitter to node 226, to which the base of Q16 is connected. A reference voltage source 230 producing a reference voltage VREF3 is connected to the gate of Q17. VREF3 is typically greater than VREF2 and less than VCC . VREF3 typically sets the level at which the comparator 22 responds to the output of the peak detector. The output signals V01 and V02 at terminals 224 and 228 are applied to variable gain amplifier 301 shown in FIG. 3.
The bias voltage VB is produced by the potential divider comprising a resistor R5 connected between terminals 15 and 201 and a diode D1 connected between terminal 201 and ground. Diode D1 is poled to conduct current in the forward direction from terminal 201 to ground, whereby the bias voltage VB developed at terminal 201 is equal to the forward voltage drop, VF, of diode D1 at a particular current. Terminal 201 is connected to the bases of Q18N and Q18P and the voltage at terminal 201 sets the current level through these transistors.
Gating circuitry 20 includes means for controlling the generation and application of the bias voltage VB and means for selectively either clamping summing output node 164 to ground or letting it respond to the AC input signal. The gating circuit 20 includes a resistor R6 connected between terminals 15 and 203. An NPN transistor Q21 is connected at its base to node 203, at its collector to node 164, and at its emitter to ground terminal 17. An NPN transistor Q20 also has its base connected to terminal 203 and its emitter grounded; the collector of Q20 is connected to bias terminal 201. An NPN transistor Q22 has its collector connected to terminal 203 and its emitter grounded, and its base is connected to a gating terminal 207 to which is applied a source 205 of gating signals.
When the gating signal produced by source 205 is "high" (i.e. sufficiently high to drive transistor Q22 fully on) transistor Q22 is turned-on and clamps the bases of Q21 and Q20 at or close to ground. This turns off conduction through Q20 and Q21. Q20 being turned-off allows current to flow from VCC supply via R5 into diode D1, establishing a forward conduction voltage VB across diode D1, which voltage VB is applied to the bases of Q18N and Q18P. So biased, the negative-swing detector 12 and the positive-swing detector 14 are rendered operative. Concurrently, the turn-off of Q21 removes the clamp to ground applied to node 164 and enables the voltage at node 164 to develop a level proportional to the current produced at the joined outputs of the negative-swing detector 12 and the positive-swing detector 14. When enabled, the combination of the negative-swing detector 12, the positive-swing detector 14 and the current-to-voltage converter 16 functions as a full-wave rectifier; and the voltage output at node 164 will vary in accordance with the output signals produced by the swing detectors 12 and 14.
When the gating signal is "low" (at or close to zero volts) Q22 is turned-off. Current then flows via R6 into the base of Q21 turning-on conduction through the collector-to-emitter path of Q21 to clamp node 164 at or close to ground potential. Concurrently, current also flows via R6 into the base of Q20 turning-on conduction through the collector-to-emitter path of Q20 to clamp the bases of Q18N and Q18P at, or close, to ground potential. Conduction through Q18N and conduction through Q18P are turned-off, to disable the negative-swing detector 12 and the positive-swing detector 14. Concurrently, the turn-on of Q21 clamps node 164 to ground, preventing any current flow into the peak detector. Thus, when the gate source signal is "high" the full-wave rectifier is enabled and when the gate source signal is low, the full-wave rectifier is disabled.
The operation of the circuit of FIG. 1 will now be examined for the condition when the gating signal is "high" with transistors Q21 and Q20 turned-off. For this condition a voltage VB is applied to the bases of Q18N and Q18P. The swing detectors 12 and 14 are identical except for the application of the color-under signal VIN, the amplitude and polarity of the "BURST" portion of which is to be detected, being to their signal input terminals 13N and 11P, respectively, and for the reference voltage VREF1 being applied to their input terminals 11N and 13P, respectively. Since the DC bias condition and response of detector 14 is essentially identical to that of detector 12, the detailed description of their respective modes of operation will be offered with reference to FIG. 5, which shows a single detector redrawn without using either of the suffices "N" and "P".
In FIG. 5, switches S1 and S2 are used to indicate two signal conditions. For condition (1) input terminal 7 is connected to terminal 19 to which is applied the AC signal VIN and node 11 is connected to terminal 21 to which is applied VREF1. This condition corresponds to the operation of detector 12. For condition (2) input terminal 7 is connected to terminal 21 to which is applied VREF1 and node 11 is connected to terminal 19 to which is applied VIN. This condition corresponds to the operation of detector 14.
When VB is applied to the base of Q18, a relatively constant current IT flows via the collector-to-emitter path of Q18 from node 45 to ground. Assume that a voltage VREF1 which is a direct current (DC) voltage and which, for purpose of illustration is assumed to equal VCC /2, is applied to the base of Q1. Concurrently, assume that (VIN +VREF1), an AC signal VIN superposed on the DC level VREF1, is applied to terminal 7 and thence via resistor R1 to the base of Q2. Assuming that initially VIN is equal to zero, it may be assumed that VREF1 is initially applied to both the bases of the differential pair of transistors Q2N and Q1N. Assuming Q2N and Q1N to have similar operating characteristics it is evident that, for VIN =0, the emitter current IE1 of Q1N is equal to the emitter current IE2 of Q2N and that IT=IE1+ IE2. It may also be assumed that the collector current ICl of Q1 is equal to the collector current IC2 of Q2. Assuming Q4 and Q5 to be monolithic integrated-circuit transistors with similar geometries and similar operating characteristics, the collector current drawn by Q1 and flowing through Q4 will induce a like amplitude current to flow through Q5. Neglecting base currents, the collector current from Q4 is approximately equal to the collector current demanded by Q2 and the collector current from Q5 is equal to the collector current demanded by Q2. (In this specification, it is assumed that the forward current gain β of the transistors is relatively high and that base current can, to a first approximation, be ignored.)
Hence, for the condition of VIN=0 and for VREF1 applied to terminals 11 and 7, the bases of Q1 and Q2 are at VREF1, the emitter current through Q3 is (at most) equal to a small base current flowing through Q2 divided by the β of Q3. Hence, for VIN equal to zero, the output collector current I.sub. C3 of Q3 may be assumed to be essentially equal to zero. That is, the output current I0 to the summing line 57 as determined by IC3 is essentially equal to zero.
The above analysis applies for the DC bias conditions of detectors 12 and 14. Hence for VIN =0, the output currents ION of detector 12 and IOP of detector 14 are, at or close, to zero. The response of the circuit of FIG. 1 and in particular the operation of the detector circuits 12 and 14 will now be analyzed for the conditions wherein VIN goes negative relative to VREF1 and wherein VIN goes positive relative to VREF1.
Referring back to FIG. 5, first consider a condition (1) where the switch S1 applies VIn to terminal 7 and the switch S2 applies VREF1 to terminal 11, implementing detector circuit 12 operation.
When VIN goes negative with switches S1 and S2 set to condition (1)--i.e. the signal at terminal 7 goes negative relative to the signal at node 11--the voltage at the base of Q2 goes negative relative to the voltage at the base of Q1. The voltage at node 45 tends to remain unchanged, following (with a forward-conduction base-emitter junction voltage offset provided by Q1) the higher voltage VREF1 present at the base of Q1. The voltage at node 45 being held up tends to decrease the base-to-emitter voltage of Q2 and thus decrease conduction through Q2. However, concurrently, the current ICl demanded by Q1 from the node 51 increases, tending to increase the currents IB4 and IB5 flowing to node 53 from the bases of Q4 and Q5 and thence the current IC4 flowing to node 53 from the collector of Q4 until the ICl current demand is fulfilled. By current mirror action, the collector current IC5 supplied by Q5 increases together with the collector current IC4 supplied by Q4. Since conduction through Q2 is decreasing, the increasing IC5 current tends to flow as an increased IB3 current flow into the base of Q3. The increased IB3 current flow into the base of Q3 is multiplied by the (β+1) common-collector gain of Q3 in the current flowing from the emitter of Q3 into node 13. The emitter current of Q3 flows primarily through the resistor R1 to cause a voltage drop thereacross, which voltage drop increases sufficiently to overcome for the most part the tendency for the base-to-emitter voltage of Q2 to be reduced responsive to VIN at the terminal 7 going negative. Conduction through Q2 is increased, to divert such portion of the increased collector current IC4 supplied by Q4 from the base of Q3 as required to keep IB3 just large enough so the emitter current IE3 from Q3 maintains a voltage drop across R1 substantially equal to (VREF1 -VIN). That is, the effect of the current feedback to node 13 is that some of the current IE3 flows into the base of Q 2 and the current levels through Q1 and Q2 are readjusted such that the voltage at node 13 will be maintained at, or close to, the voltage at node 11.
This closed-loop analysis shows that, for node 11 at VREF1, when the signal at input terminal 7 tends to decrease the voltage at inverting node node 13, Q3 will provide sufficient feedback to maintain node 13 at or close to VREF1 by withdrawing current therefrom via resistor R1. For the condition of VREF1 applied to node 11 and for the AC signal varying negatively about VREF1, node 13 functions as a virtual AC ground and will tend to stay at VREF1.
Since Q3 can supply all the current needed at node 13 to maintain node 13 equal to VREF1, it is evident that as VIN applied to input terminal 7 goes negative, the current flowing through resistor R1 will equal (VREF1 -VIN)/R1, where R1 is the resistance of R1. Thus the current (I1) through R1 will increase linearly as the AC signal increases in the negative direction. It is also evident that the output current (IO) which is identical to IC3 of Q3 is essentially equal to the current I1 through R1, since the collector and emitter currents of a bipolar transistor are related in β: (β+1) ratio and the β of an NPN monolithic-integrated-circuit transistor is normally at least 30.
When VIN goes positive with switches S1 and S2 set to condition (1)--i.e. the signal at terminal 7 goes positive relative to the signal at node 11--a current tends to flow from terminal 7 via R1 into the base of Q2. Q2 now tends to conduct more than Q1 and to reduce conduction through Q1. The tendency towards reduced conduction through Q1 is accompanied by tendencies for reduced conduction through Q4 and through Q5 as well. At the same time, as the conduction through Q2 increases, it tends to pull more collector current from node 51 and to divert current from flowing into the base of Q3, thus tending to cut off conduction through Q3. Also, Q2 goes into saturated conduction, decreasing the voltage across the base-emitter junction of Q3 below the level to maintain that junction conducting. Therefore, as VIN at terminal 7 goes positive relative to VREF1 at terminal 11, conduction through Q3 is turned off; and no current demand is presented to the summing line 57 by Q3.
Thus, it has been shown that the negative-swing detector 12 produces an output current, ION, which increases linearly with VIN, when VIN goes negative relative to VREF1. Its output current, ION, has been shown to equal zero when VIN increases and goes positive relative to VREF1.
The operation of the positive-swing detector 14 is now explained referring again to FIG. 5, but with switches S1 and S2 set to a condition (2). That is, the switch S1 applies VREF1 to terminal 7 and the switch S2 applies VIN to the non-inverting node 11, implementing detector circuit 14 operation.
When VIN goes positive with switches S1 and S2 set to condition (2)--i.e., the potential at node 11 is more positive than the potential at terminal 7--the base of Q1 goes positive with respective to the base of Q2 tending to turn-off Q2. However, as the voltage on the base of Q1 increases, its collector current IC1 increases. This increased collector current is mirrored via Q4 and Q5 causing an increase in IC2 +IB3. Since Q2 tends towards being turned-off, the increased current tends to flow into the base of Q3, causing increases in the emitter current IE3 of Q3 into node 13 and in the collector current IC3 of Q3. The increased current into node 13 raises the voltage at the base of Q2 to a value which is approximately equal to the value of the potential VIN at node 11. Since node 13 is equal to VIN and since input terminal 7 is at VREF1, the current I1 flowing through R1 is equal to (VIN -VREF1)/R1. The current through R1 flows from the emitter of Q3, giving rise to an essentially equal collector current IC3.
When VIN goes negative with switches S1 and S2 set to condition (2)--i.e., the potential at node 11 is more negative than the potential at terminal 7--the base of Q1 goes negative relative to the base of Q2. Since conduction through Q1 decreases, the currents through Q4 and Q5 also decrease. Thus, as transistor Q2 conducts more current, it tends to withdraw more current from node 51, cutting off conduction through the collector-to-emitter path of Q3.
Therefore, analysis of the circuit of FIG. 5 indicates that Q3 supplies sufficient current to maintain the voltage at node 13 equal to the voltage at node 11. For the condition when the input terminal 7 goes negative and node 13 is held at VREF1, the current through R1 and Q3 is equal to (VREF1 -VIN)/R1. Similarly, when the input terminal is held at VREF1 and the potential at node 13 rises with VIN, the current flows in the same direction through R1 and Q3 and is equal to (VIN -VREF1)/R1. Thus, the positive-swing detector 14 of FIG. 1 has been shown to produce an output current IOP which increases linearly with VIN when VIN goes positive relative to VREF. The positive-swing detector 14 has been shown to produce an output current IOP which is equal to zero when VIN goes negative relative to VREF1. It should also be evident that detectors 12 and 14 can respond to very small signal differentials. Referring back to FIG. 1, on the summing output line 57, the half-wave rectification current ION produced by negative-swing detector 12 is summed with the half-wave rectification current IOP produced by positive-swing detector 14 in an analog OR or "wired OR" operation. The resulting full-wave rectification current demand on the summing output line 57 is supplied from the input of the current-to-voltage converter 16.
FIG. 4 represents in a still more general way than FIG. 5 either one of the swing detectors 12 and 14. The FIG. 4 circuit may be viewed more generally than being a rectifier, as being a clipper. The transistors Q1, Q2, Q4, Q5, and Q18 of the FIG. 5 circuit (when turned-on) together behave like an operational amplifier (op-amp) 401, as shown in the FIG. 4 clipper or swing detector. The base of Q1 corresponds to the op-amp 401 non-inverting (+) input, the base of Q2 corresponds to the op-amp 401 inverting (-) input, and the node 51 between the collectors of Q2 and Q5 corresponds to the output OA of the op-amp 401. The op-amp 401 is an operational transconductance amplifier (OTA) in the FIG. 5 embodiment of the clipper or swing detector. The node or terminal bearing the prefix "11" defines the non-inverting node or terminal (+) of the op-amp 401, which also is one of two input terminals of the FIG. 4 clipper or swing detector. The node or terminal bearing the prefix "13" defines the inverting (-) node (or terminal) of the op-amp 401.
In the FIG. 4 clipper or swing detector considered as a whole, the node or terminal bearing the prefix "11" is one of two input terminals thereto. The node 13 is an internal node which functions as a virtual ground. Resistor R1 connects between node 13 and a terminal bearing the prefix "7", which is the other input terminal of the FIG. 4 clipper or swing detector.
The op-amp 401 is provided degenerative feedback from its output OA to its inverting (-) input 13 by a feedback amplifier having an input connection from the output OA of the op-amp 401 and having a non-inverting output connection to node 13 with the resistor R1 as a load. The feedback amplifier has a further output connection to the output terminal of the FIG. 4 clipper or swing detector, shown in FIG. 4 as an inverting output connection (IO). The feedback amplifier is shown in FIG. 4 as a common-collector-amplifier or emitter-follower connection of Q3 with the resistor R1 as an emitter load and with the further output connection being from the collector of Q3 to the inverting output connection (IO) of the FIG. 4 clipper or swing detector.
The feedback amplifier provided by the bipolar transistor Q3 connected as a common-collector amplifier, with the resistor R1 as an emitter load, can be viewed as being a transresistance amplifier, with Q3 functioning as a current amplifying device for driving the resistor R1 as a current-to-voltage conversion element. However, a low-threshold-voltage field-effect transistor in common-drain-amplifier or source-follower connection may replace the bipolar transistor Q3. The difference in the collector currents of Q2 and Q5 charge to stray capacitance at the node OA to provide voltage to which the field-effect transistor is responsive as a transconductive amplifying device. If the op-amp 401 is a voltage amplifier rather than transconductance amplifier, either the bipolar transistor Q3 or a low-threshold-voltage field-effect transistor will function as a transconductive amplifying device cooperating with the resistor R1 as a load to form a voltage amplifier as feedback amplifier.
The FIG. 1 full-wave rectifier and detector circuitry is intended for inclusion in the playback electronics of a video cartridge recorder (VCR) of the VHS type; but, before describing such playback electronics, some background information about VHS recording is provided. In VHS recording, the luminance and chrominance information contained in a composite video signal are separated from each other. The chrominance information supplied for recording is mixed with a one of four phases of 4.21 MHz carrier in a down conversion that generates a color-under signal that comprises quadrature amplitude modulation (QAM) sidebands of a suppressed 629 kHz color-under carrier wave. The phasing of the 4.21 MHz carrier wave is selected on a line-by-line basis as determined by lines and fields of composite video signal, the selection signal being generated by decoding counts of the horizontal and vertical synchronizing pulses separated from the composite video signal. The luminance information is used to frequency-modulate a higher frequency luminance carrier wave. In the resulting FM signal the sync tips are at about 3.4 MHz; black level is at about 3.7 MHz; and white level is at about 4.4 MHz. This FM signal is added to the color-under sidebands as a bias frequency, and the resulting sum signal is pre-emphasized and used to record the video tape vertically scanned by the VCR type transport.
FIG. 3 shows the playback electronics for a video cartridge recorder (VCR) of the VHS type, which the FIG. 1 full-wave rectifier and detector circuitry is designed for inclusion in. When the video tape is played back, the color-under sidebands and the FM signal are separated from each other. A low-pass filter 309 recovers the color-under sidebands, which are supplied to a variable gain control amplifier 301. A high pass filter 311 recovers the FM signal, which an FM detector 313 of the pulse-counting type demodulates in order to reproduce luminance signal with accompanying horizontal and vertical synchronizing pulses.
An oscillator 315 supplies a 4.21 MHz carrier wave, the phasing of which is selected on a line-by-line basis in accordance with counts of lines and fields of composite video signal during playback also, but as obtained by counting horizontal and vertical synchronizing pulses separated from the regenerated luminance signal. More particularly, a horizontal sync separator 317 separates the horizontal synchronizing pulses from the FM detector 313 output signal for counting by a modulo-4 scan line counter 319, and a vertical sync separator 321 separates the vertical synchronizing pulses from the FM detector 313 output signal for counting by a modulo-2 field counter 323.
An up-converter 325 heterodynes the color-under sidebands from the variable gain control amplifier 301 with the one-of-four-phases 4.21 MHz carrier wave from the oscillator 315, thereby regenerating the chrominance sidebands with 3.58 MHz subcarrier. A band-pass filter 351 with 3.58 MHz center frequency responds to the up-converter 325 output signal, to separate the regenerated 3.58 MHz chrominance sidebands from image sidebands. Combining circuitry 327 combines the regenerated 3.58 MHz chrominance sidebands from the filter 351 with the regenerated luminance signal from the FM detector 313 to regenerate composite video signal supplied to a video modulator 329 to modulate the video carrier in a low level television signal transmitter located in the VCR playback electronics.
The peak amplitude of the color-under sidebands is regulated using the variable gain control amplifier 301 prior to mixing with the 4.21 MHz carrier in the up-converter 325. This avoids overloading the mixer in the up-converter 325, while at the same time using the full dynamic range of the mixer. The variable gain control amplifier 301 is advantageously of the type described by the inventor in his allowed U.S. patent application Ser. No. 07/896,442 filed Jun. 10, 1992, entitled "CONTROLLED GAIN AMPLIFIER WITHOUT DC SHIFT OR SIGNAL PHASE REVERSAL IN LOAD CURRENT" and assigned to Samsung Electronics, Co., Ltd, now U.S. Pat. No. 5,184,088. The variable gain control amplifier 301 has its gain controlled by an ACC loop that includes, in addition to the variable gain control amplifier 301: an amplifier 303 responding to the color-under signal from amplifier 301 for supplying that signal as referred to the reference voltage VREF1, a full-wave rectifier comprising the detectors 12 and 14 for the burst portions of the color-under signal so referred, a current-to-voltage converter 16 responding to full-wave rectified color-under signal color-synchronizing burst signal being withdrawn therefrom by detectors 12 and 14 to supply a full-wave rectified burst voltage added to a pedestal voltage VREF2, a peak detector 18 responding to the full-wave rectified burst supplied from the current-to-voltage converter 16 to generate a signal measuring the amplitude of the color-under signal, and a comparator 22 for generating a gain control signal for the variable gain control amplifier 301 depending upon the amount the signal measuring the amplitude of the color-under signal tends to exceed a reference voltage VREF3.
The AGC is keyed in nature, with the detectors 12 and 14 being enabled only when supplied a burst gate signal VGATE at the time color burst occurs. The burst gate signal is generated by a burst gate generator 331 receiving horizontal sync pulses from the horizontal sync separator 317 and generating (in response to those sync pulses) a burst gate signal VGATE a prescribed time after each horizontal sync pulse during the scan lines describing a television image and containing color burst information. The burst gate generator 331 may receive the scan line count from the line counter 319 or separated vertical sync pulses from the vertical sync separator 321, as information used to determine when burst gating pulses are to be discontinued during the vertical blanking interval. Both such connections are shown in FIG. 3 although at most just one of them would be used in normal practice.
The keyed AGC of FIG. 3 differs from that encountered in the playback electronics of prior-art VCRs in that the color burst is detected at 629 kHz from the color-under signal before its up-conversion, rather than being detected at 3.58 MHz after the up-conversion. In newer types of VCRs, such as one of the type generally described in U.S. Pat. No. 5,113,262 entitled VIDEO SIGNAL RECORDING SYSTEM ENABLING LIMITED BANDWIDTH RECORDING AND PLAYBACK issued May 12, 1992 to C. H. Strolle et alii, it is desirable to use time-base correctors for the luminance signal, as demodulated from the frequency-modulated luma carrier, and for the color-under signal. U.S. Pat. No. 5,113,262 describes the digital filtering of the time-base corrected color-under signal to separate therefrom chroma sidebands and a motion signal interleaved with those sidebands. The time-base correctors employ digital memory, written in accordance with a time-base derived from the signals recovered during playback of the tape, and read in accordance with a more stable time-base that permits facilitates transversal digital filtering over adjacent scan lines. The luminance signal and the color-under signal must be digitized before they can be written into the digital memory; and in order more effectively to utilize the limited number of bits resolution (e.g., eight) in a cost-effective analog-to-digital converter, it is a practical necessity to gain control the color-under signal prior to its digitization. The variable-delay time-base correction and the large number of processing steps between the analog-to-digital converter and the up-conversion of the color-under signal to the normal chrominance band for composite video signal tends to cause tracking problems in an automatic gain control (AGC) loop detecting burst amplitude after that up-conversion, which loop can be more particularly characterized as being an automatic color control (ACC) loop.
The detection of color burst at 629 kHz from the color-under signal is more difficult to accomplish than the customary detection of color burst at 3.58 MHz, however, since there is a reduction in the number of cycles available for detection during the burst gate interval. Only one-and-a-half cycles of color burst occur at 629 kHz during the burst gate interval of each scan line. It is no longer convenient to achieve noise-immunity by using keyed synchronous detection. The detection of the peaks of these few cycles of 629 kHz color burst and the filtering to stretch these intermittently detected 629 kHz color bursts into a continuous direct control potential for application to the variable gain control amplifier 301 present more problems than the customary detection of color burst at 3.58 MHz. Full-wave rectifier circuitry embodying the invention was developed to overcome these problems.
The operation of the half-wave rectifiers 12 and 14 and the current-to-voltage converter 16 as part of the FIG. 3 chroma burst detector system is more easily explained with reference to the waveform diagrams of FIGS. 2A through 2D. The waveform of FIG. 2A is the AC input signal, VIN, applied between terminals 19 and 21 of FIG. 1. The waveform, which represents the color-under signal referred to VREF1 produced at the output of an amplifier 303 shown in FIG. 3, includes a "BURST" signal that occurs between times t1 and t2 and a line information signal that occurs between time t3 and t4. The line information signal comprises QAM sidebands encoding two color-difference signals. The "BURST" signal occurring at a frequency of 629 kHz is a reference signal, and it is important that it be properly detected to control the gain of the amplifier 301.
Referring to the portion of waveform of FIG. 2A identified as "BURST", note that the "BURST" signal is an alternating current (AC) signal which goes positive and negative with respect to VREF1 and has an amplitude that may range from a few millivolts to more than a volt. The waveform shown in FIG. 2B is a gating signal VGATE which goes high from time t1 to t2. The waveform of FIG. 2B is supplied from the burst gate generator 331 of FIG. 3; in FIG. 1 this waveform is generated by the source 205 and applied to terminal 207. As discussed above when VGATE is high, the half-wave rectifiers 12 and 14 are enabled, and when VGATE is low, the half-wave rectifiers 12 and 14 are disabled. Consequently, only when VGATE is high are the positive and negative excursions of the "BURST" signal detected as discussed above, to produce a full-wave detected signal superposed on VREF2, as shown in waveform of FIG. 2C.
The full-wave rectified signal (VFN) superposed on VREF2 is the signal which is generated at node 164 in the FIG. 1 circuitry in response to a "BURST" signal of the type shown in waveform A. The VFN signal at 164 is applied to the base of peak detector transistor Q14, which by emitter-folower action charges capacitor C1 to the value of the signal at node 164 (less a VBE drop).
The voltage (VPK) at the output 182 of peak detector 18 increases during a gating period, when VGATE is high, as shown in waveform of FIG. 2D. Following the end of the gating period, the charging capacitor C1 discharges slowly via R4 and the input conductance of the comparator 22, as shown in the waveform of FIG. 2D. The values of C1 and R4 (and the input conductance of comparator 22) are such that C1 discharges very slowly.
As noted above, during the gating period t1 to t2, conduction through Q20 and conduction through Q21 are turned-off. After the gating period is over (gate signal is low), Q21 conduction through is turned-on to clamp node 164 and the base of Q14 at or close to ground potential. This prevents any signal from being fed from the current-to-voltage converter 16 to the peak detector and thence therethrough to capacitor C1.
The output voltage VPK of peak detector 18 is applied to the base of Q15 which defines one input of a differential amplifier comprised of Q15, Q16. A reference voltage VREF3 is applied to the base of Q17, the emitter voltage (VREF3 -VBE) of which is applied to the base of Q16 in emitter-coupled differential amplifier connection with Q15. Thus, when the voltage VPK at node 182 is greater than the voltage at the base of Q16, Q15 conducts and the voltage V01 at its collector is less than the voltage V02 at the collector of Q16. On the other hand, when the voltage at node 182 is less than the voltage at the base of Q16, V01 is greater than V02. The push-pull voltages V01 and V02 may be used to control the gain of an amplifier 301 as shown in FIG. 3 and to perform other control functions.
The FIG. 1 amplitude peak detector can alternatively be used to detect the peak amplitude of color burst in an ACC loop where 3.58 MHz color burst is detected. Unlike a keyed synchronous detector, the FIG. 1 amplitude peak detector is not noise-immune. However, the reduction of the amplitude of color-difference signals during noisy conditions is sometimes deliberately sought by VCR and TV set designers. The FIG. 1 amplitude peak detector is simply modified to provide keyed synchronous detection where it is desired. This can be done by connecting the end of the resistor R5 remote from the node 201, not to the continuous operating potential VCC, but rather to an operating potential VCC chopped to zero at 3.58 MHz rate. Alternatively, a source of 3.58 MHz square wave current may be applied to the node 201.
The configurations shown in FIGS. 4 and 5 also have more general utility as amplifiers, as one skilled in the art and acquainted with the foregoing specification will appreciate, particularly when one desires an amplifier with signal clipping or keying capability (or both, as in a keyed synchronizing signal separator for television receivers). By way of example, the connection of detectors 12 and 14 shown in FIG. 1 for performing full-wave rectification can be modified for use as a signal corer followed by an absolute-value circuit; this is a function that is used in motion detectors for video signals, for example, where the function is used after determining frame-to-frame differences in the video signals to generate motion indications that exhibit immunity to frame-to-frame random noise. In such modification, the detector 12 input terminal 11N will be offset negatively in potential from the VREF1 potential at its input terminal 7N, in order to suppress Q3N collector current response to low levels of negative-going noise; and the detector 14 input terminal 7P will be offset positively in potential from the VREF1 potential at its input terminal 11P, in order to suppress Q3P collector current response to low levels of positive-going noise.
When construing the claims which follow, bear in mind that one skilled in the art will be enabled by acquaintance with the foregoing specification to design a number of variants of the preferred embodiments particularly described and claimed. Such variants are intended to be included within the scope of the broader ones of the following claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3610955 *||Jul 31, 1970||Oct 5, 1971||Fairchild Camera Instr Co||Balanced synchronous detector|
|US3866063 *||Oct 23, 1973||Feb 11, 1975||Fairchild Camera Instr Co||Improved rectifying circuit|
|US4187537 *||Dec 21, 1978||Feb 5, 1980||Zenith Radio Corporation||Full-wave rectifier|
|US4333141 *||Sep 19, 1980||Jun 1, 1982||Tokyo Shibaura Denki Kabushiki Kaisha||Full wave rectifier|
|US4343018 *||Nov 19, 1980||Aug 3, 1982||Sony Corporation||Chrominance signal processing circuit|
|US4523105 *||Sep 27, 1982||Jun 11, 1985||Rca Corporation||Full wave rectifier circuit for small signals|
|US4564814 *||Oct 19, 1982||Jan 14, 1986||Nippon Electric Co., Ltd.||Full-wave rectifier using an operational amplifier|
|US4575643 *||Apr 20, 1983||Mar 11, 1986||Toko Kabushiki Kaisha||Full-wave rectifier circuit|
|US4591735 *||Apr 20, 1984||May 27, 1986||Karlock James A||Video detail enhancing circuit|
|US4685048 *||Mar 12, 1986||Aug 4, 1987||Clarion Co., Ltd.||AC-DC transformation circuit|
|US4941080 *||Sep 14, 1989||Jul 10, 1990||U.S. Philips Corporation||Full wave rectifier circuit|
|US5055994 *||May 21, 1990||Oct 8, 1991||U.S. Phillips Corporation||A.c. to d.c. converter|
|1||"Ac-to-dc converters for low-level input signals", Robert Kreeger, Electronic Design News, Apr. 5, 1973, pp. 60-62.|
|2||"Boost precision rectifier BW above that of op amp used", Jerald Graeme, Electronic Design News, Jul. 5, 1974, pp. 67-69.|
|3||"Measure differential ac signals easily with precision rectifiers", Jerald Graeme, Electronic Design News, Jan. 20, 1975, pp. 45-48.|
|4||*||Ac to dc converters for low level input signals , Robert Kreeger, Electronic Design News, Apr. 5, 1973, pp. 60 62.|
|5||*||Boost precision rectifier BW above that of op amp used , Jerald Graeme, Electronic Design News, Jul. 5, 1974, pp. 67 69.|
|6||*||Measure differential ac signals easily with precision rectifiers , Jerald Graeme, Electronic Design News, Jan. 20, 1975, pp. 45 48.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US5778303 *||Apr 14, 1994||Jul 7, 1998||Matsushita Electric Industrial Co., Inc.||Multiplexed audio-video signal transmission system through pair-wire|
|US8134390 *||Dec 31, 2009||Mar 13, 2012||Inno-Tech Co., Ltd.||Signal converter and method thereof|
|US20100176863 *||Jul 15, 2010||Ting-Chin Tsen||Signal Converter And Method Thereof|
|CN102082517B||Nov 30, 2009||Mar 26, 2014||产晶集成电路股份有限公司||Signal converter and method thereof|
|U.S. Classification||327/104, 327/309, 348/E09.053|
|International Classification||H03K5/08, H04N9/68|
|Cooperative Classification||H03K5/08, H04N9/68|
|European Classification||H04N9/68, H03K5/08|
|Dec 27, 1991||AS||Assignment|
Owner name: CITICORP NORTH AMERICA, INC., NEW YORK
Free format text: TO AMEND THE TERMS AND OBLIGATION OF A SECURITY AGREEMENT DATED 12/29/1986.;ASSIGNOR:KINRO, INC.;REEL/FRAME:006071/0030
Effective date: 19911125
|Dec 30, 1992||AS||Assignment|
Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:CRAFT, JACK;REEL/FRAME:006412/0219
Effective date: 19921217
|Sep 11, 1998||FPAY||Fee payment|
Year of fee payment: 4
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|Aug 18, 2006||FPAY||Fee payment|
Year of fee payment: 12