|Publication number||US5398330 A|
|Application number||US 07/846,237|
|Publication date||Mar 14, 1995|
|Filing date||Mar 5, 1992|
|Priority date||Mar 5, 1992|
|Also published as||US5588113, US5881216, US6374347, US6697936, US6839832, US7395417, US7657728, US20020124160, US20030023837, US20050108510, US20090024841, WO1993018450A1|
|Publication number||07846237, 846237, US 5398330 A, US 5398330A, US-A-5398330, US5398330 A, US5398330A|
|Inventors||Anders R. Johnson|
|Original Assignee||Seiko Epson Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (6), Non-Patent Citations (10), Referenced by (77), Classifications (16), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates to the management of the program-visible machine state of computers, and more particularly, to a computer register file system and method adapted to handle exceptions which prematurely overwrite register file contents.
2. Related Art
A more detailed description of some of the basic concepts discussed in this application is found in a number of references, including Mike Johnson, Superscalar Microprocessor Design (Prentice-Hall, Inc., Englewood Cliffs, N.J. 1991); John L. Hennessy et al., Computer Architecture-A Quantitative Approach (Morgan Kaufmann Publishers, Inc., San Mateo, Calif., 1990). Johnson's text, particularly Chapter 5, provides an excellent discussion of register file exception handling.
Supporting exception handling and in particular precise interrupts, presents a complicated set of problems for the computer architect. For example, the result of a particular instruction cannot be written to a central processor unit's (CPU) register file, or any other part of the program-visible machine state, until after it can be determined that the instruction will not signal any exceptions. Otherwise, the instruction will have an effect on the visible state of the machine after the exception is signaled. (The terms CPU, computer and processor will be used interchangeably throughout this document).
Historically, this problem has been circumvented by increasing the number of processor pipeline stages (pipeline depth) so that the write does not occur until after the latest exception is determined. However, this reduces the allowable degree of instruction interlocking and/or increases the amount of by-pass circuitry required, either of which typically degrades overall performance.
The concept of a "history buffer" is described by J. E. Smith et al. ("Implementation of Precise Interrupts in Pipelined Processors", Proceedings of the 12th Annual International Symposium on Computer Architecture (June 1985), pp. 36-44), as a means for implementing precise interrupts in a pipeline scalar processor with out-of-order completion. In this approach, the register file contains the program-visible state of the machine, and the history buffer stores items of the in-order state which have been superseded by items of lookahead state (i.e., it contains old values that have been replaced by new values; hence the name history buffer).
The history buffer is managed as a circular buffer. Each entry in the history buffer is assigned an entry number. There are n entries in the history buffer, where n corresponds to the length of the longest functional unit pipeline. A head and a tail tag are used to identify the head of the buffer, and the entry in the buffer reserved for the instruction, respectively. Entries between the head and tail are considered valid.
At issue time, each history buffer entry is loaded with: (1) the value of the register file prior to the issuing of the instruction, and control information including: (2) a destination register of the result, (3) the program counter, and (4) either an exception bit or a validity bit, depending on whether an exception is generated at the time of issue.
A Result Shift Register is used in conjunction with the history buffer to manage various machine control signals, including a reorder tag which is required to properly restore the state of the machine do to out-of-order completion. The result shift register includes entries for the functional unit that will be supplying the result and the destination register of the result. The result shift register is operated as a first-in first-out (FIFO) stack.
Results on a result bus from the processor's functional unit(s) are written directly into the register file when an instruction completes. Exception reports come back as an instruction completes and are written into the history buffer. The exception reports are guided to the proper history buffer entry through the use of tags found in the result shift register. When the history buffer contains an element at the head that is known to have finished without exceptions, the history buffer entry is no longer needed and that buffer location can be re-used (the head pointer is incremented). The history buffer can be shorter than the maximum number of pipeline stages. If all history buffer entries are used (the buffer is too small), issue must be blocked until an entry becomes available. Hence, history buffers are made long enough so that this seldom happens.
When an exception condition arrives at the head of the history buffer, the buffer is held, instruction issue is immediately halted, and there is a wait until pipeline activity completes. The active buffer entries are then emptied from tail to head, and the history values are loaded back into their original registers. The program counter value found in the head of the history is the precise program counter.
The extra hardware required by this method is in the form of a large buffer to contain the history information. Also the register file must have three read ports since the destination value as well as the source operands must be read at issue time.
In view of the forgoing, it is clear that a simplified backup system is therefore required to handle exceptions.
The present invention is directed to a register file backup queue system and method for use with a computer which processes instructions to generate results which thereby change the visual state of the computer. The computer has a register file with a plurality of addressable locations for storing data. The backup system of the present invention is adapted to return the visual state of the computer to a previous state if an instruction generates an exception. The backup system utilizes less overhead so as to provide easier register file backup than a comparable software or hardware device.
The present invention sequentially stores in program order in a result tag queue, address information corresponding to destination locations in the register file where instruction results are to be stored.
From the result tag queue, a first portion of the address information is transferred to the register file and a second portion of address information is transferred to a backup queue for backup storage of the register file contents.
The backup queue also receives and stores further information corresponding to the contents of one or more destination locations in the register file before that destination location is changed according to said second portion of said address information.
The present invention transfers said further information from said backup queue back to the register file locations according to said second portion of said address information stored in said backup queue if an instruction exception is generated.
Before an instruction is retired, the value of any program-visible state that an instruction may modify (including, but not limited to, the prior value of the register file destination register) is read such that all instructions up to and including the previous instruction have taken effect prior to the read. The resulting data are placed in the backup queue that, in effect, "remembers" the program-visible state of the processor exactly prior to any given "uncommitted instruction", and thus can be used to nullify the effect of any instruction that causes an exception. (An "uncommitted instruction" is defined by Hennessy et al. as an instruction that may cause an exception at some future time.)
The present invention thus provides a mechanism by which interrupts can be supported for exceptions that are signaled after the result is written and without out-of-order completion. Design complexity is minimally increased, in that the pipeline depth of the processor does not need to be increased to handle the late-exception case. This approach is easier to "tack on" to an existing design (e.g., in the case that an enhancement makes the late-exception case possible where it was not possible before) rather than increasing the pipeline depth. In some configurations, overall performance is not significantly impacted, except in the case that an exception occurs.
The foregoing and other features and advantages of the present invention will be apparent from the following more particular description of the preferred embodiments of the invention, as illustrated in the accompanying drawings.
The invention will be better understood if reference is made to the accompanying drawings in which:
FIG. 1 shows a representative block diagram of a register file backup queue system of the present invention.
FIG. 2 is a representative flow chart showing the basic steps taken by the register file backup queue system of the present invention.
The operation of the invention is illustrated with reference to a representative block diagram shown in FIG. 1
In this example, the computer register file system environment of the present invention as shown in FIG. 1 comprises a register file 102 having a plurality of addressable locations for storing instruction operands and results, functional units and bypass logic 104, a result tag queue 106 for storing information corresponding to the address of the register file location that is designated by the instruction to store results (also called result tag), a backup queue 108, a backup data latch 110, a backup tag latch 112, a data multiplexer 114 and an address/tag multiplexer 116.
In the above example it is easiest to think of the block 102 as a register file of a central processor unit (also called the processor, CPU or computer), but the present invention applies to any part of (or the entirety of) the program-visible machine state without loss of generality.
Register file 102 includes a P-- adr input to receive information corresponding to the address(es) of the register(s) storing the operand(s) of the instruction (also called operand tags). The operands are stored in register file 102 and are passed to functional units 104 via a bus 134 for execution of the instruction in a conventional manner.
In addition to reading the operands of the instruction, the system determines the destination register to receive the results of the instruction. The system then reads the contents of that destination register prior to execution of the instruction and stores the contents and a tag (e.g., the address of the register file entry, for example) corresponding to the destination register into backup queue 108. In the event of an exception (e.g., an arithmetic exception such as an add overflow), the state of register file 102 prior to the exception can be restored by reading the contents of backup queue 108 and storing that data back into register file 102 at the location specified by the corresponding tag.
To coordinate backup of data in register file 102 a result tag queue 106 is required. Result tag queue 106 stores tags corresponding to the destination location in register file 102 for storing instruction results. Result tags are generated by decoding the instructions in a conventional manner. The tags stored in result tag queue 106 are stored in a first-in-first-out manner in execution order. Result tag queue 106 delays the tag until the previous instructions have completed in case they write to the same destination location in the register file.
The depth of backup queue 108 depends on the number of pipeline stages (i.e., cycles) between the cycle the register file is written and the cycle that an exception is detected.
One embodiment of the present invention comprises a three stage pipeline with fetch, decode and execute/store operations. In this embodiment, an exception can only be signaled during the same cycle that register file 102 is written. Therefore, backup queue 108 only needs to be deep enough to store the contents of one destination register and its tag.
Conventionally, if several instruction results are written to register file 102 and an exception occurs after a multi-cycle pipeline delay, the result is that many states of the machine would be wiped out by the late signaled exception. In the present invention, however, by deepening the backup queue 108 the lost states can be recovered in order to be able to restore those lost states. Before the exception can be handled, all previous results (those in the register file before the instruction executed) must be written back into register file 102 up to the instruction preceding the instruction that generated the exception.
As appreciated by those skilled in the art, signals that indicate whether a data exception (for example) has occurred originate in the data path and are detected by control logic (not shown). Control logic then determines what to do and generates a control signal 118 (shown in FIG. 1) which selects one of the sets of inputs of MUXs 114 and 116.
Under normal operation (i.e., no exception), control signal 118 controls MUX 114 to select "instruction result data" 122 from functional units 104 to pass the results to register file 102's write port W.
If an exception is detected, control signal 118 controls MUX 114 to select j"unwrite data" 124 from backup queue 108 to return the state of the register file to the state that it was in just prior to the instruction that caused the exception. The unwrite data 124 is that data on the top of the backup queue 108.
Similarly, under normal operation (i.e., no exception), control signal 118 controls MUX 116 to select a result tag from the top of result tag queue 106 to a write address input W-- adr of register file 102. If an exception is detected, control signal 118 controls MUX 116 to select an "unwrite tag" 125 from backup queue 108 to instruct register file 102 where to store the unwrite data.
The backup of data will now be discussed. As shown in FIG. 1, register file 102 also includes an input port "Q-- adr" for receiving information concerning instruction operands from result tag queue 106. The Q-- adr input port receives a "backup tag" 126 from result tag queue 106 corresponding to the data that is to be written into the backup queue 108. In this example, a bus 128 is shown connected to the entry of result tag queue 106 that is to be written to the register file 102 in the next cycle. At the same time a result tag is sent to the Q-- adr input it is sent via bus 128 to backup queue 108 and is temporarily stored in a tag latch 112. This permits the present invention to store the results to be overwritten by the next instruction in backup queue 108. Register file 102 outputs the "backup data" 130 corresponding to the backup tag 126 via a data output port "Q". Backup data 130 is sent to a data latch 110 so that its corresponding backup tag 126, which arrived earlier at tag latch 112, can be latched into backup queue 108 at the same time.
A control line 132 is provided to switch the direction of stacking of backup queue 108. In normal operation, backup data and backup tags are pushed into backup queue 108. In this example the backup queue 108 has a depth of one. Depending on its depth, old information is said to be "pushed out of the bottom" of the stack when the last entry is written over by newer information. If an exception is detected, control signal 132 reverses the direction of backup queue 108 and information is popped off in a last-in, first-out fashion, and is stored back into register file 102.
The process of unwriting can be controlled either by hardware or by the operating system in software. However, if the operating system does it, then care must be taken to ensure that the instructions that control the process do not write into backup queue 108 themselves; that is, there must be a mechanism for disabling the queue before the exception handler is invoked.
In a preferred embodiment of the present invention, an additional read port (i.e., in addition to the P port) is not required because the read stage and write state are separated by exactly one cycle, and one of the following conditions is satisfied:
1. There are instructions that cannot generate late exceptions that require a read port in addition to those required by instructions that can generate late exceptions, and the depth of backup queue 108 is exactly 1 (i.e., the latest exception signals exactly one cycle too late to abort the corresponding write).
2. Every instruction that requires the maximum number of read ports always writes to the same register number as one of its arguments.
If one of the previous conditions is satisfied, but the read stage and the write stage are separated by more than one cycle, then the present invention is still applicable without increasing the number of register-file read ports. In this case, it is necessary to read into backup queue 108 at the read stage instead of the stage before write, and to deepen backup queue 108. This, however, is not optimum because the additional interlock (from the result of a previous instruction to the backup read) may degrade performance.
As an example of the present invention, consider a machine with 5 pipeline stages A, B, C, D, and E, as shown below in Table 1. A representative flow chart of this example is shown in FIG. 2. Table 1 and FIG. 2 will be referred to jointly in the following discussion. The write occurs in stage D. An exception can occur in state E. Exceptions that signal after stage C of an instruction cannot prevent that instruction from writing. (Reads can occur in any of stages A, B or C without relevance to this example.) Backup queue 108 of the present invention must be two storage locations deep because exceptions can signal two cycles too late to prevent the corresponding write.
In Table 1, the cycle numbers 1-9 are shown along the top, and instructions i through i+4 and backup queue storage locations Q1 and Q2 are shown along the left hand side.
TABLE 1__________________________________________________________________________Example Pipeline with Backup QueueCycle Number1 2 3 4 5 6 7 8 9__________________________________________________________________________i* A B C D Ei + 1* A B C D Ei + 2* A B C D E***i + 3* A B C Di + 4* A B CQ.sub.1 ** i - 3 i - 2 i - 1 i i + 1 i + 2 i + 3 i + 3 i + 2Q.sub.2 ** i - 4 i - 3 i - 2 i - 1 i i + 1 i + 2 i + 2__________________________________________________________________________ *Instruction Number **Backup Queue ***Exception Signaled
The backup and exception detection of instruction i+2 is shown in FIG. 2. The operation starts at a step 202. Instruction i+2 is backed up into backup queue Q1 at stage D in cycle 6, as shown in a step 204. The result of instruction D is sent to the register file, as shown at a step 206. Suppose an exception is caused by instruction i+2 and signals in cycle 7 (see the yes branch "Y" at a conditional step 208). At this point, the instructions in stages A, B (not shown in cycle 7) and C are aborted (see a step 210), but the results of all instructions through instruction i+3 have already been written, However, from the program's viewpoint, instructions i+2 and i+3 should not have affected the state because of the exception. The state overwritten by these two instructions is stored in the backup queue (see a step 212). The data in Q1 is written back into the register file at the destination address of instruction i+3 in cycle 8 (see a step 214). Then the backup queue shifts in the reverse direction and the data in Q1 is written back at the destination of instruction i+2 in cycle 9 (see a step 216). The entire visible state now has an appropriate value for the first instruction of the exception handler to be fetched and executed (see a step 218).
Note that if instruction i-2 did not signal an exception in stage E and instruction i-3 signaled an exception in stage D, then the process would be much the same, except that instruction i-2 would not be nullified. (See loop 221 comprising steps 222 and 224.) If no exception is detected, the pipeline is merely advanced, as shown in a step 226, and execution continues.
In a further embodiment of the present invention, it is possible to use this invention to manage part of the visible state while deepening the pipeline for the remainder of the state. The most likely application is to use a backup queue for the register file(s) while delaying the retire for status bits, since it may be possible to implement bypass logic for the status bits without degrading performance.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example, and not limitation. Thus the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
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|U.S. Classification||714/15, 712/E09.049, 712/E09.061|
|International Classification||G06F9/48, G06F9/38, G06F9/46, G06F9/34|
|Cooperative Classification||G06F9/3836, G06F9/3855, G06F9/3857, G06F9/3865, G06F9/3863, G06F9/3859|
|European Classification||G06F9/38H3, G06F9/38H2, G06F9/38E|
|Mar 31, 1992||AS||Assignment|
Owner name: S-MOS SYSTEMS, INC.
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:JOHNSON, ANDERS R.;REEL/FRAME:006076/0063
Effective date: 19920310
|May 28, 1992||AS||Assignment|
Owner name: SEIKO EPSON CORPORATION, A CORP. OF JAPAN, JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:S MOS SYSTEMS, INC.;REEL/FRAME:006136/0960
Effective date: 19920522
|Aug 31, 1998||FPAY||Fee payment|
Year of fee payment: 4
|Aug 22, 2002||FPAY||Fee payment|
Year of fee payment: 8
|Aug 18, 2006||FPAY||Fee payment|
Year of fee payment: 12
|May 3, 2012||AS||Assignment|
Effective date: 20111206
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SEIKO EPSON CORPORATION;REEL/FRAME:028153/0654
Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF