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Publication numberUS5412596 A
Publication typeGrant
Application numberUS 08/235,149
Publication dateMay 2, 1995
Filing dateApr 28, 1994
Priority dateOct 25, 1991
Fee statusPaid
Publication number08235149, 235149, US 5412596 A, US 5412596A, US-A-5412596, US5412596 A, US5412596A
InventorsKazuhiro Hoshiba
Original AssigneeRohm Co., Ltd.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor storage device with a ferroelectric transistor storage cell
US 5412596 A
Abstract
A semiconductor storage device having a memory array composed of storage ceils arranged in a matrix. The storage cells include a ferroelectric transistor having a metal-ferroelectrics-semiconductor structure and a switching transistor. A source electrode of one of the transistors and a drain electrode of the other transistors are connected to each other. According to the present invention, the necessary time for writing becomes short, realizing a rapid operation of nano second order. Further, many times (1010 order) of rewriting is possible. This brings a longer life thereof compared with a EEPROM which is rewritable about 104 times. Since the reading out is non-destructive, the rewriting is not required so that the life of the device is further lengthened.
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Claims(2)
What is claimed is:
1. A semiconductor storage device having a memory array composed of storage cells arranged in a matrix on a semiconductor substrate, said storage cells each comprising:
a ferroelectric transistor having source and drain regions provided in said semiconductor substrate, a ferroelectric film provided directly on a surface of said semiconductor substrate between said source and drain regions, and a first gate electrode provided on said ferroelectric film, said ferroelectric transistor to store information by utilizing residual polarization of said ferroelectric film; and
a switching transistor having a channel region provided in said semiconductor substrate and adjacent to said ferroelectric transistor, and a second gate electrode provided over both the channel region and said first gate electrode;
wherein a source electrode of one of the two transistors is connected to a drain electrode of the other transistor.
2. The semiconductor device of claim 1, wherein the memory array comprises a first word line, a second word line, a bit line and a source line,
the first word line connecting gate electrodes of switching transistors in one lateral or longitudinal line of the array;
the second word line connecting gate electrodes of ferroelectric transistors in one lateral or longitudinal line of the array;
the bit line connecting drain electrodes of one of said switching or ferroelectric transistors of which source electrodes are connected to drain electrodes of the other one of said switching or ferroelectric transistors in one longitudinal or lateral line which is perpendicular to the second word line; and
the source line connecting source electrodes of said other one of said switching or ferroelectric transistors and said semiconductor substrate to ground.
Description

This application is a continuation of application Ser. No. 07/961,955 filed Oct. 16, 1992, now abandoned.

FIELD OF THE INVENTION

The present invention relates to a nonvolatile semiconductor storage device employing a ferroelectric film capacitor. A semiconductor storage device of the present invention has a memory array wherein storage ceils employing a ferroelectric film and a field-effect transistor (hereinafter referred to as FET) are arranged in a matrix.

BACKGROUND OF THE INVENTION

A conventional memory array is shown in FIGS. 6 and 7. The array comprises storage cells, each employing a ferroelectric film capacitor, arranged in a matrix.

The memory array in FIG. 6 is disclosed in U.S. Pat. No. 4,873,664, where a ferroelectric film capacitor C is connected with a source electrode of a switching transistor ST to form a storage cell.

The memory array in FIG. 7 disclosed in Japanese Unexamined Patent Publication No. 64993/1990, where a switching transistor ST is connected in series with the front and the rear of a metal-ferroelectrics-semiconductor transistor (hereinafter referred to as ferroelectric transistor FT) to form a storage cell. The ferroelectric transistor FT is one of FET and a ferroelectric film is used as a gate insulating film thereof.

The March 1990 issue of NIKKEI MICRODEVICES reports in pp. 72-77 that flash-type EEPROMS are is earnestly being developed as nonvolatile storage cells.

When reading out a storaged information from the memory array shown in FIG. 6, the polarized direction of the ferroelectric film is reversed and the storaged information is destroyed. This "destructive reading" which requires rewriting cell after reading out. Thus, such a semiconductor storage device has a disadvantage that the operation thereof is complicated.

The memory array shown in FIG. 7 enables non-destructive reading. However, it requires three transistors per bit. Thus, it has a disadvantage that its cell area must be enlarged.

In a flash-type EEPROM which is being earnestly developed today, it takes a long time (microsecond order) for writing. This is three orders of magnitude slower than that of the storage cell employing a ferroelectric film capacitor or of DRAM, of which necessary time for writing is nano second order. Thus, the flash-type EEPROM has a disadvantage that the necessary time for writing is very long.

SUMMARY OF THE INVENTION

In view of the above-mentioned problems, an object of the present invention is to provide a semiconductor storage device in which the necessary time for writing is short, in which reading out is non-destructive and in which the cell area is small. A semiconductor storage device of the present invention uses a nonvolatile memory array composed of storage cells employing a ferroelectric film.

According to the present invention, there is provided a semiconductor storage device having a memory array composed of storage cells arranged in a matrix, wherein the storage cells comprise a ferroelectric transistor having a metal-ferroelectrics-semiconductor structure and a switching transistor, and a source electrode of one of the transistors and a drain electrode of the other transistor are connected to each other.

The memory array in a semiconductor device of the present invention comprises a first word line, a second word line, a bit line and a source line, the first word line connecting gate electrodes of switching transistors in one lateral or lingitudinal line of the array; the second word line connecting gate electrodes of ferroelectric transistors one lateral or longitudinal line of the array; bit line connecting drain electrodes of ferroelectric transistors or switching transistors in one longitudinal or lateral line perpendicular to the second word line, the drain electrodes not being connected to source electrodes of ferroelectric transistors or switching transistors; and the source line connecting source electrodes of switching transistors or ferroelectric transistors and semiconductor substrates to the ground, the source electrodes not being connected to drain electrodes of switching transistors or ferroelectric transistors.

In a semiconductor storage device of the present invention, one ferroelectric transistor and one switching transistor are connected in series to form a storage cell. Due to this, writing to a desired storage cell can be performed by selecting the word line and the bit line, and erasing can be performed per each word line. Further, reading out from a desired storage cell can be performed by selecting the word line connecting the gate electrodes of the switching transistor and the bit line.

BRIEF EXPLANATION OF THE DRAWINGS

FIG. 1 is a cross section showing a structure of a transistor with a ferroelectric film capacitor;

FIG. 2 is a graph showing a hysteresis characteristic of a ferroelectric transistor;

FIG. 3 is an explanatory view showing a structure of an embodiment of a memory array of the present invention;

FIG. 4 is an explanatory view showing a condition where a bit line in the memory array is connected with a sense amplifer circuit;

FIG. 5 is a cross section of a semiconductor structure of an embodiment of a storage cell of the present invention;

FIG. 6 is a circuit diagram of a conventional storage cell; and

FIG. 7 is a circuit diagram of another conventional storage cell.

DETAILED DESCRIPTION

A semiconductor storage device of the present invention is explained below with reference to the drawings.

In FIGS. 1 to 5, numeral 1 represents a source region wherein n+ impurity is diffused. Numeral 2 represents a drain region wherein n+ impurity is diffused. Numerals 3, 4 and 5 respectively represent a p-type silicon semiconductor substrate, a ferroelectric film and a gate electrode. Symbols WL1 (WL1a, WL1b) and WL2 (WL2a, WL2b) respectively represent a first word line and a second word line. Symbols BL (BLa, BLb) and SL respectively represent a bit line and a source line. Numerals 13 and 14 respectively represent an insulating film. Numeral 15 represents a gate insulating film.

The operation of the transistor having the ferroelectric film 4 is explained based on FIGS. 1 and 2. FIG. 1 is a cross section of a ferroelectric transistor employing a ferroeletric film capacitor. FIG. 2 is a graph showing a relationship between the gate voltage applied to the ferroelectric transistor and the current flowing between source and drain. The ferroelectric transistor FT is one obtained by replacing a gate insulating film of a MISFET (metal-insulator-semiconductor FET) with a ferroelectric film. In the FT of this embodiment, a ferroeletric film 4 and a gate electrode 5 are formed on a p-type semiconductor substrate 3 as shown in FIG. 1. n+ impurity is diffused therearound to form a source region 1 and a drain region 2. When a voltage higher than a certain value is applied between the gate electrode 5 and the substrate 3, a residual polarization is brought because of the hysteresis characteristic of the ferroelectric film 4. Thus, even if electric potential of the electrode 5 is made to be 0 V, a current flows between the source and the drain. This relationship is shown in FIG. 2.

In the graph of FIG. 2, the axis of abscissa indicates gate voltage VG and the axis of the ordinate indicates current IDS between the source and the drain. Hysteresis characteristic is shown in the relationship between the voltage and the current. Once a voltage higher than VG1 is applied to the FT, current keeps on flowing unless the applied voltage is lowered to --VGO or less. In this specification, this condition (the current is on) is defined as written and this is indicated by "1". When the applied voltage is lowered to --VGO or less, the current between the source and the drain stops flowing. In this specification, this condition (the current is off) is defined as erased and this is indicated by "0".

Thus, by making the ON condition correspond to the "1" and the OFF condition to the "0", each storage cell serves as a memory. When reading out, a voltage is applied between the source and the drain, and a condition of a ferroelectric film (ON or OFF) can be distinguished from the fact that current flows or not, or voltage drop happens or not. Thus, the polarized direction of the ferroelectric film does not reverse when reading out, that is, non-destructive reading out can be performed.

A constitution of a memory array is explained below. In this memory array, the ferroelectric transistor FT and the switching transistor ST are connected in series to form a storage cell and this cell is arranged in a matrix.

As shown in FIG. 3, storage cells A, B, C, and D are respectively formed by connecting one ferroelectric transistor FT and one switching transistor in series. In this embodiment, a source electrode of the transistor FT and a drain electrode of the transistor ST is connected.

These storage cells are arranged in a matrix to form a memory array. In FIG. 3, four memory cells A, B, C and D are arranged in two longitudinal lines and in two lateral lines, and electrodes of each cell are wired to form an array. The array comprises first word lines WL1aand WL1b, second word lines WL2a and WL2b, bit lines BLa and BLb, and a source line. The first word line WL1a connects the gate electrodes of the switching transistors ST of the storage cells A and B, and the first word line WL1b connects the gate electrodes of the switching transistors ST of the storage cells C and D. The second word line WL2a connects the gate electrodes of the ferroelectric transistors FT of the storage cells A and B, and the second word line WL2b connects the gate electrodes of the ferroelectric transistors FT of the storage cells C and D. The bit line BLa connects the drain electrodes of the ferroelectric transistors FT of the storage cells A and C. The bit line BLb connects the drain electrodes of the ferroelectric transistors FT of the storage cells B and D. The source line SL connects the source electrodes of the switching transistors and the semiconductor substrates of all the storage cells to ground.

Hereinafter how the constitution serves as a memory array is explained. In this explanation the storage cell A serves as a selected cell carrying out writing, and the other cells B, C and D respectively serve as a non-selected cell.

The writing is carried out as follows. When a voltage not lower than VG1 is applied to the second word line WL2a, the "1" which corresponds to an ON condition is stored in the cell A. At this operation, a voltage VD is applied to the bit line BLb. The voltage VD is so selected that it is smaller than the voltage VG1, however, the difference between the VG1 and VD does not cause a reverse of a polarized direction of the ferroelectric film and allows a depletion layer to extend at channel. For this reason, by applying such voltage VD to the bit line BLb, the storage cell B is prevented from being written into . The voltage VD must be smaller than the voltage VD also for preventing a reverse of the condition of the storage cell from ON to OFF. Electrical potential of all the other lines are kept at 0 V.

The erasing is carried out as follows. When a voltage not higher than --VGO is applied to the second word line WL2a, the storage cells A and B can be set at "0" (the condition OFF). That is, the erasing is carried out per each line like a flash memory or the like. In the operation, electric potential of all the other lines are kept at 0 V.

The reading out is carried out as follows. Electric potential of the first word line WL1a is set at a voltage Vth which causes the switching transistor to be ON. The bit line BLa is precharged at a reference voltage, and is connected to a sense amplifier SA as shown in FIG. 4. Electric potential of all the other lines are kept at 0 V. In this condition, if the ferroelectric transistor FT stores the "1", current flows between the drain and the source, and the voltage of the bit line BLa drops. On the other hand, if the ferroelectric transistor FT stores "0", current does not flow between the drain and the source, and the voltage of the bit line BLa does not drop. Thus it can be found whether the ferroelectric transistor FT of the storage cell stores the "1" or the "0", by the fact that the applied voltage to the bit line BLa drops or not.

Those relationships are summarized in Table 1. In Table 1, symbols 0 mean that each line is grounded.

              TABLE 1______________________________________WL1a        WL2a     BLa    WL1b   WL2b  Blb______________________________________writing 0       VG1 0    0      0     VD           or moreerasing 0       -VG0                    0    0      0     0           or lessreading out   Vth           0        SA   0      0     0______________________________________

One of such storage cells is shown in FIG. 5 with a cross section of its semiconductor. In FIG. 5, numeral 2 represents a drain region of a ferroelectric transistor FT. Numeral 16 represents a source region of a switching transistor ST, and this region 16 is grounded by the source line SL. Between the drain region 2 and the source region 16, a channel region is defined. The channel region is partly covered by ferroelectric film 4 which is directly formed on semiconductor substrate 3. The ferroelectric film 4 has a first gate electrode on top of it to form the ferroelectric transistor FT. The part of the channel which remains uncovered by the ferroelectric film 4 is covered by a second gate electrode with gate insulating film 15 interposed therebetween to form the switching transistor ST. The second gate electrode extends over the first gate electrode to complete the flow of carrier between the transistors FT and ST. The first and the second gate electrodes are connected with the second and the first word lines WL2a and WL1a, respectively. As a material for the ferroelectric film, PZT (PbZr1-x Tix O3), PLZT ((Pb1-x Lax) (Zr1-y Tiy)1-x/4 , O3) or the like can be preferably employed because of their high spontaneous polarization. As a material for the word line and bit line, a doped polysilicon with phosphorus is typical, however, a metal such as platinum can replace the doped polysilicon.

In the above-mentioned embodiment, the source electrode of the ferroelectric transistor FT and the drain electrode of the switching transistor ST are connected to form a storage cell. However, the transistors FT and ST are interchangable to each other. In that case, the source electrode of the transistor FT is grounded by the source line SL, and the drain electrode of the transistor ST is connected with the bit line. In the above-mentioned embodiment, the first and the second word lines WL1 and WL2 connect the lateral lines of the transistors, and the bit lines connect the longitudinal lines of the transistors. However the way of connection is not limited thereto. The word lines WL2 and the bit line are interchangable to each other as long as they cross perpendicularly to each other.

As explained above, according to the present invention, a storage cell is composed of one ferroelectric transistor and one switching transistor, and a memory array is constituted with the storage cells. For this reason, a storage device of the present invention can be made smaller. Further, a condition of the ferroelectric film ("1" or "0") can be distinguished from the fact that current flows or not under the applied voltage, whereby the polarized direction of the ferroelectric film does not reverse, that is, non-destructive reading out can be carried out.

A storage device of the present invention employs a ferroelectric film capacitor, so that the necessary time for writing becomes short whereby realizing a rapid operation of nanosecond order. Further, many times (1010 order) of rewriting is possible. This brings a longer life thereof compared with a EEPROM which is rewritable about 104 times. Since the reading out is non-destructive, the rewriting is not required so that the life of the device is further lengthened.

Thus, there can be realized a storage device having a small-sized and easy-to-use memory array with high performance and this greatly contributes to the development of recent electronics.

Though several embodiments of the present invention are described above, it is to be understood that the present invention is not limited only to the above-mentioned, various changes and modifications may be made in the invention without departing from the spirit and scope thereof.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US4161038 *Sep 20, 1977Jul 10, 1979Westinghouse Electric Corp.Complementary metal-ferroelectric semiconductor transistor structure and a matrix of such transistor structure for performing a comparison
US4873664 *Feb 12, 1987Oct 10, 1989Ramtron CorporationSelf restoring ferroelectric memory
US4888630 *Mar 21, 1988Dec 19, 1989Texas Instruments IncorporatedFloating-gate transistor with a non-linear intergate dielectric
US5010520 *Jul 27, 1988Apr 23, 1991Kabushiki Kaisha ToshibaNonvolatile semiconductor memory device with stabilized data write characteristic
US5197027 *Jan 24, 1991Mar 23, 1993Nexcom Technology, Inc.Single transistor eeprom architecture
US5198994 *Nov 8, 1991Mar 30, 1993Kabushiki Kaisha ToshibaFerroelectric memory device
US5218568 *Dec 17, 1991Jun 8, 1993Texas Instruments IncorporatedElectrically-erasable, electrically-programmable read-only memory cell, an array of such cells and methods for making and using the same
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US5592409 *Jan 18, 1995Jan 7, 1997Rohm Co., Ltd.Nonvolatile memory
US5666305 *Mar 14, 1995Sep 9, 1997Olympus Optical Co., Ltd.Method of driving ferroelectric gate transistor memory cell
US5757042 *Jun 14, 1996May 26, 1998Radiant Technologies, Inc.High density ferroelectric memory with increased channel modulation and double word ferroelectric memory cell for constructing the same
US5768176 *Jun 6, 1997Jun 16, 1998Nec CorporationMethod of controlling non-volatile ferroelectric memory cell for inducing a large amount of electric charge representative of data bit
US5789775 *Jan 26, 1996Aug 4, 1998Radiant TechnologiesCircuit for storing a word
US5856688 *Sep 30, 1997Jan 5, 1999Samsung Electronics Co., Ltd.Integrated circuit memory devices having nonvolatile single transistor unit cells therein
US5959879 *Mar 31, 1998Sep 28, 1999Samsung Electronics Co., Ltd.Ferroelectric memory devices having well region word lines and methods of operating same
US5978250 *Sep 17, 1997Nov 2, 1999Samsung Electronics Co., Ltd.Ferroelectric memory devices having reconfigurable bit lines and methods of operating same
US5978253 *Nov 13, 1998Nov 2, 1999Samsung Electronics Co., Ltd.Methods of operating integrated circuit memory devices having nonvolatile single transistor unit cells therein
US6025735 *Dec 23, 1996Feb 15, 2000Motorola, Inc.Programmable switch matrix and method of programming
US6072454 *Feb 28, 1997Jun 6, 2000Kabushiki Kaisha ToshibaLiquid crystal display device
US6097624 *Oct 29, 1999Aug 1, 2000Samsung Electronics Co., Ltd.Methods of operating ferroelectric memory devices having reconfigurable bit lines
US6147896 *Oct 28, 1999Nov 14, 2000Electronics And Telecommunications Research InstituteNonvolatile ferroelectric memory using selective reference cell
US6198651Sep 8, 1998Mar 6, 2001Samsung Electronics Co., Ltd.Ferroelectric memory devices which utilize boosted plate line voltages to improve reading reliability and methods of operating same
US6215693May 8, 2000Apr 10, 2001Samsung Electronics Co., Ltd.Methods of operating ferroelectric memory devices having reconfigurable bit lines
US6922361 *Jun 8, 2004Jul 26, 2005Samsung Electronics Co., Ltd.Non-volatile memory device
US7075144May 20, 2005Jul 11, 2006Samsung Electronics Co., Ltd.Non-volatile memory device
US7259981 *Nov 29, 2005Aug 21, 2007United States Of America As Represented By The Administrator Of The National Aeronautics And Space AdministrationNonvolatile analog memory
US7643326 *Dec 14, 2007Jan 5, 2010Hynix Semiconductor, Inc.Semiconductor memory device with ferroelectric device
US7898009 *Feb 22, 2007Mar 1, 2011American Semiconductor, Inc.Independently-double-gated transistor memory (IDGM)
US8089108Feb 28, 2011Jan 3, 2012American Semiconductor, Inc.Double-gated transistor memory
US8148759 *Feb 28, 2011Apr 3, 2012American Semiconductor, Inc.Single transistor memory with immunity to write disturb
US8213259 *Oct 12, 2010Jul 3, 2012Seagate Technology LlcNon-volatile memory cell with resistive sense element block erase and uni-directional write
US8493768 *Nov 21, 2011Jul 23, 2013Electronics And Telecommunications Research InstituteMemory cell and memory device using the same
US20110026305 *Oct 12, 2010Feb 3, 2011Seagate Technology LlcNon-Volatile Memory Array With Resistive Sense Element Block Erase and Uni-Directional Write
US20120007158 *Jun 30, 2011Jan 12, 2012Electronics And Telecommunications Research InstituteNon-volatile memory transistor having double gate structure
US20120134197 *Nov 21, 2011May 31, 2012Eletronics And Telecommunications Research InstituteMemory cell and memory device using the same
WO1997027631A1 *Jan 21, 1997Jul 31, 1997Radiant Technologies IncHigh density memory and double word ferroelectric memory cell for constructing the same
Classifications
U.S. Classification365/145, 257/E27.104, 257/295
International ClassificationG11C11/22, H01L27/115
Cooperative ClassificationH01L27/11502, G11C11/22
European ClassificationG11C11/22, H01L27/115C
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