|Publication number||US5438667 A|
|Application number||US 08/175,689|
|Publication date||Aug 1, 1995|
|Filing date||Dec 30, 1993|
|Priority date||Jan 3, 1991|
|Also published as||DE4100056A1|
|Publication number||08175689, 175689, US 5438667 A, US 5438667A, US-A-5438667, US5438667 A, US5438667A|
|Original Assignee||Meder; Horst|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (5), Referenced by (1), Classifications (5), Legal Events (7)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a continuation of application Ser. No. 07/665,299 filed Mar. 6, 1991, now abandoned.
1. Field of the Invention
The invention relates to a method for bidirectional data transmission between a computer system having at least two processors or a processor divided into a plurality of real or virtual subsystems with different control unit address administration and at least one peripheral unit with unique control unit address which is connected via data paths to said computers.
2. Description of the Related Art
The invention accordingly relates to a method for addressing compatibility of heterogeneous computer systems and also to an electronic apparatus for automatic control unit address conversion.
A heterogeneous computer system may consist of one or more processors, frequently of different type, and a number of peripheral units, such as disk memories, magnetic tape units, display devices and printers. In such a multiprocessor composite system for functional and economic reasons it is frequently expedient to make a peripheral device accessible to more than one processor.
To enable a peripheral unit to be addressed by a processor a unique control unit address must be assigned thereto. Hardware and/or software-induced or organisational restrictions in processors of different type may require different control unit addresses for the same peripheral unit. In such a case, the peripheral unit provided with a unique address can be used only by processors which address the peripheral unit via the same control unit address.
Hitherto it was necessary to use different peripheral units for different processors.
If a plurality of peripheral units is employed the result is a considerable financial expenditure. Even then, the computers cannot directly access the information (services) of the respective other peripheral unit. In such a case, until today for example in a magnetic tape system a human operator had to remove the magnetic tape from the magnetic tape system associated with the processor B and place it in a second magnetic tape system associated with the processor A.
Another possibility resides in switching the data paths over using a conventional channel switch but in that case the peripheral device must be reconfigured to the control unit address of the respective processor which in many systems is not possible or is not possible at any instant. It is only by employing such unsatisfactory ways that the processor A can have access to the services of the peripheral unit allocated to the processor B. This manifests itself as a considerable disadvantage in information processing, both from the financial and from the organisational point of view. This unsatisfactory condition is the state of the art.
It would be desirable to have available a method which permits free access of the processors to peripheral devices irrespective of possible hardware and/or software-induced restrictions.
The invention is therefore based on the problem of making available a method which permits access to peripheral units irrespective of any restrictions (hardware and/or software) and that in particular permits the simultaneous use of a peripheral unit by processors of different type.
This complex problem is surprisingly solved in a method of the type wherein the computers addressing logs are output and the addressing logs of the computers having control unit addresses which are inconsistent with the control unit address of the peripheral unit are monitored, then in a writing operation to the peripheral unit (i.e. in the direction from the computer to the peripheral unit) the control unit address to be identified in the addressing logs is automatically detected, wherein a control signal for address conversion is output, then on the basis of the control signal for address conversion the normal data path is blocked, thereby simultaneously the preset control unit address consistent with the peripheral unit is switched to the normal data path and is further conducted to the peripheral unit, then for reading data from the peripheral unit (i.e. in the direction from the peripheral unit to the computer) the control unit address transmitted by the peripheral unit is automatically recognised, then the normal data path is blocked, and instead the control unit address consistent with the computer is switched to the normal data path and further conducted to the computer and that after an effected address conversion the data transmission takes place bidirectionally.
The method according to the invention can be carried out with an apparatus which is distinguished by an addressing compatibility device in the data path between a computer, the control unit address of which is not consistent with the control address of the peripheral unit, and the peripheral unit.
Generally, the automatic address conversion is carried out in that the addressing logs on the data paths of the individual processors are monitored and if necessary converted for the purpose of addressing compatibility.
The procedure here may be that a detecting device connected into the data path of the processor which monitors the addressing log of the address/data bus. If the detecting device recognises the control unit address of the processor for the respective peripheral device, a control signal is activated and the normal data path blocked. At the same time as the blocking occurs, via an addressing device the control address of the peripheral device made available by the addressing generator is switched to the data path.
"Addressing generator" means an electronic circuit permitting presetting of the control unit address of the processor and of the peripheral device. The generated control unit addresses are used to detect the control unit address of the processor for the respective peripheral device and for making available the address valid for the peripheral device on detection.
A "detecting device" means an electronic circuit which monitors the data path and in the event of the control unit address preset in the addressing generator being present automatically outputs a control signal for address conversion. The control signal blocks the normal data path.
The addressing generator may be constructed as simple DIP switch or as chargeable storage means. In the latter case a dynamic programmable address switchover is possible without delay and without manual intervention.
An "addressing device" means an electronic circuit which stores the preset control unit address and outputs the latter to the data path when the control signal for the address conversion is present.
With the step according to the invention as a whole the following function sequence results: the addressing compatibility device is switched into the data path of a processor having a control unit address which is not identical to the control unit address of the peripheral device. The addressing generator is set to the two designated control unit addresses. If the processor responds to the designated peripheral address the addressing compatibility device identifies the control unit address because the latter was preset in the addressing generator, said device blocking the normal data path and applying the control unit address of the peripheral device preset in the address generator to the address/data bus.
With the measure according to the invention, the computer or processor into the data path of which the addressing compatibility circuit is switched can respond to the peripheral device as if the control unit address of the processor coincided with the address of the peripheral unit. The circuit must be implemented in such a manner that the timing is observed in accordance with the interface specifications.
The electronic address monitoring device can be installed into a conventional channel switch or into any other suitable device or be available on its own.
Examples of the invention will now be explained in detail by way of example with the aid of the attached drawings, wherein:
FIG. 1 shows the prior art hitherto,
FIG. 2 shows the principle of the invention,
FIG. 3 is a basic circuit diagram of the addressing compatibility device,
FIG. 4 is an equivalent circuit diagram of an address in logic and an address out logic.
FIG. 1 shows an example of a computer system consisting of the processors 1 and 2 which are not of the same type, a magnetic tape terminal device 3, the data paths 4 and 5 and the magnetic tape devices 6 and 7. The computer or processor 1 operates via the data path 4 with the magnetic tape device 6 with the control unit address `8` and the processor 2 operates via the magnetic terminal device 3 and the data path 5 with the magnetic tape device 7 with the control unit address `7`. Although the magnetic tape device 7 can be switched with a conventional channel switch from the data path 5 to the data path 4 it is supported as regards software only by the processor 2. This is the state of the art.
FIG. 2 shows an example of a heterogeneous computer system in which in particular an address converter 9 is switched into the data path 4 of the processor 1. The device 8 in which the data paths 4 and 5 are combined to a data path 10 permits together with the device 9 software support of the magnetic tape device 7 by both the computers 1 and 2. In the Figures identical reference numerals are employed for elements having the same effect.
FIG. 3 shows the basic circuit of an addressing compatibility device for a channel switching system consisting of an address out logic for reading out data as shown in FIG. 3-A and an address in logic for reading in data, to be seen in FIG. 3-B.
The address out logic consists of a detecting device 13a which monitors the address log of the bidirectional address and data bus 11 and of the control bus 12, and control lines 14 and 15 which in the event of the control unit address preset in the addressing generator 19 being applied to the data bus 11 pass a control signal for address conversion to the bus driver 17 and to the addressing logic 18. The bus driver 17 blocks the normal data path for as long as the control signal for address conversion is present on the control line 14 containing an inverter 16. The addressing generator 19 makes the preset address of the peripheral device to be addressed available, said address being stored in the addressing logic 18, and via the auxiliary bus 20 applies the address to the address and data bus 11 when the control signal for the address conversion is present on the control line 15.
The address in logic is closely related to the address out logic. It consists of a detecting device 13b which monitors the addressing log of the bidirectional address and data bus 11 and of the control bus 12 and control lines 21 and 22 which in the event of the control unit address preset in the addressing generator 25 being present on the data bus 11 pass a control signal for address conversion to the bus driver 17 and to the addressing logic 24. The bus driver 17 blocks the normal data path as long as the control signal for the address conversion is present on the control line 21 containing an inverter 23. The addressing generator 25 makes the preset address of the peripheral device to be addressed available, said address being buffered in the addressing logic 24, and applies said address via the auxiliary bus 26 to the address and data bus 11 when the control signal for address conversion is present on the control line 22.
FIG. 4-A shows in the Figure at the top a detail of the electrical equivalent circuit of the address out logic consisting of a group of 4 DIP switches 27a which form the addressing generator for this part of the circuit, 4 pull-up resistances of 1 kOhm 28a, pulling the inputs 2, 4, 6, 8 of the driver chip 29 to high level when the corresponding DIP switch is open; otherwise the potential at the corresponding input of the driver chip 29 is at low level. If the control signal for the address conversion is present on the control line 15 containing the inverter 16 the enable input of the line driver chip 30 is set to high potential and the chip therefore blocked. At the same time the enable inputs 1 and 19 of the driver chip 29 are set and the address generated with the DIP switches 27 is applied via the auxiliary bus 20 to the address/data bus 11. FIG. 4-B shows in the illustration a detail of the electrical equivalent circuit diagram of the address out logic consisting of a group of 4 DIP switches 27a which form the addressing generator for this part of the circuit, 4 pull-up resistances of 1 kOhm 28a which pull the inputs 2, 4, 6, 8 of the driver chip 31 up to high when the corresponding DIP switch is opened; otherwise, the potential at the corresponding input of the driver chip 31 is at low. If the control signal for the address conversion is present on the control line 21 containing the inverter 23 the enable input of the line driver chip 32 is set to low potential and the chip therefore blocked. At the same time the enable input of the driver chip 31 is set and the address generated with the DIP switches 27b is applied via the auxiliary bus 26 to the address/data bus 11.
One example of embodiment of the invention is a computer system which consists of an IBM AS/400 having a magnetic terminal IBM 2604, an IBM/38, a magnetic tape system IBM3430, and the addressing compatibility device which is connected into the data path of one of the two processors.
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|Citing Patent||Filing date||Publication date||Applicant||Title|
|US20080034993 *||Aug 10, 2007||Feb 14, 2008||Heidelberger Druckmaschinen Ag||Method of Controlling Register when Overprinting a Plurality of Separated Colors|
|U.S. Classification||710/3, 710/108|
|Feb 2, 1999||SULP||Surcharge for late payment|
|Feb 2, 1999||FPAY||Fee payment|
Year of fee payment: 4
|Jan 21, 2003||FPAY||Fee payment|
Year of fee payment: 8
|Feb 19, 2003||REMI||Maintenance fee reminder mailed|
|Feb 14, 2007||REMI||Maintenance fee reminder mailed|
|Aug 1, 2007||LAPS||Lapse for failure to pay maintenance fees|
|Sep 18, 2007||FP||Expired due to failure to pay maintenance fee|
Effective date: 20070801