|Publication number||US5453786 A|
|Application number||US 08/348,951|
|Publication date||Sep 26, 1995|
|Filing date||Nov 25, 1994|
|Priority date||Jul 30, 1990|
|Publication number||08348951, 348951, US 5453786 A, US 5453786A, US-A-5453786, US5453786 A, US5453786A|
|Inventors||Robert J. Trent|
|Original Assignee||Mpr Teltech Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (7), Referenced by (27), Classifications (9), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a continuation of application Ser. No. 07/966,194, filed Jan. 29, 1993 now abandoned.
The present invention relates to a method and apparatus for processing image data for transmission along telephone lines and for decoding the processed data after transmission such that the data can be transformed to produce color images of color television quality.
Known systems for transmitting image data along telephone lines are severely limited in the speed at which the data can be transmitted and reassembled at a receiving end. For example, a single frame of a color television quality image contains 512 by 512 by 24 bits and takes approximately 90 seconds to transmit without compression using a 64 kilobit per second standard ISDN B channel. One method to enhance transmission speed is to compress the data according to known transforms and then, after transmission, to decompress the compressed, transmitted data.
A television screen, for example, is divided up into a plurality of individual image units referred to as pixels. For colour images each pixel may contain three separate parameters such as red, green and blue. Each parameter may be defined as to intensity by an eight bit number called a byte. Thus, each pixel is defined by three bytes. In order to process the data efficiently it is useful to treat a block of 8 by 8 pixels known as a "tile". A known technique consists of directing a first tile of an image into a processor and then inputting the first tile into a digital transformer. The tile output modified by the transformer is sent back to the processor where it is further compressed and sent to an output port. The second tile in the image is then sent to the transformer. This process is repeated until all of the image tile have been processed. In such a system the requirement for numerous fetch and other instructions from the processor makes the process impractically slow. Thus, the advantages of transmission speed increase due to compression is offset by the time take to compress and decompress.
Accordingly, it is an object of the invention to provide an improved method of processing imaging data for compression and decompression. It is a further object of the invention to provide a buffer to receive and store data corresponding to an image and then to process the captured data.
According to the invention there is provided a method of processing digital image data such as obtained from a television screen for transmission along telephone lines in a way that the transmitted data can be transformed to produce images in colour. The method includes storing a frame of digital data in a frame buffer, transferring data from said frame buffer to a tile buffer, generating a clock signal, and generating sets of address and control signals in a state machine. The clock signal is applied to a digital transformer while the address and set of control signals are applied to the tile buffer to directly transfer data in the tile buffer to the digital transformer. After the data is transformed in the digital transformer it is returned to the tile buffer where it is used to overwrite the corresponding original data stored in the tile buffer. The latter process is followed by coding the transformed data stored in the tile buffer so as to compress them. The process is repeated until all data in the frame buffer has been compressed.
Preferably, the data is transferred directly to the tile buffer. The clock signal may have a frequency of greater than approximately one megahertz. Advantageously, the digital transforming step applies a discrete cosine transform while the coding is Huffman coding.
An improvement in speed is achieved by utilizing Y, I and Q parameters to define a pixel colour. By alternating I and Q data in each alternate pixel, a saving of 1/3 of the data required to describe the image is achieved without a significant loss of resolution or colour.
The compressing step may include sequentially transferring data in the form of tiles into a tile buffer and performing a discrete cosine transform on each of the tiles wherein each tile is composed of a matrix of 8 by 8 pixels and each pixel being characterized as to colour and intensity. The transformed tiles are then coded in accordance with Huffman Coding.
The tile pixels in the frame buffer are extracted row by row tile by tile until an entire row of tiles has been transferred. commencing from the first row and proceeding in sequence row by row until the last row has been extracted.
The video signals, if in analog form, are first digitized before storing them in the frame buffer. After compressing the data it is transferred to a communication output interface.
The method may also include reversing the order of processing to perform first inverse Huffman Coding on compressed data, followed by inverse Huffman Coding and then transferring the decompressed data to the frame buffer for further transfer to be transformed into analog video signals.
The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as other features and advantages thereof, will be best understood by reference to the detailed description which follow, read in conjunction with the accompanying drawings, wherein:
FIG. 1 is a block diagram of a conventional system for processing image data;
FIG. 2 is a block diagram of a preferred apparatus for processing image data from analog video source such as a television monitor;
FIG. 3(a) and 3(b) are schematic diagrams showing a portion of a row of pixels in a part of the frame buffer to demonstrate their composition for two different choices of parameters to describe colour and intensity;
FIG. 4 is a timing diagram showing the movement of tiles into and out of the discrete cosine transform;
FIG. 5 is a schematic block diagram showing the state machine and its output of address and control signals which govern the flow of data between the frame buffer, the tile buffer and the discrete cosine transform;
FIG. 6 is a table showing the structure of the address bits generated by the state machine which are used to transfer data between the frame buffer, the tile buffer and the discrete cosine transform (DCT); and
FIG. 7 is a block diagram showing a more detailed system corresponding to that shown in FIGS. 2 and 5 hereof.
Referring to FIG. 1 there is shown a conventional system for processing image data received from a video source in analog form on line 12. The signals on line 12 are converted to digital signals by analog to digital converter 14, outputted on line 16 to a frame buffer 17 and then to a processor 18. The processor transmits the data on line 20 to a digital transformer 22 which modifies the data and returns it back to the processor 18 where it is then sent along line 30 to a telephone line for transmission. The digital transformer 22, which performs a discrete cosine transform on tiles made up of a block of 8 pixels by 8 pixels, inputs and outputs its data in a predefined order. This required ordering of the data is determined by the internal structure of the digital transformer 22. The image data received by the processor 18 from the frame buffer 17 are sent to and received from the digital transformer 22 in tiles of 8 pixels by 8 pixels in the order expected by the digital transformer 22. Each tile of image data from the frame buffer 17 is directed through the digital transformer 22 and further processed by the processor 18 in order to compress the image. Although data is compressed by the transformer 22, the time for compression and subsequent decompression on a receiving end (not shown) would offset any advantage due to increased speed of transmission.
Referring to FIG. 2 there is shown a system in accordance with a preferred embodiment of the invention in which analog signals on line 12 are converted to digital signals on line 16 by an analog-to-digital converter 14. The digitized image data from the analog to digital converter 14 is sent on line 16 to a frame buffer 32 in which the image data is temporarily stored or captured. The frame buffer 32 consists of 8 one megabit video dynamic random access memory chips (called "VRAMS") made by Texas Instruments Incorporated which form two image memory units each of 512×512×16 bits capacity. Data in the frame buffer 32 is stored in rows with each block of 8 pixel×8 pixel forming a tile. A first row of tiles ("row 0") is moved into the tile buffer 37 from the frame buffer 32 along line 35 in response to control signals from a state machine 58. The memory 39 of the tile buffer 37 (see FIG. 7) consists of enough high speed static random access memory (SRAM) chips 41 to contain one row of 8 pixel by 8 pixel tiles from the frame buffer 32. The state machine 58 moves the first two tiles in the tile buffer 37 into the digital transformer 36, which in this case is a discrete cosine transform chip manufactured by INMOS in the United Kingdom and sold under part number 1MSA121 (hereinafter referred to as a "DCT"), where they are processed and then transferred back to the tile buffer 37. The state machine 58 presents the individual pixels of each tile to the DCT chip 36 in the order required by the DCT chip 36. In addition, the state machine 58 overwrites each tile in the tile buffer 37 with the resulting DCT coefficients generated by the DCT chip 36. The DCT chip 36 takes 8 pixel×8 pixel tiles, performs a discrete cosine transform, and then outputs the results.
Following the transformation of the first two tiles from the tile buffer 37 through the DCT chip 36, each remaining pair of tiles in the tile buffer 37 is directed through the DCT chip 36 by the state machine 58 until all of the tiles have been transformed and their resulting DCT coefficients are stored back in the tile buffer 37. The DCT coefficients in the tile buffer 37 are then accessed by a digital signal processor (DSP) 42 chip which commences a coefficient to symbol conversion, namely such as Huffman coding, on the data. Other types of conversion are possible. The DSP chip 42 is manufactured by Texas Instruments Incorporated under part number TMS320C25. The resulting compressed data from the DSP 42 is then sent to a communication card 74 and is ultimately sent over a telephone line or stored on a hard disk drive (not shown).
While the DSP chip 42 is performing coefficient to symbol conversion, the state machine 58 begins operation on the second row of tiles (row 1) in the frame buffer 32. It transfers this row of image data to the tile buffer 37 and, once again, runs this data through the DCT chip 36 and deposits the results back in the tile buffer 37 for the DSP 42 to eventually access. Row by row of tiles from the frame buffer 32 are transferred to the tile buffer 37, transformed by the DCT 36, and then directed to the DSP 42 for coefficient to symbol conversion until the entire image, comprised of all 64 rows of tiles, has been compressed. The data movement operations caused by the state machine 58 and the processing by the DSP 42 may occur concurrently so that discrete cosine transformations may occur in parallel with Huffman coding, further increasing the compression speed.
The circuit of FIG. 2 can also receive compressed data on line 44 into the DSP 42 which applies a symbol to coefficient conversion known as reverse Huffman coding. Other types of conversion are also possible. Following operation by the DSP 42, the data is transferred to the tile buffer 37 from which it goes into the DCT 36. The DCT chip 36 is configured to apply an inverse transform and hence decompress the data. The decompressed data is written into the frame buffer 32 from which it can be directed to a desired output.
Referring to FIG. 7 there is shown a more detailed diagram of the imaging system. Here analog video signals received by a daughter card 66 are digitized and sent to shift register 62 which is incorporated into the frame buffer 32 together with the VRAM chip 64. The frame buffer 32 is controlled by a video system controller chip 68 which refreshes the frame buffer 32 and arbitrates access to the frame buffer 32. The DSP 42 has its own discrete memory 43 consisting of 64 kilobytes of high speed static ram memory 41 and 32 Kilobytes of electrically erasable programmable only memory (EPROM) 39. Output from the DSP is through either a communication daughter card 74 or to a host interface 70 couplable to a host computer 72.
Each pixel 46 of frame buffer 32 is shown schematically in FIG. 3(b) as consisting of three parameters such as red 47, green 48 and blue 49. The intensity of each colour component is described by an 8 bit number. Other means of describing the colour and intensity of a pixel may be used. The method employed in the present invention consists of choosing a parameter Y corresponding to intensity and two parameters I and Q which correspond to colour. It is possible with such a choice to reduce the number of bytes required in each pixel from three to two by alternating I and Q in adjacent pixels as shown in FIG. 3(a) without detracting noticeably from the quality of the picture. Thus, each tile consists of an 8 pixel×8 pixel block with each pixel having a number of bits to describe its colour and intensity.
Image data in the frame buffer 32 is stored in a YIQ format. With respect to FIG. 2, when a row of tiles is transferred from the frame buffer 32 to the memory of the tile buffer 37. However, the state machine 58 first sends all of the Y image components of all tiles in the tile buffer 37 through the DCT chip 36, followed by the I then Q components. Once the operation of the DCT chip 36 is complete, the DSP 42 is able to access the DCT coefficients in the tile buffer 37 for all three components Y, I, and Q.
To appreciate the timing of transferring tiles FIG. 4 shows that the first two tiles are transferred sequentially to the DCT 36 and are returned to the tile buffer before the next two tiles are extracted from the frame buffer 32 and placed in the tile buffer 37. Thus, there is a delay of two tiles introduced by the return of processed tiles from the DCT 36.
The operation of the state machine 58, implemented with programmable array logic the chips for which are commonly referred to as PAL's, is controlled by the digital signal processor 42. Upon informing the state machine 58 of the required operation, such as a frame buffer 32 to tile buffer 37 transfer or DCT 36 transformation, by depositing a specific control value in a state machine control register 60 (see FIG. 5), the DSP 42 sends a signal to the state machine 58 informing it to "go". The state machine 58 performs the operation requested by the DSP 42 and, upon completion, sends an "I'm done" signal to the DSP 42. While the state machine 58 is performing an operation the DSP 42 is free to do other tasks.
When performing any transfer operation, as seen in FIG. 5, the state machine 58 must generate address signals for the tile buffer 37 and frame buffer 32 and control signals for the tile buffer 37, frame buffer 32, and DCT chip 36. The address generated by the state machine 58 originates from a group of counters 46 divided into address fields. Each field of addresses may be independently incremented by the state machine 58. The concatenated address fields form the full address used by both the tile buffer 37 and the frame buffer 32 memories. Individual address fields may define the tile number "t", row number "r", and column number "c" transferred at any given time in a state machine operation. By examining a control register 60 of the state machine 58 and the current address of the address fields, the state machine 58 is able to decide the appropriate 37 next address" for the next data transfer and pulses the appropriate increment signal on selected ones of lines 56 to the counters 46 so that that address is generated. The control signals inform the tile buffer 37, frame buffer 32, and DCT chip 36 when to read and write data. They are generated by the state machine 58 by examining the state machine control register 60 and the current state of the state machine 58.
The state machine addresses, shown in detail in FIG. 6, each consist of 13 bits divided up into four different fields. The fields are write "w", row number "r", tile number "t" and column number "c". Together w, r, t, and c produce an address which points to a single pixel or coefficient within the frame buffer 32 or tile buffer 37. The tile field "t" indicates the current tile which is involved-in a state machine transfer. There are 64 Y tiles and 32 of each of the I and Q tiles contained within a row of tiles. Therefore, 6 bits are required to indicate a unique Y field of a tile and 5 bits to indicate a unique I or Q field. The row field "r" indicates the row, numbered from 0 to 7. The value in the single bit write field is used to determine whether a tile buffer "read" or tile buffer "write" will occur during transfers to and from the DCT 36. Because I image components are stored only in even pixels in the frame buffer and Q image components are stored only in odd pixels in the frame buffer, as shown in FIG. 3(b), the arrangement for the I and Q tile and column fields differ from the Y component's tile and column field arrangement.
The state machine carries out the following five different transfer operations:
(1) Transfer of a row of tiles from the frame buffer 32 to the tile buffer 37.
(2) Transfer of a row of tiles from the tile buffer 37 to the frame buffer 32.
(3) Transfer the Y component of the tiles in the tile buffer through the DCT chip 36 and back into the tile buffer 37.
(4) Transfer of the I component of the tiles in the tile buffer 37 tiles through the DCT chip 37 and back into the tile buffer 37.
(5) Transfer of the Q component of the tiles in the tile buffer 37 through the DCT chip 36 and back into the tile buffer 37.
The address generated by the state machine 58 flows to both the tile and frame buffers 37 and 32, respectively. As an example, when setup by the DSP 42 to perform a frame buffer 32 to tile buffer 37 transfer and told to "go", the state machine's address fields are initially all equal to zero. The address is pointing, therefore, to row 0 and column 0 of tile 0, which is the first pixel in both the frame and tile buffers 32 and 37, respectively. A read signal is sent to the frame buffer 32, a write signal is sent to the tile buffer 37 and the first word of image components is transferred directly from frame buffer 32 to the tile buffer 37.
Immediately following the aforementioned pixel transfer, the state machine 58 examines the current state of the address fields and the type of transfer requested. It uses this information to determine the proper "next address" required and strobes the appropriate increment pulses to generate that address. In this case, increment pulse 0 would be strobed resulting in the column field being increased to 1. The second pixel is then transferred directly from the frame buffer 32 to the tile buffer 37 by the state machine 58 by again strobing the appropriate read and write control signals.
The state machine 58 continually strobes the appropriate increment pulses to generate the required address and the read/write control signals to initiate the frame buffer 32 to tile buffer 37 transfer until all pixels in the selected row of tiles in the frame buffer 32 have been transferred to the tile buffer 37. The full address sent to both the frame buffer 32 and tile buffer 37 is simply incremented by one for each pixel transfer, in a frame buffer 32 to tile buffer 37 transfer, until the state machine 58 detects that the last transfer (the 4095th pixel) has been accomplished. At this time, the state machine 58 sends an "I'm done" signal to the DSP 42 to indicate the completion of the requested operation.
When the state machine 58 is conditioned by the DSP 42 to transfer data to or from the DCT 36 and told to "go", for each DCT chip 36 clock cycle, the state machine 58 must send an expected pixel or coefficient of data to or cause the tile buffer 37 to receive it from the DCT chip 36. The DCT chip 36 requires input and output data to be handled in a strict order. For example, the DCT chip 36 requires data to be presented to it row by row within a give tile. The state machine is able to generate the proper address by examining the type of DCT operation in progress (Y, I, or Q) and the current state of the address field. The address initially points to row and column 0 of tile 0. As data is transferred from the tile buffer 37 to the DCT chip 36, the column address field is first incremented until it reaches a maximum, i.e. 7. For the next transfer the column address field is reset and the row field is incremented. Eventually, when both the column and row address field reach their maximum value, they are reset and the tile field is incremented. Using this technique to generate the address flowing to the tile buffer 37, the DCT chip 36, is able to receive tile input data in the appropriate order. Output data from the DCT chip 35, directed to the tile buffer 37, is stored back in the appropriate tile, column, and row address locations using the same address generation technique. The write field indicates whether a tile buffer to DCT chip or DCT chip 36 to tile buffer 37 data transfer is currently occurring. Once all tiles within the tile buffer 37 have been directed through the DCT chip 36, the state machine 58 sends an "I'm done" signal to the DSP.
It is possible to use adaptive Huffman Coding rather than Huffman Coding. However, in the latter case it would require transferring back transformed data after operation of the DCT into the frame buffer as adaptive Huffman Coding requires that the whole of the intermediate results be looked at.
Accordingly, while this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.
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|U.S. Classification||375/240.01, 375/E07.226, 375/240.2|
|International Classification||H04N11/04, H04N7/30|
|Cooperative Classification||H04N11/044, H04N19/60|
|European Classification||H04N11/04B1, H04N7/30|
|May 19, 1997||AS||Assignment|
Owner name: IBM CANADA LTD., CANADA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MPR TELTECH, LTD.;REEL/FRAME:008639/0903
Effective date: 19961001
|Jun 16, 1997||AS||Assignment|
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:IBM CANADA LTD.;REEL/FRAME:008595/0729
Effective date: 19970523
|Dec 2, 1998||FPAY||Fee payment|
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|Dec 11, 2002||FPAY||Fee payment|
Year of fee payment: 8
|Nov 20, 2006||FPAY||Fee payment|
Year of fee payment: 12