Publication number | US5461337 A |

Publication type | Grant |

Application number | US 08/183,612 |

Publication date | Oct 24, 1995 |

Filing date | Jan 18, 1994 |

Priority date | Jan 18, 1994 |

Fee status | Paid |

Publication number | 08183612, 183612, US 5461337 A, US 5461337A, US-A-5461337, US5461337 A, US5461337A |

Inventors | Davy H. Choi |

Original Assignee | Texas Instruments Incorporated |

Export Citation | BiBTeX, EndNote, RefMan |

Patent Citations (6), Referenced by (1), Classifications (13), Legal Events (4) | |

External Links: USPTO, USPTO Assignment, Espacenet | |

US 5461337 A

Abstract

A source of equally spaced timing signals which includes a first signal source providing a first signal tracing an essentially exponential voltage curve, a second signal source including a transistor having a control electrode and an electron flow path therethrough having a voltage drop V_{BE} thereacross, a voltage source providing a voltage V_{CC} coupled to one end of the electron flow path, a resistance R_{L} coupled between the control electrode and the voltage source, the other end of the flow path providing a second voltage signal in accordance with the equation V_{i} =V_{H} -I_{i} R_{L} for i=1 to n where I_{i} =(V_{H} /R_{L})(1-e^{-i}α) and V_{H} =V_{CC} -V_{BE} and a comparator providing a timing signal whenever the second voltage signal is greater than the first signal.

Claims(13)

1. A source of equally spaced timing signals, comprising:

a first voltage signal source providing a voltage tracing an essentially exponential voltage;

a second voltage signal source providing a voltage V_{i} =V_{H} -I_{i} R_{L} coupled to a current path including a transistor having a control electrode;

an electron flow path therethrough controlled by said control electrode; and

a voltage drop V_{BE} between said control electrode and said electron flow path;

a resistance R_{L} disposed between a third voltage source V_{CC} and said control electrode; and

a current generator coupled between said control electrode and a reference voltage source which provides a current I_{i} at said control electrode according to the equation for i=1 to n time intervals of: I_{i} -(V_{H} /R_{L}) (1-e^{-i}α) where α=IR_{L} /2V_{T} and V_{H} =V_{CC} -V_{BE} ; and

a comparator providing a timing signal whenever said voltage V_{i} becomes greater than said essentially exponential voltage.

2. A source as set forth in claim 1, further including a current source disposed between said current path and said reference voltage source providing said voltage V_{i} =V_{H} -I_{i} R_{L} at said current path.

3. A source as set forth in claim 1, further including means to vary the value of i.

4. A source as set forth in claim 3, wherein said means to vary the value of i is a decoder,

5. A source of equally spaced timing signals, comprising:

a first signal source providing a first signal tracing an essentially exponential voltage curve;

a electrode:

a electron flow path coupled to said electrode;

a resistance R_{L} disposed between a voltage source and said electrode:

a second signal source providing a second voltage signal in accordance with the equation V_{i} =V_{H} -I_{i} R_{L} for i=1 to n where I_{i} =(V_{H} /R_{L}) (1-e^{-i}α) and V_{H} =V_{CC} -V_{BE} and V_{BE} is a base to emitter voltage drop of a transistor coupled to said second signal source; and

a comparator providing a timing signal whenever said second voltage signal becomes greater than said first signal.

6. The source of claim 5, wherein said electrode is a control electrode and said electron flow path is formed between said control electrode and said second signal source, said transistor having a voltage drop V_{BE} thereacross, said voltage source V_{CC} being coupled to one end of said electron flow path, and where in said resistance R_{L} is coupled between said control electrode and said voltage source, the other end of said flow path providing a second voltage signal to said control electrode in accordance with the equation V_{i} -V_{H} -I_{i} R_{L} for i=1 to n where I_{i} =(V_{H} /R_{L}) (1-e^{-i}α) and V_{H} =V_{CC} -V_{BE}.

7. A source as set forth in claim 6, further including a current source disposed between said voltage source and said control electrode to provide a current I_{B} =(V_{H} /R_{L})e^{-i}α between said voltage source and said control electrode and a current source between said control electrode and a source of reference voltage to provide a current I_{A} =V_{H} /R_{L}.

8. A source as set forth in claim 5, further including means to vary the value of i.

9. A source as set forth in claim 8, wherein said means to vary the value of i is a decoder.

10. A source as set forth in claim 6, further including means to vary the value of i.

11. A source as set forth in claim 10, wherein said means to vary the value of i is a decoder.

12. A source as set forth in claim 7, further including means to vary the value of i.

13. A source as set forth in claim 12, wherein said means to vary the value of i is a decoder.

Description

This invention relates to a system for providing indicia of linear or equally spaced time position variations, particularly for use in conjunction with write precompensation circuits to compensate for bit shift.

There has been a problem in the prior art in obtaining timing signals having equal spacing therebetween in general and particularly in connection with write precompensation circuits. Write precompensation circuitry is provided to compensate for the bit shift caused by the intersymbol interference. In order to increase disk storage capacity, adjacent stored bits are placed very close together. The "1" bits are represented by alternating magnetic fluxes with the peak positions representing the data information. When two signals are superimposed upon each other, a composite of the two signals is obtained. This causes a shift of the peak position from the ideal. In the past, one way of compensating for this peak shift problem has been to write the data closer together than required by a certain amount at first so that the peak shift process would push the adjacent bits apart later and cause the final peaks to be in the idealized location. A discussion of this problem is set forth in Electronics, Apr. 21, 1982 at page 111.

A prior art write compensation circuit is shown by the block diagram implementation in FIG. 1 which recognizes specific write data patterns and can add or subtract delays in the time position of write data bits to counteract the read back bit shift. In this prior art circuit, all of the circuitry including pads WCS and WO bar are on a single chip and capacitor C and resistance R are off chip. The magnitude of the time shift of the signal, which is at the output at the WO bar pad, is determined by the RC network composed of resistance R and capacitor C which are external to the chip in accordance with the equation:

TPC=WPαR(C+C_{S}) (1)

where TPC is time position compensation, α is a constant that provides the best fit of measured results, C_{S} is stray capacitance at the WCS pad and, for example, WP=-3, -2, -1, 0, +1, +2, +3.

In the circuit of FIG. 1, a digital write data signal is provided by a digital write data circuit 2 and provides an output signal shown in FIG. 2 as WCS, this signal being applied to the positive input of a comparator 4. A digital to analog converter (DAC) 6 generates, for example, seven different DC levels or WP in the above equation, one at a time, at the negative input of the comparator 4 whose output is the WO bar output as shown in the timing diagram in FIG. 2.

As can be seen in FIG. 2, the WO bar signal is high until the voltage level at the negative input of the comparator 4 provided by the DAC is the same as or higher than the voltage level from the circuit 2. The DAC 6 generates the seven different voltage levels at seven different time positions.

Only the falling or trailing edges of signals at the WCS and WO bar pads are used for timing. As can be seen in FIG. 2, the WCS signal follows an exponential decay waveform, this occurring only when transistor Q_{1} of FIG. 1 is turned off due to the presence of the R and C components which are external to the chip. This is the case for a data bit "1" where current I is switched on. Essentially, the timing shift only applies to a data bit "1" as explained above. Thus, the output level of DAC 6 has to be moved in a nonlinear but controlled fashion in order to obtain "equal" time steps as the DAC output changes, this corresponding to the WP parameter stepping through the seven steps from -3 to +3 as stated in the TPC equation (1) supra. This has been a problem in the prior art.

In accordance with the present invention, the above described problem is resolved and there is provided a DAC which is capable of providing a nonlinear output to compensate for the nonlinearity in the output of the digital data write circuit 2.

The voltage V_{WCS} on the WCS pad in FIG. 1 is shown in FIG. 3 as a solid trace which decays exponentially from V_{H}, where V_{H} is V_{CC} -V_{BE}, V_{CC} is the supply voltage and V_{BE} is the base to emitter voltage of a bipolar transistor in an ECL circuit. V_{H} is defined in the output stage of an ECL-type circuit shown in FIG. 1 as follows: The current I is turned on or off, depending upon the logic state of the circuit. The highest output voltage is obtained when I=0, in which case the voltage at pad WCS is V_{out} =(V_{CC} -IR_{1} -V_{BE})=(V_{CC} -V_{BE}), where R_{1} is the load resistance at the base of transistor Q_{1}. V_{WCS} is described by the following equation as a function of time t:

V_{WCS}=V_{H}exp(-t/(R C_{T}))

where C_{T} =C+C_{S} (stray capacitance).

As the output voltage of DAC 6 (V_{1} . . . V_{7} or V_{i} of FIG. 3) intersects V_{WCS} at different points, seven coordinates are generated which are represented as (t_{i}, V_{i}) where i=1 to 7 as shown in FIG. 3. In order to match this nonlinearity of the output at pad WCS from the circuit 2, the DAC output stage is constructed as shown in FIG. 1, where R_{L} is the load resistance. V_{i} represents seven equations since the largest "i" in this example is 7 and "i" represents n equations when i=n and is thus described by the equation:

V_{i}=V_{CC}-I_{i}R_{L}-V_{BE}=V_{H}-I_{i}R_{L}. (2)

There is a one-to-one mapping between I_{i} and V_{i} as indicated in the above equation. V_{i} is defined to be V_{1} for I_{1}, V_{2} for I_{2}, etc. The purpose of this mathematical analysis is to find the requirements on I_{i} in generating V_{i} so that seven equal time intervals are provided and defined by (t_{i} -t_{i-1}) for i=1 to 7 and t_{o} =0 or, more generally, n equal time intervals for i=1 to n.

At intersection points, V_{WCS} =V_{i} and the above V_{WCS} equation in V_{i} generates a set of seven equations for i=1 to 7 as follows:

V_{i}=V_{H}exp(-t_{i}/(R C_{T}))

or

t_{i}=R C_{T}1n(V_{H}/V_{i}).

Equating consecutive time intervals, i.e., t_{2} -t_{1} =t_{1}, t_{3} -t_{2} =t_{2} -t_{1}, etc., results in six equations for i=1 to 6 with V_{o} =V_{H}. Accordingly,

V_{i}V_{i}=V_{i-1}V_{i+1}( 3)

The above TPC equation (1) is evaluated for one time interval to obtain the equation t_{1} =αR C_{T}. With V_{1} =V_{H} exp (-t_{1} /(R C_{T})), there is derived the equation:

V_{1}=V_{H}e^{-}α. ( 4)

Manipulation of the equations (2), (3) and (4) results in the equation for i=1 to 7 of:

I_{i}=(V_{H}/R_{L})(1-e^{-i}α).

Therefore, the requirements on I_{i} for the generation of equal time steps used in write precompensation applications are provided and it is merely necessary to substitute a DAC circuit for the prior art DAC 6 of FIG. 1 which operates according to the equation for i=1 to n of:

I_{i}=(V_{H}/R_{L})(1-e^{-i}α).

FIG. 1 is a block diagram of a prior art write compensation circuit;

FIG. 2 is a timing diagram showing the operation of the write precompensation circuit of FIG. 1;

FIG. 3 is a timing diagram showing the intersections of the V_{WCS} waveform and the DAC output V_{i} as V_{i} moves from V_{1} to V_{7}, generating seven equal time intervals;

FIG. 4 is a block diagram implementation of linear time variations based upon the equation I_{i} =(V_{H} /R_{L})(1-e^{-i}α) for i=1 to 7;

FIG. 5 is a circuit diagram showing the generation of the currents used in FIG. 6 in accordance with the present invention; and FIG. 6 is a circuit diagram of a DAC which can be used in accordance with the present invention.

A block diagram implementation of linear time position variations based upon the equation I_{i} =(V_{H} /R_{L})(1-e^{-i}α) which is equation (5) above is shown in FIG. 4. A reference current sink circuit 11 is provided which operates in accordance with the equation I_{A} =V_{H} /R_{L}. A 3-bit decoder 13 generates the index i for i=1 to 7 according to the decoding scheme interpreting specific write data patterns. The 3-bit decoder controls a current source circuit 15 which operates in accordance with the equation I_{B} =(V_{H} /R_{L})e^{-i}α. Therefore, a net current I_{i} =I_{A} -I_{B} is provided to control the transistor 17, the emitter of which is the output of the DAC, V_{i} for i=1 to 7 and I_{i} =(V_{H} /R_{L})(1-e^{-i}α). The matching characteristics of this type of circuit are met in a monolithic integrated circuit. This circuit is utilized in the circuit of FIG. 1 in place of the DAC 6 therein to provide the equally spaced timing pulses in accordance with the equations as set forth hereinabove.

Referring now to FIG. 5, there is shown a circuit diagram of an exponential current generator in accordance with the present invention. This circuit includes two inputs, iI and I_{R} and one output, I_{R} +I_{exp}. The input iI is coupled to the base of an NPN transistor Q_{11} and then, through a resistance R_{3} to the base and collector of an NPN transistor Q_{13}. The emitter of transistor Q_{13} is the output I_{R} +I_{exp}. The input I_{R} is coupled to the collector of transistor Q_{11}, the emitter of which is coupled to the output I_{R} + I_{exp}. The input I_{R} is also coupled to the gate of transistor N_{1}, the current path of transistor N_{1} being coupled between V_{CC} potential and the collector of transistor Q_{13}.

The equations describing the circuit of FIG. 5 are as follows:

(iI)R_{3}+V_{BE2}=V_{BE1}

I_{R}=I_{S}exp (V_{BE1}/V_{T})

I_{exp}=I_{S}exp(V_{BE2}/V_{T})

where V_{BE1} is the base to emitter voltage of transistor Q_{11}, V_{BE2} is the base to emitter voltage of transistor Q_{13}, I_{S} is the saturation current of a bipolar transistor and V_{T} =kT/q, where k is Boltzmann's constant, T is the absolute temperature and q is the charge of an electron.

The above equations can be simplified into:

I_{exp}=I_{R}exp(-((iI)R_{3})/V_{T})

Therefore, the output current is given by:

I_{R}+I_{exp}=I_{R}[1+exp(-((iI)R_{3})/V_{T})](6)

Transistor N_{1} biases the collector of transistor Q_{11} at a sufficiently high voltage to ensure that transistor Q_{11} operates in its saturation region.

Referring now to FIG. 6, there is shown a schematic diagram of a circuit which provides the currents as set forth in FIG. 4 and which can be used as a DAC in accordance with the present invention.

The exponential current generator described in conjunction with FIG. 5 is incorporated into the circuit of FIG. 6. Current iI is forced into resistance R_{3} and current I_{R} is forced into transistor Q_{11}. Transistors Q_{10} and Q_{12} are added to the circuit of FIG. 5 to minimize base current errors. The sum of the emitter currents from transistors Q_{11} and Q_{13} is given by the equation:

I_{R}+I_{exp}=I_{R}[1+exp(-((iI)R_{3})/2V_{T})](7)

This equation is different from equation (6) above by a "2" factor which is present to account for the addition of transistors Q_{10} and Q_{12}.

A reference current I_{R} is provided by placing resistance R_{1} =R_{L} and the base to emitter voltage V_{BE} of transistor Q_{16} between V_{CC} and ground or reference voltage. Thus, current I_{R} =(V_{CC} -V_{BE})/R_{L} flows through transistor Q_{16}. The two current mirrors, transistors Q_{15} /Q_{16} and transistors P_{3} /P_{4} then force current I_{R} into transistor P_{3} as well. Another 2× current mirror composed of transistors Q_{14} /Q_{16} (the size of transistor Q_{14} is twice that of transistor Q_{16}) forces a current 2I_{R} into transistor Q_{14} as shown in FIG. 6.

Transistor Q_{1} to Q_{9} and resistances R_{4} to R_{6} form a standard digital to analog converter (DAC). By ratioing transistors Q_{7} to Q_{9} and resistances R_{4} to R_{6} appropriately, a current I is provided in transistor Q_{7}, a current 2I is provided in transistor Q_{8} and a current 4I is provided in transistor Q_{9}. The three switches, Q_{1} /Q_{2}, Q_{3} /Q_{4} and Q_{5} /Q_{6} are controlled by signals A/A--, B/B-- and C/C-- respectively. Depending upon the logic states of signals A, B and C, there will be a signal current 0, I, 2I, . . . , 7I passing through transistor P_{1}, this current being referred to herein as iI, where i=0, 1, 2, . . . , 7. The current mirror P_{1} /P_{2} then forces iI into transistor P_{2}.

As discussed above, with current iI from transistor P_{2} travelling through resistance R_{3} and current I_{R} travelling from transistor P_{3} into transistor Q_{11}, the current (I_{R} +I_{exp}) described by equation (7) is provided at the node 1 junction as shown in FIG. 6. Also, as previously demonstrated, there is a current 2I_{R} leaving the node 1 junction and entering transistor Q_{14}. Summing currents at node 1 results in:

I_{R}+I_{exp}+I_{out}=2 I_{R}##EQU1## where

α=IR_{3}/2V_{T}. (9)

It is apparent that the current I_{out} as set forth in equation (8) is identical to current I_{i} set forth in equation (5) and shown in FIG. 4.

Transistor N_{2} isolates node 1 from the base of transistor Q_{17}. The gate of transistor N_{2} or node 2 is biased up by transistor N_{3} and Q_{18} to replicate the connection of transistors N_{2} /Q_{14}. The current mirror composed of transistors P_{2} /P_{5} forces current iI into transistor N_{3}. As the index i increases, current iI increases, this, in turn, increasing the current I_{out} in accordance with equation (8). As a result, node 2 moves up due to the increased current iI in transistor N_{3} and increased current I_{out} in transistor N_{2}. Accordingly, the output stage bias maintains its proper balance.

It is desirable that the coefficient α given by equation (9) be temperature invariant. As shown in FIG. 6, current I is set up as:

I=(V_{BG}-V_{BE})/R (10)

where V_{BG} is a temperature-invariant bandgap reference voltage. Since V_{BE} has a negative temperature coefficient, current I as shown in equation (10) will increase as temperature increases. Because V_{T} =kT/q also increases with temperature, α will be temperature invariant.

Though the invention has been described with respect to a specific preferred embodiment thereof, many variations and modifications will immediately become apparent to those skilled in the art. It is therefore the intention that the appended claims be interpreted as broadly as possible in view of the prior art to include all such variations and modification.

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Referenced by

Citing Patent | Filing date | Publication date | Applicant | Title |
---|---|---|---|---|

US5952867 * | Nov 17, 1997 | Sep 14, 1999 | Texas Instruments Incorporated | Exponentiator circuit and method for generating decibel steps of programmable current gain |

Classifications

U.S. Classification | 327/346, 327/58, 327/63, G9B/20.011 |

International Classification | H03K5/24, G11B20/10, H03K5/13 |

Cooperative Classification | G11B20/10194, H03K5/24, H03K5/131 |

European Classification | G11B20/10A6B, H03K5/13B, H03K5/24 |

Legal Events

Date | Code | Event | Description |
---|---|---|---|

Jan 18, 1994 | AS | Assignment | Owner name: TEXAS INSTRUMENTS INCORPORATED, TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CHOI, DAVY H.;REEL/FRAME:006848/0291 Effective date: 19931209 |

Mar 30, 1999 | FPAY | Fee payment | Year of fee payment: 4 |

Mar 28, 2003 | FPAY | Fee payment | Year of fee payment: 8 |

Mar 20, 2007 | FPAY | Fee payment | Year of fee payment: 12 |

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