US 5461337 A
A source of equally spaced timing signals which includes a first signal source providing a first signal tracing an essentially exponential voltage curve, a second signal source including a transistor having a control electrode and an electron flow path therethrough having a voltage drop VBE thereacross, a voltage source providing a voltage VCC coupled to one end of the electron flow path, a resistance RL coupled between the control electrode and the voltage source, the other end of the flow path providing a second voltage signal in accordance with the equation Vi =VH -Ii RL for i=1 to n where Ii =(VH /RL)(1-e-iα) and VH =VCC -VBE and a comparator providing a timing signal whenever the second voltage signal is greater than the first signal.
1. A source of equally spaced timing signals, comprising:
a first voltage signal source providing a voltage tracing an essentially exponential voltage;
a second voltage signal source providing a voltage Vi =VH -Ii RL coupled to a current path including a transistor having a control electrode;
an electron flow path therethrough controlled by said control electrode; and
a voltage drop VBE between said control electrode and said electron flow path;
a resistance RL disposed between a third voltage source VCC and said control electrode; and
a current generator coupled between said control electrode and a reference voltage source which provides a current Ii at said control electrode according to the equation for i=1 to n time intervals of: Ii -(VH /RL) (1-e-iα) where α=IRL /2VT and VH =VCC -VBE ; and
a comparator providing a timing signal whenever said voltage Vi becomes greater than said essentially exponential voltage.
2. A source as set forth in claim 1, further including a current source disposed between said current path and said reference voltage source providing said voltage Vi =VH -Ii RL at said current path.
3. A source as set forth in claim 1, further including means to vary the value of i.
4. A source as set forth in claim 3, wherein said means to vary the value of i is a decoder,
5. A source of equally spaced timing signals, comprising:
a first signal source providing a first signal tracing an essentially exponential voltage curve;
a electron flow path coupled to said electrode;
a resistance RL disposed between a voltage source and said electrode:
a second signal source providing a second voltage signal in accordance with the equation Vi =VH -Ii RL for i=1 to n where Ii =(VH /RL) (1-e-iα) and VH =VCC -VBE and VBE is a base to emitter voltage drop of a transistor coupled to said second signal source; and
a comparator providing a timing signal whenever said second voltage signal becomes greater than said first signal.
6. The source of claim 5, wherein said electrode is a control electrode and said electron flow path is formed between said control electrode and said second signal source, said transistor having a voltage drop VBE thereacross, said voltage source VCC being coupled to one end of said electron flow path, and where in said resistance RL is coupled between said control electrode and said voltage source, the other end of said flow path providing a second voltage signal to said control electrode in accordance with the equation Vi -VH -Ii RL for i=1 to n where Ii =(VH /RL) (1-e-iα) and VH =VCC -VBE.
7. A source as set forth in claim 6, further including a current source disposed between said voltage source and said control electrode to provide a current IB =(VH /RL)e-iα between said voltage source and said control electrode and a current source between said control electrode and a source of reference voltage to provide a current IA =VH /RL.
8. A source as set forth in claim 5, further including means to vary the value of i.
9. A source as set forth in claim 8, wherein said means to vary the value of i is a decoder.
10. A source as set forth in claim 6, further including means to vary the value of i.
11. A source as set forth in claim 10, wherein said means to vary the value of i is a decoder.
12. A source as set forth in claim 7, further including means to vary the value of i.
13. A source as set forth in claim 12, wherein said means to vary the value of i is a decoder.
This invention relates to a system for providing indicia of linear or equally spaced time position variations, particularly for use in conjunction with write precompensation circuits to compensate for bit shift.
There has been a problem in the prior art in obtaining timing signals having equal spacing therebetween in general and particularly in connection with write precompensation circuits. Write precompensation circuitry is provided to compensate for the bit shift caused by the intersymbol interference. In order to increase disk storage capacity, adjacent stored bits are placed very close together. The "1" bits are represented by alternating magnetic fluxes with the peak positions representing the data information. When two signals are superimposed upon each other, a composite of the two signals is obtained. This causes a shift of the peak position from the ideal. In the past, one way of compensating for this peak shift problem has been to write the data closer together than required by a certain amount at first so that the peak shift process would push the adjacent bits apart later and cause the final peaks to be in the idealized location. A discussion of this problem is set forth in Electronics, Apr. 21, 1982 at page 111.
A prior art write compensation circuit is shown by the block diagram implementation in FIG. 1 which recognizes specific write data patterns and can add or subtract delays in the time position of write data bits to counteract the read back bit shift. In this prior art circuit, all of the circuitry including pads WCS and WO bar are on a single chip and capacitor C and resistance R are off chip. The magnitude of the time shift of the signal, which is at the output at the WO bar pad, is determined by the RC network composed of resistance R and capacitor C which are external to the chip in accordance with the equation:
where TPC is time position compensation, α is a constant that provides the best fit of measured results, CS is stray capacitance at the WCS pad and, for example, WP=-3, -2, -1, 0, +1, +2, +3.
In the circuit of FIG. 1, a digital write data signal is provided by a digital write data circuit 2 and provides an output signal shown in FIG. 2 as WCS, this signal being applied to the positive input of a comparator 4. A digital to analog converter (DAC) 6 generates, for example, seven different DC levels or WP in the above equation, one at a time, at the negative input of the comparator 4 whose output is the WO bar output as shown in the timing diagram in FIG. 2.
As can be seen in FIG. 2, the WO bar signal is high until the voltage level at the negative input of the comparator 4 provided by the DAC is the same as or higher than the voltage level from the circuit 2. The DAC 6 generates the seven different voltage levels at seven different time positions.
Only the falling or trailing edges of signals at the WCS and WO bar pads are used for timing. As can be seen in FIG. 2, the WCS signal follows an exponential decay waveform, this occurring only when transistor Q1 of FIG. 1 is turned off due to the presence of the R and C components which are external to the chip. This is the case for a data bit "1" where current I is switched on. Essentially, the timing shift only applies to a data bit "1" as explained above. Thus, the output level of DAC 6 has to be moved in a nonlinear but controlled fashion in order to obtain "equal" time steps as the DAC output changes, this corresponding to the WP parameter stepping through the seven steps from -3 to +3 as stated in the TPC equation (1) supra. This has been a problem in the prior art.
In accordance with the present invention, the above described problem is resolved and there is provided a DAC which is capable of providing a nonlinear output to compensate for the nonlinearity in the output of the digital data write circuit 2.
The voltage VWCS on the WCS pad in FIG. 1 is shown in FIG. 3 as a solid trace which decays exponentially from VH, where VH is VCC -VBE, VCC is the supply voltage and VBE is the base to emitter voltage of a bipolar transistor in an ECL circuit. VH is defined in the output stage of an ECL-type circuit shown in FIG. 1 as follows: The current I is turned on or off, depending upon the logic state of the circuit. The highest output voltage is obtained when I=0, in which case the voltage at pad WCS is Vout =(VCC -IR1 -VBE)=(VCC -VBE), where R1 is the load resistance at the base of transistor Q1. VWCS is described by the following equation as a function of time t:
VWCS =VH exp(-t/(R CT))
where CT =C+CS (stray capacitance).
As the output voltage of DAC 6 (V1 . . . V7 or Vi of FIG. 3) intersects VWCS at different points, seven coordinates are generated which are represented as (ti, Vi) where i=1 to 7 as shown in FIG. 3. In order to match this nonlinearity of the output at pad WCS from the circuit 2, the DAC output stage is constructed as shown in FIG. 1, where RL is the load resistance. Vi represents seven equations since the largest "i" in this example is 7 and "i" represents n equations when i=n and is thus described by the equation:
Vi =VCC -Ii RL -VBE =VH -Ii RL. (2)
There is a one-to-one mapping between Ii and Vi as indicated in the above equation. Vi is defined to be V1 for I1, V2 for I2, etc. The purpose of this mathematical analysis is to find the requirements on Ii in generating Vi so that seven equal time intervals are provided and defined by (ti -ti-1) for i=1 to 7 and to =0 or, more generally, n equal time intervals for i=1 to n.
At intersection points, VWCS =Vi and the above VWCS equation in Vi generates a set of seven equations for i=1 to 7 as follows:
Vi =VH exp(-ti /(R CT))
ti =R CT 1n(VH /Vi).
Equating consecutive time intervals, i.e., t2 -t1 =t1, t3 -t2 =t2 -t1, etc., results in six equations for i=1 to 6 with Vo =VH. Accordingly,
Vi Vi =Vi-1 Vi+1 ( 3)
The above TPC equation (1) is evaluated for one time interval to obtain the equation t1 =αR CT. With V1 =VH exp (-t1 /(R CT)), there is derived the equation:
V1 =VH e-α. ( 4)
Manipulation of the equations (2), (3) and (4) results in the equation for i=1 to 7 of:
Ii =(VH /RL)(1-e-iα).
Therefore, the requirements on Ii for the generation of equal time steps used in write precompensation applications are provided and it is merely necessary to substitute a DAC circuit for the prior art DAC 6 of FIG. 1 which operates according to the equation for i=1 to n of:
Ii =(VH /RL)(1-e-iα).
FIG. 1 is a block diagram of a prior art write compensation circuit;
FIG. 2 is a timing diagram showing the operation of the write precompensation circuit of FIG. 1;
FIG. 3 is a timing diagram showing the intersections of the VWCS waveform and the DAC output Vi as Vi moves from V1 to V7, generating seven equal time intervals;
FIG. 4 is a block diagram implementation of linear time variations based upon the equation Ii =(VH /RL)(1-e-iα) for i=1 to 7;
FIG. 5 is a circuit diagram showing the generation of the currents used in FIG. 6 in accordance with the present invention; and FIG. 6 is a circuit diagram of a DAC which can be used in accordance with the present invention.
A block diagram implementation of linear time position variations based upon the equation Ii =(VH /RL)(1-e-iα) which is equation (5) above is shown in FIG. 4. A reference current sink circuit 11 is provided which operates in accordance with the equation IA =VH /RL. A 3-bit decoder 13 generates the index i for i=1 to 7 according to the decoding scheme interpreting specific write data patterns. The 3-bit decoder controls a current source circuit 15 which operates in accordance with the equation IB =(VH /RL)e-iα. Therefore, a net current Ii =IA -IB is provided to control the transistor 17, the emitter of which is the output of the DAC, Vi for i=1 to 7 and Ii =(VH /RL)(1-e-iα). The matching characteristics of this type of circuit are met in a monolithic integrated circuit. This circuit is utilized in the circuit of FIG. 1 in place of the DAC 6 therein to provide the equally spaced timing pulses in accordance with the equations as set forth hereinabove.
Referring now to FIG. 5, there is shown a circuit diagram of an exponential current generator in accordance with the present invention. This circuit includes two inputs, iI and IR and one output, IR +Iexp. The input iI is coupled to the base of an NPN transistor Q11 and then, through a resistance R3 to the base and collector of an NPN transistor Q13. The emitter of transistor Q13 is the output IR +Iexp. The input IR is coupled to the collector of transistor Q11, the emitter of which is coupled to the output IR + Iexp. The input IR is also coupled to the gate of transistor N1, the current path of transistor N1 being coupled between VCC potential and the collector of transistor Q13.
The equations describing the circuit of FIG. 5 are as follows:
(iI)R3 +VBE2 =VBE1
IR =IS exp (VBE1 /VT)
Iexp =IS exp(VBE2 /VT)
where VBE1 is the base to emitter voltage of transistor Q11, VBE2 is the base to emitter voltage of transistor Q13, IS is the saturation current of a bipolar transistor and VT =kT/q, where k is Boltzmann's constant, T is the absolute temperature and q is the charge of an electron.
The above equations can be simplified into:
Iexp =IR exp(-((iI)R3)/VT)
Therefore, the output current is given by:
IR +Iexp =IR [1+exp(-((iI)R3)/VT)](6)
Transistor N1 biases the collector of transistor Q11 at a sufficiently high voltage to ensure that transistor Q11 operates in its saturation region.
Referring now to FIG. 6, there is shown a schematic diagram of a circuit which provides the currents as set forth in FIG. 4 and which can be used as a DAC in accordance with the present invention.
The exponential current generator described in conjunction with FIG. 5 is incorporated into the circuit of FIG. 6. Current iI is forced into resistance R3 and current IR is forced into transistor Q11. Transistors Q10 and Q12 are added to the circuit of FIG. 5 to minimize base current errors. The sum of the emitter currents from transistors Q11 and Q13 is given by the equation:
IR +Iexp =IR [1+exp(-((iI)R3)/2VT)](7)
This equation is different from equation (6) above by a "2" factor which is present to account for the addition of transistors Q10 and Q12.
A reference current IR is provided by placing resistance R1 =RL and the base to emitter voltage VBE of transistor Q16 between VCC and ground or reference voltage. Thus, current IR =(VCC -VBE)/RL flows through transistor Q16. The two current mirrors, transistors Q15 /Q16 and transistors P3 /P4 then force current IR into transistor P3 as well. Another 2× current mirror composed of transistors Q14 /Q16 (the size of transistor Q14 is twice that of transistor Q16) forces a current 2IR into transistor Q14 as shown in FIG. 6.
Transistor Q1 to Q9 and resistances R4 to R6 form a standard digital to analog converter (DAC). By ratioing transistors Q7 to Q9 and resistances R4 to R6 appropriately, a current I is provided in transistor Q7, a current 2I is provided in transistor Q8 and a current 4I is provided in transistor Q9. The three switches, Q1 /Q2, Q3 /Q4 and Q5 /Q6 are controlled by signals A/A--, B/B-- and C/C-- respectively. Depending upon the logic states of signals A, B and C, there will be a signal current 0, I, 2I, . . . , 7I passing through transistor P1, this current being referred to herein as iI, where i=0, 1, 2, . . . , 7. The current mirror P1 /P2 then forces iI into transistor P2.
As discussed above, with current iI from transistor P2 travelling through resistance R3 and current IR travelling from transistor P3 into transistor Q11, the current (IR +Iexp) described by equation (7) is provided at the node 1 junction as shown in FIG. 6. Also, as previously demonstrated, there is a current 2IR leaving the node 1 junction and entering transistor Q14. Summing currents at node 1 results in:
IR +Iexp +Iout =2 IR ##EQU1## where
α=IR3 /2VT. (9)
It is apparent that the current Iout as set forth in equation (8) is identical to current Ii set forth in equation (5) and shown in FIG. 4.
Transistor N2 isolates node 1 from the base of transistor Q17. The gate of transistor N2 or node 2 is biased up by transistor N3 and Q18 to replicate the connection of transistors N2 /Q14. The current mirror composed of transistors P2 /P5 forces current iI into transistor N3. As the index i increases, current iI increases, this, in turn, increasing the current Iout in accordance with equation (8). As a result, node 2 moves up due to the increased current iI in transistor N3 and increased current Iout in transistor N2. Accordingly, the output stage bias maintains its proper balance.
It is desirable that the coefficient α given by equation (9) be temperature invariant. As shown in FIG. 6, current I is set up as:
I=(VBG -VBE)/R (10)
where VBG is a temperature-invariant bandgap reference voltage. Since VBE has a negative temperature coefficient, current I as shown in equation (10) will increase as temperature increases. Because VT =kT/q also increases with temperature, α will be temperature invariant.
Though the invention has been described with respect to a specific preferred embodiment thereof, many variations and modifications will immediately become apparent to those skilled in the art. It is therefore the intention that the appended claims be interpreted as broadly as possible in view of the prior art to include all such variations and modification.