US 5461337 A Abstract A source of equally spaced timing signals which includes a first signal source providing a first signal tracing an essentially exponential voltage curve, a second signal source including a transistor having a control electrode and an electron flow path therethrough having a voltage drop V
_{BE} thereacross, a voltage source providing a voltage V_{CC} coupled to one end of the electron flow path, a resistance R_{L} coupled between the control electrode and the voltage source, the other end of the flow path providing a second voltage signal in accordance with the equation V_{i} =V_{H} -I_{i} R_{L} for i=1 to n where I_{i} =(V_{H} /R_{L})(1-e^{-i}α) and V_{H} =V_{CC} -V_{BE} and a comparator providing a timing signal whenever the second voltage signal is greater than the first signal.Claims(13) 1. A source of equally spaced timing signals, comprising:
a first voltage signal source providing a voltage tracing an essentially exponential voltage; a second voltage signal source providing a voltage V _{i} =V_{H} -I_{i} R_{L} coupled to a current path including a transistor having a control electrode;an electron flow path therethrough controlled by said control electrode; and a voltage drop V _{BE} between said control electrode and said electron flow path;a resistance R _{L} disposed between a third voltage source V_{CC} and said control electrode; anda current generator coupled between said control electrode and a reference voltage source which provides a current I _{i} at said control electrode according to the equation for i=1 to n time intervals of: I_{i} -(V_{H} /R_{L}) (1-e^{-i}α) where α=IR_{L} /2V_{T} and V_{H} =V_{CC} -V_{BE} ; anda comparator providing a timing signal whenever said voltage V _{i} becomes greater than said essentially exponential voltage.2. A source as set forth in claim 1, further including a current source disposed between said current path and said reference voltage source providing said voltage V
_{i} =V_{H} -I_{i} R_{L} at said current path.3. A source as set forth in claim 1, further including means to vary the value of i.
4. A source as set forth in claim 3, wherein said means to vary the value of i is a decoder,
5. A source of equally spaced timing signals, comprising:
a first signal source providing a first signal tracing an essentially exponential voltage curve; a electrode: a electron flow path coupled to said electrode; a resistance R _{L} disposed between a voltage source and said electrode:a second signal source providing a second voltage signal in accordance with the equation V _{i} =V_{H} -I_{i} R_{L} for i=1 to n where I_{i} =(V_{H} /R_{L}) (1-e^{-i}α) and V_{H} =V_{CC} -V_{BE} and V_{BE} is a base to emitter voltage drop of a transistor coupled to said second signal source; anda comparator providing a timing signal whenever said second voltage signal becomes greater than said first signal. 6. The source of claim 5, wherein said electrode is a control electrode and said electron flow path is formed between said control electrode and said second signal source, said transistor having a voltage drop V
_{BE} thereacross, said voltage source V_{CC} being coupled to one end of said electron flow path, and where in said resistance R_{L} is coupled between said control electrode and said voltage source, the other end of said flow path providing a second voltage signal to said control electrode in accordance with the equation V_{i} -V_{H} -I_{i} R_{L} for i=1 to n where I_{i} =(V_{H} /R_{L}) (1-e^{-i}α) and V_{H} =V_{CC} -V_{BE}.7. A source as set forth in claim 6, further including a current source disposed between said voltage source and said control electrode to provide a current I
_{B} =(V_{H} /R_{L})e^{-i}α between said voltage source and said control electrode and a current source between said control electrode and a source of reference voltage to provide a current I_{A} =V_{H} /R_{L}.8. A source as set forth in claim 5, further including means to vary the value of i.
9. A source as set forth in claim 8, wherein said means to vary the value of i is a decoder.
10. A source as set forth in claim 6, further including means to vary the value of i.
11. A source as set forth in claim 10, wherein said means to vary the value of i is a decoder.
12. A source as set forth in claim 7, further including means to vary the value of i.
13. A source as set forth in claim 12, wherein said means to vary the value of i is a decoder.
Description This invention relates to a system for providing indicia of linear or equally spaced time position variations, particularly for use in conjunction with write precompensation circuits to compensate for bit shift. There has been a problem in the prior art in obtaining timing signals having equal spacing therebetween in general and particularly in connection with write precompensation circuits. Write precompensation circuitry is provided to compensate for the bit shift caused by the intersymbol interference. In order to increase disk storage capacity, adjacent stored bits are placed very close together. The "1" bits are represented by alternating magnetic fluxes with the peak positions representing the data information. When two signals are superimposed upon each other, a composite of the two signals is obtained. This causes a shift of the peak position from the ideal. In the past, one way of compensating for this peak shift problem has been to write the data closer together than required by a certain amount at first so that the peak shift process would push the adjacent bits apart later and cause the final peaks to be in the idealized location. A discussion of this problem is set forth in Electronics, Apr. 21, 1982 at page 111. A prior art write compensation circuit is shown by the block diagram implementation in FIG. 1 which recognizes specific write data patterns and can add or subtract delays in the time position of write data bits to counteract the read back bit shift. In this prior art circuit, all of the circuitry including pads WCS and WO bar are on a single chip and capacitor C and resistance R are off chip. The magnitude of the time shift of the signal, which is at the output at the WO bar pad, is determined by the RC network composed of resistance R and capacitor C which are external to the chip in accordance with the equation:
TPC=WPαR(C+C where TPC is time position compensation, α is a constant that provides the best fit of measured results, C In the circuit of FIG. 1, a digital write data signal is provided by a digital write data circuit 2 and provides an output signal shown in FIG. 2 as WCS, this signal being applied to the positive input of a comparator 4. A digital to analog converter (DAC) 6 generates, for example, seven different DC levels or WP in the above equation, one at a time, at the negative input of the comparator 4 whose output is the WO bar output as shown in the timing diagram in FIG. 2. As can be seen in FIG. 2, the WO bar signal is high until the voltage level at the negative input of the comparator 4 provided by the DAC is the same as or higher than the voltage level from the circuit 2. The DAC 6 generates the seven different voltage levels at seven different time positions. Only the falling or trailing edges of signals at the WCS and WO bar pads are used for timing. As can be seen in FIG. 2, the WCS signal follows an exponential decay waveform, this occurring only when transistor Q In accordance with the present invention, the above described problem is resolved and there is provided a DAC which is capable of providing a nonlinear output to compensate for the nonlinearity in the output of the digital data write circuit 2. The voltage V
V where C As the output voltage of DAC 6 (V
V There is a one-to-one mapping between I At intersection points, V
V
or
t Equating consecutive time intervals, i.e., t
V The above TPC equation (1) is evaluated for one time interval to obtain the equation t
V Manipulation of the equations (2), (3) and (4) results in the equation for i=1 to 7 of:
I Therefore, the requirements on I
I FIG. 1 is a block diagram of a prior art write compensation circuit; FIG. 2 is a timing diagram showing the operation of the write precompensation circuit of FIG. 1; FIG. 3 is a timing diagram showing the intersections of the V FIG. 4 is a block diagram implementation of linear time variations based upon the equation I FIG. 5 is a circuit diagram showing the generation of the currents used in FIG. 6 in accordance with the present invention; and FIG. 6 is a circuit diagram of a DAC which can be used in accordance with the present invention. A block diagram implementation of linear time position variations based upon the equation I Referring now to FIG. 5, there is shown a circuit diagram of an exponential current generator in accordance with the present invention. This circuit includes two inputs, iI and I The equations describing the circuit of FIG. 5 are as follows:
(iI)R
I
I where V The above equations can be simplified into:
I Therefore, the output current is given by:
I Transistor N Referring now to FIG. 6, there is shown a schematic diagram of a circuit which provides the currents as set forth in FIG. 4 and which can be used as a DAC in accordance with the present invention. The exponential current generator described in conjunction with FIG. 5 is incorporated into the circuit of FIG. 6. Current iI is forced into resistance R
I This equation is different from equation (6) above by a "2" factor which is present to account for the addition of transistors Q A reference current I Transistor Q As discussed above, with current iI from transistor P
I
α=IR It is apparent that the current I Transistor N It is desirable that the coefficient α given by equation (9) be temperature invariant. As shown in FIG. 6, current I is set up as:
I=(V where V Though the invention has been described with respect to a specific preferred embodiment thereof, many variations and modifications will immediately become apparent to those skilled in the art. It is therefore the intention that the appended claims be interpreted as broadly as possible in view of the prior art to include all such variations and modification. Patent Citations
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