US 5491652 A Abstract A for Fast Fourier Transform (FFT) address generator utilizes a butterfly counter to count a butterfly count for each butterfly stage of FFT in numerical sequence; and a stage counter to count a stage count for the butterfly stage of FFT in bit-shifting manner. A data address logic is coupled to the butterfly counter and the stage counter to receive the butterfly count and the stage count, and to generate a data address according to a first regularized logic function. A twiddle factor address logic is coupled to the butterfly counter and the stage counter to receive the butterfly count and the stage count, and to generate a twiddle factor address according to a second regularized logic function.
Claims(6) 1. An address generator for a 2
^{m} -point FFT comprising:a butterfly counting mechanism for counting a butterfly count (B _{m-2} B_{m-3} . . . B_{0}) for each butterfly stage of FFT in numerical sequence;a stage counting mechanism for counting a stage count (R _{m-1} R_{m-2} . . . R_{0}) for the butterfly stage of FFT in bit-shifting manner;a data address logic mechanism, coupled to said butterfly counting mechanism and said stage counting mechanism, for receiving said butterfly count (B _{m-2} B_{m-3} . . . B_{0}) and said stage count (R_{m-1} R_{m-2} . . . R_{0}), and for generating a data address (A_{m-1} A_{m-2} . . . A_{0}) according to a first predetermined logic function: ##EQU4## wherein S is a select signal for the upper/lower data addresses in a butterfly of FFT; anda twiddle factor address logic mechanism, coupled to said butterfly counting mechanism and said stage counting mechanism for receiving said butterfly count (B _{m-2} B_{m-3} . . . B_{0}) and said stage count (R_{m-1} R_{m-2} . . . R_{0}), and for generating a twiddle factor address (C_{m-2} C_{m-3} . . . C_{0}) according to a second predetermined logic function:(C 2. The FFT address generator as claimed in claim 1, wherein said data address logic mechanism includes bit-reversing mechanism for reversing the bits of said stage count (R
_{m-1} R_{m-2} . . . R_{0}) before performing the data address generation logic according to said first predetermined logic function, in case of the decimation-in-frequency FFT; and wherein said twiddle factor address logic mechanism includes bit-reversing mechanism for reversing the bits of the butterfly count (B_{m-2} B_{m-3} . . . B_{0}) before performing the twiddle factor address generation logic function according to said second predetermined logic, in case of the DIF FFT.3. The FFT address generator as claimed in claim 2, further comprising a butterfly full logic mechanism, coupled to said butterfly counting mechanism, for receiving said butterfly count (B
_{m-2} B_{m-3} . . . B_{O}), and for generating a full signal to flag the last butterfly calculation in a certain butterfly stage of FFT.4. The FFT address generator as claimed in claim 3, further comprising a stage full logic mechanism, coupled to said stage counting mechanism, for receiving said stage count (R
_{m-1} R_{m-2} . . . R_{0}), and for generating a last signal to flag the last butterfly stage of FFT.5. The FFT address generator as claimed in claim 4, wherein said data address logic mechanism utilizes a pass-transistor array structure to implement said first predetermined logic function.
6. The FFT address generator as claimed in claim 4, wherein said twiddle factor address logic mechanism utilizes a pass-transistor array structure to implement said second predetermined logic function.
Description The present invention relates to an FFT (Fast Fourier Transform) address generator, and more particularly to an FFT address generator which has simpler structure and higher speed than conventional models. The FFT is probably one of the most important algorithms in digital signal processing (DSP) applications. There are two approaches for computing the transform: software implemented on a programmable DSP, and dedicated FFT processor development. Real-time DSP favors the use of the latter, which offers parallel processing capability. An FFT processor hardware system mainly consists of two parts: the butterfly processor for arithmetic operation, and an address generator for the generation of read/write addresses. The address generator provides addresses of the operation data as well as the so-called "twiddle factors" W To meet the requirements of different signal flow graphs and different point numbers, the logic design of an FFT address generator is complicated, and arithmetic-logic-unit-like structures are often used. Addresses are generated through the execution of instructions. The propagation delay time of conventional FFT address generators is relatively high. Through the study of FFT signal flow graphs, it has been found by the present inventors that in FFT calculation, the rules of binary address generation for the data and twiddle factors W In accordance with the present invention, an address generator for a 2 a butterfly counting mechanism for counting a butterfly count (B a stage counting mechanism for counting a stage count (R a data address logic mechanism, coupled to the butterfly counting mechanism and the stage counting mechanism, for receiving the butterfly count (B a twiddle factor address logic mechanism, coupled to the butterfly counting mechanism and the stage counting mechanism for receiving the butterfly count (B
(C According to one feature of the present invention, the data address logic mechanism includes a bit-reversing mechanism for reversing the bits of the stage count (R According to another feature of the present invention, the FFT address generator further comprises a butterfly full logic mechanism, coupled to the butterfly counting mechanism, for receiving the butterfly count (B According to further feature of the present invention, the data address logic mechanism utilizes a pass-transistor array structure to implement the first predetermined logic function. The twiddle factor address logic mechanism also utilizes a pass-transistor array structure to implement the second predetermined logic function. The present invention can be more fully understood by reference to the following description and accompanying drawings, which form an integral part of this application: FIG. 1 shows a well-known decimation-in-time type of signal flow graph for an 8-point radix-2 FFT processor; FIG. 2 shows a well-known decimation-in-frequency type of signal flow graph for an 8-point radix-2 FFT processor; FIG. 3 is a schematic block diagram of an FFT address generator according to one preferred embodiment of the present invention; FIG. 4 is a schematic electronic circuit diagram of a data address logic able to be used in the FFT address generator of FIG. 3; FIG. 5 is a schematic electronic circuit diagram of a twiddle factor address logic able to be used in the FFT address generator of FIG. 3. On the basis of FFT in-place calculation, the basic function of an FFT processor hardware system is the provision of two types of signal flow graphs of radix-2: decimation-in-time (DIT) and decimation-in-frequency (DIF). The DIT and DIF types of signal flow graphs have different structures and should be discussed separately. For radix-2 decimation, a 2 At first, the DIT-type signal flow graph for 8-point radix-2 FFT is considered, and then the general rules of address generation are concluded. The data addresses (α
TABLE 1______________________________________The data addresses (a In order to analyze the rule, the addresses are written in binary form. The X column in Table 1 lists the addresses of upper data in the butterfly while the X' column lists the addresses of lower data. The butterfly calculation is counted in each stage of decimation in numerical sequence as in the left column (b By observing and analyzing Table 1, it is found that there are regularities in the bits of data address (α The complex constant W
TABLE 2______________________________________The addresses (c For convenience of analysis, two auxiliary "zero" bits (00) are added to the end of the butterfly count value (b By studying the regularity of the W For each stage of decimation, the W From this regularity, the Boolean expression of the W
(c After the above-described regularities of the data and W The equation (1) is expanded as: ##EQU3## wherein S is a select signal for the upper/lower data addresses in a butterfly. The select signal S equals "0" for the address of the upper data in a butterfly, and equals "1" for the address of the lower data. The equation (2) is expanded as:
(C Through comparison of two types of signal flow graphs, it is found that DIF FFT can also utilize the above-described address generation logic of DIT FFT with a little modification. For a DIF FFT of 2 a. Reverse the bits of the stage count R[m-1:0] while the butterfly count B[m-2:0] remains unchanged, and using the same address generation logic, i.e. Eq. (3), the data address of DIF FFT can be attained simply. b. Reverse the bits of the butterfly count B[m-2:0] while the stage count R[m-1:0] remains unchanged, using the same address generation logic, i.e. Eq. (4), the constant W Following to the address generation logic described above, an address generator for an FFT processor is designed and shown in FIG. 3, according to one preferred embodiment of the present invention. The address generator for the FFT processor includes a butterfly counter 10, a stage counter 20, a first full logic or butterfly full logic 30, a second full logic or stage full logic 40, a data address logic 50, and a twiddle factor W The data address logic 50 is coupled to the butterfly counter 10 and the stage counter 20 to receive the butterfly count (B A reset signal RESET may be connected to the butterfly counter 10 and the stage counter 20 in order to reset the butterfly count (B In order to adapt both of the DIT and DIF FFT algorithms, the data address logic 50 may include a bit-reversing mechanism for reversing the bits of the stage count (R In terms of circuit design, for the logic mechanisms of the data and twiddle factor address generation, it is convenient to utilize a MOS (Metal-Oxide-Semiconductor) pass-transistor array. This structure is similar to the barrel shifter. After a study of the address generation logic of equations (1), (2), (3), and (4), it will be found that all logic functions are a summation of two-variable-multiplication items. In addition, all multiplication items include a logic variable R While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention need not be limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, the scope of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structures. Patent Citations
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