|Publication number||US5497458 A|
|Application number||US 08/087,583|
|Publication date||Mar 5, 1996|
|Filing date||Jul 6, 1993|
|Priority date||Jul 6, 1993|
|Publication number||08087583, 087583, US 5497458 A, US 5497458A, US-A-5497458, US5497458 A, US5497458A|
|Inventors||Richard Finch, Eric Schieve, Joseph Vivio|
|Original Assignee||Dell Usa, L.P.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (5), Referenced by (26), Classifications (5), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates to cache memory systems in computer systems, and more particularly to a cache testability circuit which disables writes to main memory to facilitate cache memory testing.
2. Description of the Related Art
Modern computer systems are required to manipulate and store increasingly larger amounts of code and data. One method that is commonly used to speed up memory accesses in computer systems is to utilize what is referred to as cache memory. A cache memory is a small amount of very fast, and expensive, zero wait state memory that is interposed between a device which regularly requests data and a storage device. For example, the most common type of cache memory is referred to as a microprocessor cache memory. The microprocessor cache memory is interposed between the microprocessor and main memory and stores frequently used code and data. When a microprocessor requests data and the data resides in the cache, then a cache hit occurs and the data is provided back to the microprocessor without requiring a main memory access. If the requested data does not reside in the cache, then a cache miss occurs, and the microprocessor then must retrieve the requested data from main memory.
Cache management is usually performed by a device referred to as a cache controller. The cache controller determines the organization of the cache memory as well as the write policy that is enforced. For example, a cache memory may be organized as either a direct mapped cache or a set associative cache. In order to more fully understand cache organization, it is helpful to conceptualize main memory as comprising a plurality of pages of memory of a certain size. A number of the upper address bits comprising a memory address can individually access each of these conceptual pages, while the remaining or lower address bits comprise an offset within a respective page.
In a direct mapped cache, the cache memory is organized as a single conceptual page of memory, and there is a single unique location in the cache memory where a piece of data may reside. This unique location is determined by the offset or lower address bits of the address of the respective data. Therefore, the lower address bits or offset determine where a piece of data will be stored in the cache memory. The upper address bits, referred to as the tag, are stored in a separate block of memory referred to as the tag memory or tag RAMs. Each location in the cache memory includes a corresponding tag location which stores the upper address bits of the address corresponding to the data stored in the respective cache memory location. When a memory access occurs, the cache controller performs a tag compare cycle to compare the tag location corresponding to the respective offset where the data might be stored with the upper address bits of the requested address. If the contents of the tag location equal the upper address bits of the memory access, then a cache hit occurs.
In a set associative cache design, the cache memory is organized into multiple banks or ways of cache memory wherein each bank of memory corresponds to a conceptual page in main memory. Thus, in a four-way set associative cache, a piece of data having an address can be stored in either of four places in the cache memory. As with a direct mapped cache, where the data is stored in a respective bank of memory depends on the offset or lower address bits of the address corresponding to the data, and the upper address bits or tag are stored in a corresponding tag location.
The write policies enforced by a cache controller are generally referred to as either write-through or write-back. In a write-through cache, on a write hit the data is updated in both the cache memory and in main memory simultaneously. In a write-back cache, the updated data is only written back to main memory when the need arises, such as when another device requests this data from main memory.
As with main memory, the cache memory must generally be tested during power-up of the computer system to ensure that the memory is operating properly. Prior to testing a cache memory, it is first necessary to determine the size of the cache memory. Cache sizing is necessary because subsequently employed cache memory testing routines are typically required to fill the entire cache memory space with data patterns and then perform accesses to this stored data. One problem with sizing and testing a cache memory is that it is difficult to determine whether the processor is accessing data that resides in the cache memory or actually accessing data in main memory. This problem arises because a quickly responding read from main memory sometimes appears to the processor as if it were a cache memory read.
Prior art methods for discerning differences between a cache memory access and a main memory access have used timing methods. Generally, a cache memory access is much faster than a main memory access, and thus a cache memory access can be distinguished from a main memory access based on response time. However, timing methods generally cannot be used in embedded diagnostic routines because there are a multitude of different processor speeds that can be used in the system. Floppy disk based diagnostics routines can be utilized which use software timing loops based on the processor speed in the respective system being tested. However, this requires a number of different floppy disks for computers having different processor speeds. In addition, loading a floppy disk to perform diagnostics at every power-up is very inconvenient for the user. A diagnostic routine may also rely upon hardware based system timers. However, hardware based timers introduce hardware dependencies into the diagnostic testing and thus may need to be modified in subsequent computer systems. Therefore, a method and apparatus is required which provides the ability to size and test cache memory systems independent of the particular hardware configuration in which the cache memory is embedded.
Another method that has been used to distinguish between cache memory and main memory accesses in order to perform robust cache memory sizing and testing is to create a cacheable address space which is either not readable or not writable or both. If the cacheable address space is not writable, then on write hits to the cache memory the data will only be stored in the cache memory. Thus, a pattern of data written to addresses which are cached will result in storage of the respective data in the cache memory, and this data will not be stored in the non-writable main memory. This creates a disparity between the data stored in the cache memory and the data stored in main memory. Thus, on subsequent reads of these addresses, the return data will provide a ready indication of whether a cache hit or cache miss occurred. Similarly, if the main memory is not readable, read cycles issued by the processor can only be serviced by the cache memory. This also provides a ready indication between cache hits and cache misses.
One method that has been used to obtain either non-readable or non-writable cacheable address space is to load data and tag addresses into the cache memory and tag RAMs, respectively, and then disable the main memory. Main memory that has been disabled or is otherwise invalid is both non-readable and non-writable and thus serves the desired purpose. Therefore, a memory space that is cacheable but yet has no actual valid main memory for data storage enables a simple and ready method for distinguishing between a cache memory access and a main memory access.
Another prior art method that has been used to provide a cacheable space with no actual main memory is to designate logical address space cacheable that does not have any corresponding physical memory. Thus, on subsequent memory accesses, cache hits will result in data being provided from the cache memory, whereas on cache misses no actual physical memory is present for the logical address generated. This also provides a ready method for distinguishing between cache hits and cache misses during memory sizing and testing.
In each of the above methods where main memory has been either disabled or is not present, the memory controller will designate addresses corresponding to this memory space as non-cacheable. Therefore, one requirement of the above methods is that the cache controller must have the ability to respond to cache hits regardless of the cacheability indicated by the memory controller. However, new chip sets such as the Intel 82424TX cache and DRAM controller (CDC) include a combined cache controller and DRAM or memory controller which does not allow the cache controller to respond to cache hits where the corresponding memory address space has been rendered non-cacheable. Thus, simply disabling or invalidating the main memory after the cache has been loaded does not allow cache memory testing because the memory controller will not allow cache hits to occur if the requested address corresponds to memory that has been disabled or is otherwise non-cacheable. In addition, creating a cacheable logical address space that does not have corresponding physical memory is not possible since the memory controller will maintain this address space non-cacheable due to physical memory not being present. Therefore, a method and apparatus is desired which allows the testing of cache memory in systems having integrated cache and memory controllers which do not allow cache hits to non-cacheable memory locations.
Another method to achieve either non-readable or non-writable cacheable address space is to use cacheable Read Only Memory (ROM). Since cacheable ROM is by definition read only, a diagnostic program can distinguish between cache misses and cache hits by simply writing a data pattern to the respective addresses and then reading this data back. One problem with this method is that in many systems a cacheable read only memory is a feature not provided by the memory controller in the respective computer system.
The present invention comprises a DRAM disable circuit which provides a generic means for testing cache memory systems. The disable circuit comprises a buffer which receives a write signal from the memory controller and provides this signal to main memory. During cache memory diagnostics this buffer is disabled, preventing writes to main memory. This disables writes to main memory in a manner external to the memory controller and thus allows tags to be loaded from a cacheable space in main memory. The memory controller believes main memory is valid and thus maintains the address space cacheable. However, since writes to main memory are disabled, cache testing can be performed whereby read misses, cycles to main memory, can be distinguished from read hits. This enables the testing of cache memory systems in computer systems using integrated cache and memory controllers which prevent read hits to memory addresses whose cacheability has been disabled. This also provides a testability function that is hardware independent and thus can be used regardless of the configuration or processor used in the computer system.
A better understanding of the present invention can be obtained when the following detailed description of the preferred embodiment is considered in conjunction with the following drawings, in which:
FIG. 1 is a computer system according to one embodiment of the invention;
FIG. 2 illustrates the DRAM disable circuit according to one embodiment of the invention; and
FIG. 3 illustrates a method for performing cache testability diagnostics utilizing the circuit in FIG. 2.
Referring now to FIG. 1, a computer system incorporating the present invention is shown. The elements of a computer system not necessary to understand the operation of the present invention have been omitted for simplicity. The computer system includes a central processing unit or CPU 122 which is coupled to a memory or host bus 124. The CPU 122 includes a cache memory 132 coupled between the CPU 122 and the host bus 124. The CPU 122 may also include a separate internal cache memory (not shown). The host bus 124 includes address, data, and control portions. Main memory 126 comprised of dynamic random access memory (DRAM) is coupled to the host bus 124.
A combined cache and DRAM controller (CDC) 130 which integrates both cache controller and memory controller logic is coupled to the CPU 122, the cache memory 132, main memory or DRAM 126 and the host bus 124. In the preferred embodiment, the CDC 130 is the 82424TX produced by Intel. The CDC 130 preferably does not allow cache hits to tag addresses that are not cacheable or whose cacheability has been disabled. A DRAM write disable circuit 136 according to the present invention is coupled between the CDC 130 and main memory 126. As discussed below, the DRAM write disable circuit 136 disables write operations to main memory 126 during cache memory diagnostics to create a cacheable address space corresponding to non-writable physical memory. This allows cache hits to be distinguished from cache misses during diagnostics and thus enables cache memory sizing and testing.
The host bus 124 is coupled to an expansion or input/output (I/O) bus 140 by means of a bus controller 142. The expansion bus 140 includes slots for various other devices, including video 144, a floppy drive 146 and hard drive 148. The expansion bus 140 is also connected to a third peripheral bus referred to as the X bus 160 through a buffer 162. Coupled to the X bus 160 are read only memory (ROM) and an I/O diagnostic port 214. The ROM 164 is preferably designated as non-cacheable by the CDC 130. The I/O diagnostic port 214 acts as a signal source in the preferred embodiment of the invention and is used during cache memory diagnostics as follows. During diagnostics at power-up, the CPU 122 writes a bit to the diagnostics port 214, which asserts a signal referred to as CACHE-- TEST to the DRAM write disable circuit 136. The CACHE-- TEST signal directs the DRAM write disable circuit 136 to disable writes to the main memory 126, as discussed below.
As discussed in the background portion, it is important that both main memory 126 and the cache memory 132 be tested during Power On Self Test (POST) to ensure that all memory components are working properly. When testing a cache memory system 132, it is first necessary to determine the size of the cache memory 132 prior to testing. Sizing the cache memory 132 is necessary prior to testing because cache memory testing routines typically operate by filling the entire cache memory space with data patterns and then performing read accesses to test the results. Both cache memory sizing and testing require a determination as to whether the processor is accessing data in the cache memory 132 or actually accessing main memory 126. This determination is many times difficult because a quickly responding read from main memory 126 may appear to the CPU 122 as a cache memory read.
Methods that have been used to distinguish between cache memory reads and main memory reads involve creating a cacheable memory address space wherein the physical main memory is invalid or has been disabled. However, the cache and memory controller logic used in the preferred embodiment of the invention, the Intel 82424TX CDC, operate such that the memory controller prevents cache read hits to tag addresses whose cacheability has been disabled. Therefore, it is no longer possible to simply disable the main memory or DRAM after loading the cache memory 132 because subsequent cache reads will be designated non-cacheable by the memory controller in the CDC 130.
Another method that has been used is to create a cacheable memory address space wherein the corresponding physical memory is not present. However, the CDC 130 of the preferred embodiment does not allow a cacheable address space corresponding to physical memory that is not present. Another method has been to use cacheable ROM. However, the CDC 130 does not allow cacheable ROM.
Therefore, the present invention operates by disabling write operations to main memory 126. The memory or DRAM controller 210 (FIG. 2) in the CDC 130 still believes that main memory 126 is both readable and writable and thus maintains the address space cacheable. In this manner, cache memory testing can be performed whereby read misses (cycles to DRAM) can be easily distinguished from read hits.
Referring now to FIG. 2, the DRAM disable circuit according to the preferred embodiment of the invention is shown. In the description that follows, a "#" sign following a signal indicates that the signal is asserted when it has a logic low value. As shown, DRAM controller 210 comprised in the CDC 130 generates a write signal referred to as WRITE# to the input of a write buffer 212 comprised in the DRAM write disable circuit 136. The diagnostic port 214 provides the CACHE-- TEST signal to the output enable (oe) input of the buffer 212. The buffer 212 provides an output signal referred to as DRAM-- WRITE# to the main memory or DRAM 126. When the CACHE-- TEST signal is asserted, the output of the buffer 212 is disabled. The DRAM-- WRITE# signal is also connected through a pull-up resistor 216 to a positive voltage supply +VCC. The pull-up resistor 216 maintains the DRAM-- WRITE# signal at a logic high value (+VCC) when the CACHE-- TEST signal is asserted and the output of the buffer 212 is floated.
When cache memory diagnostics are being performed, the CPU 122 writes a bit to the diagnostic port 214 which causes the port to assert the CACHE-- TEST signal to the output enable pin of the output buffer 212. This disables assertion of the DRAM-- WRITE# signal to the main memory 126 and thus prevents writes from occurring to main memory 126.
Referring now to FIG. 3, a flowchart diagram illustrating operation of the cache memory testing method of the present invention is shown. In step 302 the CPU 122 reads data from the main memory or DRAM 126 to load tags into the cache memory 132. In this step, the CPU 122 is reading dummy data from the DRAM 126. This dummy data is stored in the cache memory 132, and the upper address bits comprising the tag are stored in the tag RAMs comprised within the CDC 130. This read is done solely to load tags into the tag RAMs in the CDC 130. In the cache system of the preferred embodiment, write misses do not generate cache allocations and thus do not load tag addresses into the tag RAMs. Therefore a read to load the tag RAMs is necessary. However, it is noted that if the cache system performs cache allocations on write misses, then CPU write operations can be used to load the tag RAMs as desired.
In step 304 the CPU 122 writes a bit to the diagnostic port 214, and the port asserts the CACHE-- TEST signal to the output enable pin of the DRAM write buffer 212. As discussed above, this serves to disable assertion of the DRAM-- WRITE# signal and thus disables all writes to main memory 126. It is noted that step 304 can precede step 302, and writes to the DRAM 126 can be disabled prior to reading data from the DRAM 126 to load the tag RAMs. Disabling writes to the DRAM 126 prior to the read in step 302 serves to lock the current data into the DRAM 126 prior to reading dummy data into the cache memory 132.
In step 306 the CPU 122 performs a cache sizing algorithm to determine the size of the cache memory 132. This cache sizing algorithm can be any of several types that are used, as is well known in the art. For more information on specific cache memory sizing algorithms, please see related co-pending application Ser. No. 08/043,508 titled "Cache Memory Sizing Procedure" whose inventor is Eric William Schieve, and which is assigned to the same assignee as the present application, which is hereby incorporated by reference.
In step 308 the CPU 122 performs the desired cache memory testing algorithm. The cache memory testing algorithm may include writing patterns to the cache memory 132 and then subsequently reading these patterns back to test for memory integrity. It is noted that any of various types of cache memory testing algorithms can be performed, as is well known in the art.
Therefore, a method and apparatus for performing cache memory sizing and testing is shown. The computer system includes a circuit which disables write operations to the DRAM 126 to enable the CPU 122 to distinguish between cache read hits and cache read misses. By disabling writes to main memory 126 in this manner, the memory controller 210 in the CDC 130 still believes that main memory 126 is valid and thus maintains the address space cacheable. This enables cache memory sizing and testing in computer systems which do not allow cache read hits to occur to non-cacheable and/or invalid memory locations. This also provides a testability function that is hardware independent and thus can be used regardless of the configuration or processor used in the computer system.
Although the method and apparatus of the present invention has been described in connection with the preferred embodiment, it is not intended to be limited to the specific form set forth herein, but on the contrary, it is intended to cover such alternatives, modifications, and equivalents, as can be reasonably included within the spirit and scope of the invention as defined by the appended claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4575792 *||Mar 31, 1982||Mar 11, 1986||Honeywell Information Systems Inc.||Shared interface apparatus for testing the memory sections of a cache unit|
|US5195096 *||Mar 9, 1992||Mar 16, 1993||John Fluke Mfg. Co., Inc.||Method of functionally testing cache tag RAMs in limited-access processor systems|
|US5276833 *||Jul 2, 1990||Jan 4, 1994||Chips And Technologies, Inc.||Data cache management system with test mode using index registers and CAS disable and posted write disable|
|US5287481 *||May 4, 1992||Feb 15, 1994||Opti, Inc.||Automatic cache flush with readable and writable cache tag memory|
|US5341494 *||Dec 10, 1993||Aug 23, 1994||Compaq Computer Corporation||Memory accessing system with an interface and memory selection unit utilizing write protect and strobe signals|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US5610867 *||Sep 28, 1995||Mar 11, 1997||International Business Machines Corporation||DRAM signal margin test method|
|US5740353 *||Dec 14, 1995||Apr 14, 1998||International Business Machines Corporation||Method and apparatus for creating a multiprocessor verification environment|
|US5831987 *||Jun 17, 1996||Nov 3, 1998||Network Associates, Inc.||Method for testing cache memory systems|
|US5848275 *||Jul 29, 1996||Dec 8, 1998||Silicon Graphics, Inc.||Compiler having automatic common blocks of memory splitting|
|US5903915 *||Mar 16, 1995||May 11, 1999||Intel Corporation||Cache detection using timing differences|
|US5928334 *||Mar 28, 1997||Jul 27, 1999||International Business Machines Corporation||Hardware verification tool for multiprocessors|
|US6032230 *||Dec 28, 1998||Feb 29, 2000||Sun Microsystems, Inc.||Method and apparatus that detects and tolerates inconsistencies between the cache and main memory, and the translation lookaside buffer and the virtual memory page table in main memory|
|US6240532 *||Apr 6, 1998||May 29, 2001||Rise Technology Company||Programmable hit and write policy for cache memory test|
|US6285974||May 4, 1999||Sep 4, 2001||International Business Machines Corporation||Hardware verification tool for multiprocessors|
|US6425056 *||Oct 26, 1998||Jul 23, 2002||Micron Technology, Inc.||Method for controlling a direct mapped or two way set associative cache memory in a computer system|
|US6892173 *||Mar 30, 1998||May 10, 2005||Hewlett-Packard Development Company, L.P.||Analyzing effectiveness of a computer cache by estimating a hit rate based on applying a subset of real-time addresses to a model of the cache|
|US6910107 *||Aug 23, 2000||Jun 21, 2005||Sun Microsystems, Inc.||Method and apparatus for invalidation of data in computer systems|
|US6957208||Oct 31, 2000||Oct 18, 2005||Sun Microsystems, Inc.||Method, apparatus, and article of manufacture for performance analysis using semantic knowledge|
|US6986130||Jul 28, 2000||Jan 10, 2006||Sun Microsystems, Inc.||Methods and apparatus for compiling computer programs using partial function inlining|
|US7035989||Feb 16, 2000||Apr 25, 2006||Sun Microsystems, Inc.||Adaptive memory allocation|
|US7240169||Jan 18, 2002||Jul 3, 2007||Sun Microsystems, Inc.||Protocol for coordinating the distribution of shared memory|
|US7406681||Oct 12, 2000||Jul 29, 2008||Sun Microsystems, Inc.||Automatic conversion of source code from 32-bit to 64-bit|
|US8190513||May 29, 2012||Fraud Control Systems.Com Corporation||Method of billing a purchase made over a computer network|
|US8229844||Jul 24, 2012||Fraud Control Systems.Com Corporation||Method of billing a purchase made over a computer network|
|US8560907 *||Aug 12, 2008||Oct 15, 2013||Altera Corporation||Debugging external interface|
|US8630942||Oct 22, 2008||Jan 14, 2014||Fraud Control Systems.Com Corporation||Method of billing a purchase made over a computer network|
|US9030860 *||May 15, 2013||May 12, 2015||Sidense Corp.||Power up detection system for a memory device|
|US20020059503 *||Jan 18, 2002||May 16, 2002||Sun Microsystems, Inc.||Protocol for coordinating the distribution of shared memory|
|US20130308364 *||May 15, 2013||Nov 21, 2013||Sidense Corp.||Power up detection system for a memory device|
|CN104303235A *||May 15, 2013||Jan 21, 2015||赛登斯公司||A power up detection system for a memory device|
|CN104303235B *||May 15, 2013||Apr 6, 2016||赛登斯公司||用于存储器设备的上电检测系统|
|U.S. Classification||714/30, 365/201|
|Jul 6, 1993||AS||Assignment|
Owner name: DELL U.S.A., L.P., TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FINCH, RICHARD;SCHIEVE, ERIC;VIVIO, JOSEPH;REEL/FRAME:006619/0581;SIGNING DATES FROM 19930702 TO 19930706
|Jun 21, 1999||FPAY||Fee payment|
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|Sep 5, 2003||FPAY||Fee payment|
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|Sep 5, 2007||FPAY||Fee payment|
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|Sep 10, 2007||REMI||Maintenance fee reminder mailed|