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Publication numberUS5498992 A
Publication typeGrant
Application numberUS 08/358,031
Publication dateMar 12, 1996
Filing dateDec 14, 1994
Priority dateApr 30, 1992
Fee statusLapsed
Publication number08358031, 358031, US 5498992 A, US 5498992A, US-A-5498992, US5498992 A, US5498992A
InventorsBenny W. H. Lai, Richard C. Walker
Original AssigneeHewlett-Packard Company
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Unity gain positive feedback integrator with programmable charging currents and polarities
US 5498992 A
Abstract
An integrator includes a capacitor and a bootstrap circuit for detecting any leaking charge from the capacitor and replacing it. The integrator also includes a charge injection circuit for adjusting the charge applied to the capacitor in response to a digital control input to the charge injection circuit. The bootstrap circuit has two transistors to sense leaking charge, and two further transistors forming a differential pair. The bootstrap circuit uses positive feedback and unity gain to replenish the lost charge.
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Claims(3)
What is claimed is:
1. An integrator circuit comprising:
a storage capacitor coupled to an input and output for storing charge, the charge on the capacitor representing the time integral of the current flowing from the input through the capacitor to the output; and
circuit means connected to the capacitor for detecting leaking charge from the capacitor, thereby maintaining the charge stored in the capacitor, wherein the circuit means comprises means for providing positive feedback in response to the leaking charge,
the circuit means further comprising first and second transistors for sensing the leakage charge and having first and second bases, respectively, the first and second bases being connected to opposite sides of the capacitor,
the means for providing positive feedback comprising third and fourth transistors having third and fourth bases, respectively, the first and second transistors having first and second emitters and first and second collectors, respectively, and the third and fourth transistors having third and fourth collectors, respectively, the first and second emitters being connected to the third and fourth bases, respectively, the first and second collectors being connected to the first and second bases, respectively, and the third and fourth collectors being cross-connected to the second and first bases, respectively,
the circuit means further comprising a first load resistor and a first diode connected between the first collector and base of the first transistor, and a second load resistor and a second diode connected between the second collector and base of the second transistor.
2. An integrator circuit comprising:
a storage capacitor coupled to an input and output for storing charge, the charge on the capacitor representing the time integral of the current flowing from the input through the capacitor to the output; and
circuit means connected to the capacitor for detecting leaking charge from the capacitor, thereby maintaining the charge stored in the capacitor, wherein the circuit means comprises means for providing positive feedback in response to the leaking charge,
the circuit means further comprising first and second transistors for sensing the leakage charge and having first and second bases, respectively, the first and second bases being connected to opposite sides of the capacitor,
the means for providing positive feedback comprising third and fourth transistors having third and fourth bases, respectively, the first and second transistors having first and second emitters and first and second collectors, respectively, and the third and fourth transistors having third and fourth collectors, respectively, the first and second emitters being connected to the third and fourth bases, respectively, the first and second collectors being connected to the first and second bases, respectively, and the third and fourth collectors being cross-connected to the second and first bases, respectively,
the circuit means further comprising a first load resistor and a fifth transistor connected between the first collector and base of the first transistor, the fifth transistor having a first emitter connected to the first base of the first transistor, and a fifth base and collector connected together, and a second load resistor and a sixth transistor connected between the second collector and base of the second transistor, the sixth transistor having a sixth emitter connected to the second base of the second transistor, and a sixth base and collector connected together.
3. The integrator circuit of claim 2, wherein the circuit means further comprises a pair of diodes, the diodes each having a cathode and an anode, the cathode of the first diode and the anode of the second diode being coupled to the base of the first transistor and the anode of the first diode and the cathode of the second diode being coupled to the base of the second transistor.
Description
CROSS REFERENCE TO RELATED APPLICATIONS

This is a continuation of application Ser. No. 07/877,449 filed on Apr. 30, 1992, now abandoned.

FIELD OF THE INVENTION

The invention relates to integrators and, more particularly, to low-noise capacitive integrators using unity gain positive feedback with programmable integrating rates.

BACKGROUND OF THE INVENTION

Integrators are electronic devices that produce an output signal equal to the time integral of the input signal. These integrators are characterized by the integration rate, and their ability to remember the signal over time. For capacitive integrators, the charging current and the value of the capacitor determine the integration rate, and the leakage current from the capacitor determines the effectiveness of the integrator's memory.

A capacitive integrator utilizes a storage capacitor to store and maintain charge within the integrator circuit. Traditionally, these capacitive integrators are implemented with capacitive negative feedback using an operational amplifier (op-amp) having a gain approaching infinity. However, due to this requirement of high open-loop gain, the op-amp must be carefully compensated to maintain stability. Such compensation is very difficult, especially for applications requiring high-speed processing. In addition, because of the high gain, the op-amp is more susceptible to picking up unwanted noise.

When a capacitive integrator is used in a phase-lock loop circuit, the capacitor is chosen such that the loop is stable over an operating frequency range. If this range is scaled, then the integrating rate of the integrator must be scaled accordingly. Typical integrators with a constant charging current require the value of the capacitor to be scaled inversely by the same factor to achieve the required charging rate. For a fixed-valued capacitor, it must be physically replaced by substitution. This process is inconvenient, expensive, and time-consuming.

It is desirable, therefore, to provide an inexpensive, relatively simple capacitive integrator which does not require an operational amplifier.

It is also desirable to produce a capacitive integrator which can adjust the charging rate without changing the value of the capacitor.

SUMMARY OF THE INVENTION

The present invention provides a unity gain, positive feedback integrator with programmable charging currents and polarities which provides all or some of the desirable characteristics of an ideal capacitive integrator. To this end, the present invention provides a bootstrap circuit using positive feedback to store and maintain the charge of a storage capacitor of the integrator and provides a programmable charging current circuit coupled to the bootstrap circuit for allowing the charging rate of the capacitor to be variable.

By using positive feedback and unity gain, this invention does not require frequency compensation to maintain stability as do the negative feedback op-amps commonly used. Moreover, due to the programmable charging current circuit, the invention allows the charging current into the storage capacitor to be adjustable. This feature allows the designs of phase-lock loops to operate over a wide frequency range with one storage capacitor.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be better understood, and its advantages will become apparent, by reference to the following detailed description in conjunction with the accompanying drawings in which:

FIG. 1 is a block diagram of the bootstrap circuit and programmable charge injection circuit included within the integrator according to the present invention;

FIG. 2 is a schematic diagram of a preferred embodiment of the bootstrap circuit used in the integrator of FIG. 1;

FIG. 3 is a preferred embodiment of the charge injection circuit of FIG. 1; and

FIG. 4 is an alternative embodiment of the bootstrap circuit of FIG. 2.

DETAILED DESCRIPTION OF THE INVENTION

Referring to FIG. 1, an integrator circuit is formed by a charge injection circuit 4, and a bootstrap circuit 8, which includes storage capacitor 10. The input charges to the integrator according to the present invention are first applied at inputs 2a, 2b of charge injection circuit 4. These input charges are processed by circuit 4 and transferred to circuit 8 at conductors 6a, 6b. The charges are then stored at capacitor 10.

The charge injection circuit is preferably programmable by applying further inputs at adjust control inputs 5, 7. The output of the charge injection circuit is applied across conductors 6a, 6b to the bootstrap circuit 8. The output of the integrator occurs at output nodes 12a, 12b in the form of a voltage signal.

In operation, the programmable charge injection circuit 4 controls the charging rate of the capacitor 10. The bootstrap circuit 8 maintains the charge stored in the capacitor by replacing any charge lost when current leaks from the capacitor. By maintaining charge, the outputs 12a, 12b will truly represent an integral of the input voltages applied at input 2a, 2b.

Referring to FIG. 2, the preferred embodiment of bootstrap circuit 8 according to the present invention includes a capacitor 10 having a first plate 14 and a second plate 20. The first plate 14 connects to node A at the base 18 of a first sensing transistor Qsn0. The second plate 20 of the capacitor 10 connects to node B at the base 24 of a second sensing transistor Qsn1. Transistor Qsn1 is preferably identical to transistor Qsn0. The emitter 26 of transistor Qsn0 is connected to node C. Node C is connected to the base 28 of a transistor Qun0. Similarly, the emitter 30 of transistor Qsn1 is connected to node D. Node D is connected to the base 32 of transistor Qun1. Transistor Qun1 is preferably identical to transistor Qun0. The respective emitters 34, 36 of transistors Qun0 and Qun1 are connected by emitter resistor 37 (RE). This provides a differential pair of transistors.

The emitters of transistors Qun0 and Qun1 are each coupled to current source I1 which biases the pair of transistors to their operating ranges. Similarly, the emitters of transistors Qsn0 and Qsn1 are connected to current sources I2. Collector 38 of transistor Qun0 is coupled to node B. The collector 40 of transistor Qun1 is cross-coupled to node A. A first diode 42 is connected between node A and node E. A second diode 44 is connected between node B and node F. A load resistor 46 is connected to node E. Similarly, a load resistor 48 is connected to node F. The collector 50 of transistor Qsn0, the collector 52 of transistor Qsn1, and load resistors 46 and 48 are connected to ground. All transistors are preferably NPN-type, but can also be other suitable types, such as PNP.

The operation of the bootstrap circuit of FIG. 2 will now be described. To maintain the charge stored in capacitor 10, the bootstrap circuit 8 detects the leakage current which flows from the capacitor and replaces the amount of charge lost due to this leakage current. For example, assume a charge is put into the capacitor 10 which results in +ΔQ at plate 14 and -ΔQ at plate 20. This will result in a voltage represented by +ΔV at node A and -ΔV at node B. The +ΔV voltage at node A will result in a current Δia (equal to ΔV/RL) through diode 42, as shown. Similarly, for node B, current Δia will appear going down through diode 44. These currents are leakage currents, and the charge lost from the capacitor due to these currents must be replaced to maintain the initial charge stored ΔQ in the capacitor.

To do this, the voltage +ΔV is sensed by transistor Qsn0. This voltage also appears at the base of transistor Qun0 at node C. Likewise, -ΔV is sensed by transistor Qsn1 at node B. This negative voltage also appears at the base of transistor Qun1 at node D. The +ΔV voltage at node C results in a current Δib away from node B, and the -ΔV voltage at node D results in a Δib current into node A. If the values of the circuit components are properly set, Δib can be made equal to Δia, thereby eliminating the net leakage current Δic. In other words, the net leakage current Δic would normally equal Δia without using the bootstrap circuit. However, the bootstrap circuit senses Δia and produces Δib, such that Δic =Δia -Δib, and the circuit elements are selected such that Δia minus Δib equals zero. Therefore, the leakage current is returned to the capacitor, in effect, so the charge in the capacitor is maintained.

To achieve this cancellation, the voltage gain (Av), from the difference of the voltages at node C and node D to the difference of the voltages at node A and node B, equals 1. In this case, it will be appreciated that the leakage currents will cancel. To ensure this result, the resistance of emitter resistor 37 (RE) is preferably set equal to one-half of the resistance of load resistors RL, thus RL =RE /2. Note that the bias currents through Qun0 and diode 44 are equal, so their transconductances are equal. Likewise, the transconductances of transistor Qun1 and diode 42 are also equal. Well known small circuit analysis thus shows that Δia =Δib, and thus Δic =ia -Δib =0.

The bias current I1 sets the operating point of the differential pair Qun0 and Qun1. The dynamic range of unity gain, that is, the maximum voltage difference between nodes C and D for the gain to be unity, is determined by I1 and RE. I2 is simply used to bias the sensing transistors Qsn0 and Qsn1 into their operating ranges.

If the gain is slightly below 1, then there will be slight leakage current from the capacitor. If the gain is slightly above 1, the capacitor voltage will slowly tend toward its maximum storage value. In either case, however, the circuit will not oscillate. In effect, the closer to unity, the longer the charge will remain because the RC time constant will be greater. This is not a concern for most phase-lock loop applications in which the charge to the capacitor is continually updated.

The charge injection to the bootstrap circuit for charging the capacitor is applied at nodes E and F, which are coupled to conductors 6a and 6b, as shown in FIG. 2. The charging current is preferably applied to nodes E and F as shown, although it could be applied directly to the capacitor at nodes A and B.

Referring to FIG. 3, the programmable charge injection circuit according to the present invention allows the integrator circuit to control the integration rate without having to replace the capacitor 10 of the bootstrap circuit shown in FIG. 2. Instead, the charge injection circuit allows scaling of the charging current that is sent to the capacitor. The input to the integrator is applied to differential voltage inputs 2a, 2b, which are coupled to the bases 70, 72 of transistors 66, 68. The emitters 74, 76 of transistors 66, 68 are coupled at node 78 to form a differential pair. The collectors 80, 82 of the transistors provide the charging current at nodes 6a and 6b of FIG. 2 to capacitor 10.

To control the amount of charge that is stored in the capacitor, the gain of the differential pair is altered by varying the bias current applied to node 78 of the differential pair. This bias current is altered by a 2-bit digital adjustment circuit 90 which includes adjustment control inputs 5a, 5b for a first bit of the digital input and adjustable current inputs 7a and 7b for a second bit of the digital input. The digital input at input nodes 5a, 5b is applied to bases 93, 95 of transistors 92 and 94. Collector 96 of transistor 92 provides one component of the biasing current to the differential pair 66, 68. The collector 98 of transistor 94 is coupled to ground. The emitters 97, 99 of transistors 92, 94 are connected together at node 100.

Similarly, inputs 7a, 7b are connected to transistors 102 and 104 at their bases 103, 105. Collector 106 of transistor 102 provides the second component of biasing current to the differential pair 66, 68. Collector 108 of transistor 104 is coupled to ground. Emitters 110 and 112 of the transistors 102 and 104 are coupled together at node 114. Node 100 is biased with a current source Ib. Node 114 is biased by a current source Ic. The current sources Ib and Ic are both coupled to a third current source Ia, which is connected to node 116. The transistors are all preferably NPN.

It will be appreciated that as the digital inputs at digital input adjustments 5 and 7 are changed, a variable amount of biasing current will be applied to the differential pair 66, 68. Thus, by effecting the digital inputs to the digital adjustment circuit 90, the charging current sent to capacitor 10 can be altered.

A variation of the bootstrap circuit is shown in FIG. 4. This variation is referred to as an enhanced bootstrap circuit 108. In FIG. 4, like reference numbers represent like elements as those in FIG. 2.

The enhancements in FIG. 4 include the substitution of resistors 200, 205 and transistors 201, 206 for diodes 42, 44, respectively. Collectors 203, 208 of transistors 201, 206 are connected to nodes E, F, respectively, and bases 202, 207 are connected through resistors 200, 205 to nodes E, F, respectively. Emitters 204, 209 are connected to nodes A, B, respectively. In addition, a pair of diodes 301, 302 are connected the anode of diode 301 and the cathode of diode 302 coupled to node B and the cathode of diode 301 and the anode of diode 302 coupled to node A, to clamp nodes A, B to a specified voltage level, e.g., 0.8 volts. This helps ensure that differential pair 28, 32 and the circuit always operate at unity gain, provided that I1 is set so that its dynamic range of unity gain is beyond 1.0 volt in this case.

The bootstrap integrator preferably operates where it can maintain unity gain. An analysis of the preferred voltage range is thus provided as follows:

As input voltage to the differential pair increases from 0, the current through resistor 37 increases from I1 to 2I1, because the current through Qun1 decreases. Since the base-emitter voltages of Qun0 and Qun1 are almost the same, while both devices are still on, the input voltage difference is absorbed by resistor 37 (RE). As this voltage approaches RE times I1, the current to Qun1 is passed sufficiently through resistor 37 such that Qun1 begins to turn off. Beyond this, the linear relationship of the gain disappears. By symmetry, the full range is 2(RE)I. For practical purposes, one should preferably stay within 90% of this range.

It should be noted that transistors 201, 206, 28, and 32 are preferably identical for optimal matching. Resistors 200, 205 are preferably provided, as these resistors allow even better matching of impedance at the base-emitter junctions of transistors 201, 206. Resistors 46, 48, 37, 200, and 205 are preferably built with identical materials and geometries for optimal matching.

It is also noted that the charging currents from the charge injection circuit could be applied directly to the capacitor at nodes A, B. However, if these charging currents have a common-mode dc current component, this dc current will flow through the diodes 42, 44, thereby changing their dc biases, which then changes the unity gain of the bootstrap circuit. Thus, the preferred nodes for charge injection are nodes E, F. Since the impedances of the diodes are small compared to RL, the charging currents will appear at the capacitor.

The integrator according to the invention may be used in various applications, most preferably in the device for clock recovery and data retiming for random NRZ data, as disclosed in U.S. Pat. No. 5,012,494, incorporated by reference herein.

The unity gain positive feedback technique allows an integrator to be implemented with IC technology and one external capacitor. Compared to traditional integrators based on op-amps (negative feedback with infinite gain), this has advantages of not needing compensation for stability. This is especially important in high-speed processes where negative feedback and compensation is very difficult. The reduction in active area is also tremendous.

The addition of the programmable charging currents to the bootstrapped capacitor enables designs of phase-lock loops to work over a very wide range of frequencies with the same capacitor without tradeoffs in stability in the overall loop. In the past, to operate a phase-lock loop at 1/n of the desired frequency, the value of the capacitor would have to be n times larger to maintain the same stability margin for the loop. With the present invention, the charging current to the capacitor could easily be programmed to be n times smaller, thereby maintaining the same capacitor value.

Numerous variations of the invention will be evident to one of ordinary skill; therefore, the scope of the claims is not intended to be limited to the described embodiments.

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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US5677642 *Nov 1, 1994Oct 14, 1997At&T Global Information Solutions CompanySignal generator with supply voltage tolerance
EP1211808A1 *Nov 14, 2001Jun 5, 2002Philips Electronics N.V.Apparatus for pulse width modulating very high frequency signals
Classifications
U.S. Classification327/345, 327/482, 327/199, 327/215, 327/589, 327/341, 327/336
International ClassificationG06G7/184
Cooperative ClassificationG06G7/184
European ClassificationG06G7/184
Legal Events
DateCodeEventDescription
Apr 29, 2008FPExpired due to failure to pay maintenance fee
Effective date: 20080312
Mar 12, 2008LAPSLapse for failure to pay maintenance fees
Sep 17, 2007REMIMaintenance fee reminder mailed
Feb 22, 2006ASAssignment
Owner name: AVAGO TECHNOLOGIES GENERAL IP PTE. LTD., SINGAPORE
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AGILENT TECHNOLOGIES, INC.;REEL/FRAME:017207/0020
Effective date: 20051201
Sep 12, 2003FPAYFee payment
Year of fee payment: 8
May 30, 2000ASAssignment
Owner name: AGILENT TECHNOLOGIES INC, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HEWLETT-PACKARD COMPANY;REEL/FRAME:010977/0540
Effective date: 19991101
Owner name: AGILENT TECHNOLOGIES INC INTELLECTUAL PROPERTY ADM
Apr 28, 2000ASAssignment
Owner name: HEWLETT-PACKARD COMPANY, A DELAWARE CORPORATION, C
Free format text: MERGER;ASSIGNOR:HEWLETT-PACKARD COMPANY, A CALIFORNIA CORPORATION;REEL/FRAME:010841/0649
Effective date: 19980520
Sep 10, 1999FPAYFee payment
Year of fee payment: 4