|Publication number||US5517047 A|
|Application number||US 08/287,773|
|Publication date||May 14, 1996|
|Filing date||Aug 9, 1994|
|Priority date||Jul 28, 1992|
|Also published as||US5362667, US5728624|
|Publication number||08287773, 287773, US 5517047 A, US 5517047A, US-A-5517047, US5517047 A, US5517047A|
|Inventors||Jack H. Linn, Robert K. Lowry, George V. Rouse, James F. Buller, William H. Speece|
|Original Assignee||Harris Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (11), Non-Patent Citations (4), Referenced by (49), Classifications (16), Legal Events (8)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This is a division of application Ser. No. 07/921,197 filed on Jul. 28, 1992, U.S. Pat. No. 5,362,667.
The present invention relates to electronic integrated circuits and methods of fabrication, and, more particularly, to dielectrically isolated semiconductor integrated circuits and related fabrication methods.
Integrated circuits fabricated in silicon-on-insulator substrates offer performance advantages including freedom from latchup for CMOS structures, high packing density, low parasitic capacitance, low power consumption, radiation hardness, high voltage operation, and the possibility of three dimensional integration. Indeed, isolation trenches extending through the silicon layer down to the insulation provide a simple approach to dielectric isolation of integrated circuit devices. The sidewalls of such trenches are coated with an insulator, usually silicon dioxide ("oxide"), and the remaining portion of trench opening, if any, is filled with a filler which is usually polycrystalline silicon. Diffused PN junctions can also be used for lateral isolation.
Additionally, silicon-on-insulator technology using very thin films offers special advantages for submicron devices. Scaling bulk devices tends to degrade their characteristics because of small-geometry effects, such as punch-through, threshold voltage shift, and subthreshold-slope degradation. The use of silicon-on-insulator devices suppresses these small-geometry effects. Therefore, even in the submicron VLSI era, silicon-on-insulator technology can offer even higher device performance than can bulk technology, along with the inherent advantages of silicon-on-insulator.
Silicon-on-insulator substrates may be fabricated in various ways: a crystalline silicon layer may be formed over an existing oxide layer either by laser or strip heater recrystalization of polysilicon deposited on the oxide or by selective epitaxial silicon growth over the oxide. However, the quality of such a silicon layer is generally inferior to that normally associated with bulk silicon. Other approaches form an oxide layer beneath an existing high quality silicon layer either by oxidizing a buried porous silicon layer or by oxygen ion implantation; however, such oxide is low quality and the silicon top layer may be damaged during the oxide layer formation.
Another approach to silicon-on-insulator is wafer bounding as described by J. Lasky et al., Silicon-On-Insulator (SOI) by Bonding and Etch-Back, 1985 IEDM Tech. Deg. 684. This wafer bonding process proceeds as follows: a lightly doped epitaxial layer of silicon is grown on a heavily doped silicon substrate, oxide is thermally grown on the epilayer, a second lightly doped silicon substrate is thermally oxidized, the two oxidized surfaces are pressed together. See FIG. 1a. The pressed together wafers are inserted into an oxidizing atmosphere at 1,100° C. to bond them as illustrated in FIG. 1b. Lastly, a preferential etch is used to remove the heavily doped substrate, leaving the thin, lightly doped epitaxially layer above the bonded thermally grown oxides which are now on the second substrate as shown in FIG. 1c. The resulting thin silicon layer above the thermally grown oxide has high quality and the oxide also retains its quality and may be thick, as might be desired for CMOS or high voltage devices, or then, as might be desired for shared element applications. FIG. 1d heuristically illustrates trench isolation with poly filled trenches isolating MOSFET and bipolar devices.
Conceptually, this process may meet all the desired goals for the ultimate silicon-on-insulator material (a specular finished crystalline silicon layer without dislocations and a back interface with the insulator of quality equal to the interface of thermally grown silicon dioxide on silicon; both the crystalline silicon layer and the insulator of variable thickness).
Another wafer bonding method, illustrated in FIGS. 2a-c and described in copending U.S. patent application Ser. No. 07/834,439, filed Feb. 12, 1992, U.S. Pat. No. 5,266,135, proceeds as follows. Start with a device wafer having a lightly doped epilayer on a heavily doped substrate and a handle wafer with a thick (4,000 A) oxide layer. Activate the surface of the device wafer with an acid or peroxide wash to enhance hydroxyl group formation. Place a drop of oxidant such as water plus hydrogen peroxide on the oxide, and squeeze the wafers together. See FIG. 2a. The drop of oxidant has a volume in the range of 0.8 to 8.0 microliters per square inch of wafer surface. Dry the squeezed wafers at room temperature for a day and then heat the squeezed wafers to 1150 degrees C. for two hours. The heating drives an oxidation of the device wafer and the silicon-oxygen bonds formed fuse the two wafers. See FIG. 2b. Lastly, grind and etch the device wafer until exposure of the device epilayer. This completes the silicon-on-insulator substrate as shown in FIG. 2c. For applications requiring a thick (10-60 μm) silicon-on-insulator layer and a thicker (e.g., 4 μm) bottom oxide, but allowing some tolerance in the layer thickness, a slightly simpler process could be used. A uniformly lightly doped device wafer could be used, and the thinning process could be just grinding and polishing.
However, bonded wafers have problems with the buried oxide not being radiation hardened without an implant through the device layer. And an implant would only be applicable to device layers with thicknesses of up to about 2-3 μm. It has been demonstrated that implanting electronegative elements, like nitrogen, will enhance radiation tolerance. Implanting these dopants can be a problem in that silicon crystal defects are created in the device layer during implant. High temperature annealing can "heal" many of these implant defects, however, a great deal of thermal processing is required and some defects will remain.
Implanting dopants can also result in conducting "pipes" within the buried dielectric. These can be caused by particulates on the surface of the wafer preventing the correct dopant concentration from being implanted to produce a stoichiometric dielectric.
It is also difficult to control any doped buried layers introduced into the silicon prior to wafer bonding due to the high temperature of the bonding process and subsequent anneals.
Bonded wafers also have inherent stresses which can result in cracked or debonded areas due to mismatches in coefficients of thermal expansion between the substrate layers and bonding layer.
Bonded waters with silicon dioxide buried layers are also susceptible to contaminant diffusion as oxides are poor diffusion barriers to mobile ions like sodium. Contaminants introduced during the bonding process can easily diffuse to the device layer interface and result in electrical stability problems.
The present invention provides bonded wafer processing with the features of (1) relatively low temperature bonding by the use of low temperature, chemical oxidizers, (2) dielectric hardening by the use of chemical dopants directly in the bonding liquid without the use of high energy, silicon damaging implants, (3) better stress compensation by providing dopants in the bonding liquid which will produce a bonding layer which has closely matched coefficients of thermal expansion to that of the substrate wafers, (4) limiting contaminant migration by the use of dopants in the bonding liquid which will produce a bonding layer which is a barrier to diffusion of mobile contaminants, (5) a method of simultaneously producing a buried doped layer in the silicon during the bonding process, and (6) a method of producing a bonded wafer with a multi-level buried dielectric sandwich from pre-deposited dielectric layers on both wafers.
The present invention will be described with reference to the accompanying drawings, which are schematic for clarity:
FIGS. 1a-d illustrate in cross sectional elevation views known wafer bonding methods and integrated circuits;
FIGS. 2a-c illustrate in cross sectional elevation views a copending wafer bonding method;
FIGS. 3a-i are cross sectional elevation views of a first preferred embodiment method of wafer bonding and a SIMS profile of the result plus a comparison SIMS profile;
FIG. 4 shows a third preferred embodiment method;
FIGS. 5a-b are cross sectional elevation views of a fourth preferred embodiment;
FIGS. 6-8 illustrate further preferred embodiment methods; and
FIG. 9 shows in cross sectional elevation view a portion of a preferred embodiment integrated circuit.
FIGS. 3a-e illustrate in cross sectional elevation view a first preferred embodiment method of bonded wafer processing.
(a) Begin with a four inch diameter 500 μm thick silicon device wafer 302 and a comparable diameter 500 μm thick silicon handle wafer 312. Device wafer 302 has the doping type and resistivity (e.g., N type and 20 ohm-cm resistivity) desired for eventual device fabrication and has only native oxide on its surfaces. Thermally oxidize handle wafer 312 to form oxide layers 314 and 316. Oxide 316 will become the bottom oxide, so the oxide is grown to the desired bottom oxide thickenss; for example, 4 μm. Oxide 314 provides stress compensation to restrain warpage. Place drop 305 of oxidizing aqueous solution of HNO3 and H2 O2 on oxide 316; see FIG. 3a. Drop 305 is 20% by volume a 67% HNO3 solution and 80% by volume a 30% H2 O2 solution. Other mixtures also work. Drop 305 has a volume of about 0.05 cc which implies 4.0 microliters per square inch of wafer surface and theoretically will spread out to a layer with thickness (if uniform) of 6 μm on oxide 316. Note that drop 305 wets the surface of oxide 316. (Drop volume in the range of 4 to 10 microliters per square inch of wafer surface provides good bonding.) A buried layer in the final device structures will be formed as part of the bonding process, so device wafer 302 does not require an implant.
(b) Press handle wafer 312 and device wafer 302 together with drop 305 of first preferred embodiment oxidizer on the surface of oxide 316. Let the pressed together wafers dry for 24 hours and then heat them to 800°-1000° C. in a 2-6 hour furnace cycle with an oxidizing ambient. This low temperature bonding does not depend entirely on oxidation as in the process of FIGS. 2a-c, but is coupled with an oxidation reduction reaction of nitrate oxidizing the silicon of wafer 302 coupled with slow thermal oxidation. See FIG. 3b. The nitrate forms both silicon-oxygen and silicon-nitrogen bonds, and the water primarily evaporates. The reactions basically are:
Si+HNO3 +H2 O2 →Siw Ox Ny +H2 O+O2
This creates bonded zone 315 of a mixture of silicon oxynitrides ("nitrox") connecting the remainder of device wafer 302 to oxide 316 and handle wafer 312. Bonded zone nitrox 315 has a thickness of roughly 500-800 Å and average values of x and y of roughly 0.8 and 0.2, respectively. FIG. 3h shows a SIMS (secondary ion mass spectroscopy) profile of the bonded wafer structure with nitrox apparent between the oxide (lefthand portion of FIG. 3h) and the silicon (center and righthand portion). FIG. 3i shows for comparison a SIMS profile of a bonded wafer made by the process of FIGS. 2a-c and with nitrogen implanted to the oxide-silicon interface. The nitrox in FIG. 3h is confined to a 500-800 Å, thick bonding zone and avoids the long nitrogen tails due to implantation straggle apparent in FIG. 3i. Of course, increasing the ratio of HNO3 to H2 O2 will increase x and decrease y and somewhat increase the thickness of bonded zone nitrox 315; and conversely for a decrease in the ratio.
(c) After bonding, remove the bulk of device wafer 302 by grinding, lapping, and polishing to leave the desired device island thickness; for example, 35-40 μm. This thinning of device wafer 302 proceeds without any etchstop, so the final thickness of device wafer 302 depends upon process control. See FIG. 3c. The use of an etchstop permits much smaller device island thicknesses, such as 1 μm.
(d) Thermally grow mask oxide 326 on device wafer 302 to a thickness of about 4 μm, this increases backside oxide 314 on handle wafer 312 to about 4.5 μm but will not affect bond nitrox layer 315 or bottom oxide layer 316. Mask oxide 326 will be used as a trench etch mask. See FIG. 3d.
(e) Print a trench pattern into photoresist spun onto mask oxide 326. Note that the bottom oxide 316 (4 μm), the mask oxide 326 (4 μm) and the backside oxide 314 (4.5 μm) are all fairly closely matched in thickness during the photoresist patterning, and bond nitrox layer 315 is fairly thin. This provides a rough stress balance and limits warpage of the bonded wafers. Use the patterned photoresist as etch mask to wet etch (HF) the trench pattern in oxide 326. The wet etch removes 4 μm from backside oxide 314 to leave only 0.5 μm. Then strip the photoresist and use the patterned oxide 326 to plasma reactive ion etch (RIE) device wafer 302 to form silicon islands 322, 323, . . . on bond nitrox layer 315. See FIG. 3e.
(f) Strip patterned oxide 326 with a wet etch. This etch also removes the remaining backside oxide 314 on the back of handle wafer 312. Then thermally grow oxide to a thickness of 4 μm to form isolation oxide 336 on the sides of islands 322, 323, . . . This also forms 4 μm of oxide 338 on the island surfaces and 4 μm of backside oxide 346 on handle wafer 312. Next, deposit polysilicon 348 to fill the trenches. Lastly, planarize to remove the polysilicon except from the trenches. See FIG. 3f. Note that again the island surface oxide 338, bottom oxide 316, and backside oxide 346 all have about the same thickness (4 μm).
(g) Fabricate devices in islands 322, 323, . . . with repeated cylces of (1) thermally grow oxide layer, (2) spin on photoresist using a spinner vacuum chuck, (3) pattern the photoresist using an aligner vacuum chuck, (4) wet etch the oxide using the patterned photoresist as etch mask, (5) and diffuse or implant or etch silicon using the patterned oxide as diffusion/implant/etch mask. FIG. 3g illustrates in magnified view a partially completed MOSFET in island 322 which would be just one of thousands of such devices in an integrated circuit fabricated on the bonded wafer.
An advantage of silicon-on-insulator integrated circuits with devices overlying bond nitrox layer 315 rather than just bottom oxide layer 316 lies in their radiation hardness. Radiation affects a typical silicon-on-oxide structure by generating positive charges at the silicon-oxide interface. These positive charges will shift a MOSFET threshold due to the body effect. However, nitrogen in nitrox layer 315 will neutralize positive charges at the interface.
Also, nitrox layer 315 has a higher dielectric constant than bottom oxide layer 316. In fact, the dielectric constant of nitride is about 7.9 and that of oxide is about 3.9.
Experimental bonding temperatures of 850° C. and 1000° C. appear to yield bonded wafers with as good a bond as those bonded at 1150° C., which is the bonding temperature in the method of FIGS. 2a-c.
The second preferred embodiment method of bonded wafer processing follows the steps of the first preferred embodiment method but augments or replaces the oxidizer of drop 305 by a silicon oxidizer such as aqueous HClO4. For example, the drop could be 50% HNO3, 20% HClO4 and 30% H2 O2, or 100% HClO4. The same relatively low temperature bonding occurs, and the chlorine ends up bonded in the silicon interface nitrox or oxide layer. The chlorine provides an additional neutralizer for positive charge generated at the silicon interface due to radiation. In this sense, perchlorate is similar to nitrate in that it both oxidizes silicon and provides positive charge neutralization. Of course, other oxidizers of silicon such as CrO3, H2 Cr2 O7, . . . can be used for the relatively low temperature bonding. These oxidizers will leave Cr, . . . in the silicon interface bonded layer, and electronegative ones will aid radiation hardness by neutralizing positive charges.
The third preferred embodiment method follows the steps of the first preferred embodiment method, but augments the oxidizer of drop 305 with radiation hardening dopants such as F, S, P, . . . which will remain (at least in part) at the silicon interface during bonding. That is, in addition to HNO3 for relatively low temperature bonding, drop 305 contains dopants such as HF, H2 S, POCl3, . . . which will generate electronegative dopants to neutralize radiation-generated positive charges as they arise. Thus oxidizers such as dichromate plus electronegative dopants could provide both the low temperature bonding plus radiation hardening. Alternatively, a high temperature bonding (H2 O2 alone) with these dopants would provide a doped oxide bonded layer which included radiation hardening.
The fourth preferred embodiment method follows the steps of the first preferred embodiment method, but augments the oxidizer of drop 305 with buried layer dopants such as As, P, B, Sb, . . . which will diffuse into the bottoms of silicon islands 322, 323, . . . during bonding and form buried layers. That is, in addition to HNO3 for relatively low temperature bonding, drop 305 contains dopants such as As2 O3, POCl3, . . . which will generate the electrically active dopants such as As, P, B, Sb, in the device wafer during bonding. A portion of these dopants will diffuse to form buried layer 420 as illustrated in FIG. 4 with device wafer 402, handle wafer 412, bottom oxide 416, and bonded nitrox 415. The doping concentrations of the buried layers in the silicon depends upon the quantity of dopants initially introduced into drop 305. For example, if drop 305 were 1% dopant, then the drop would provide a dose on the order of 1018 dopant atoms per cm2 of interface. Thus drop 305 can easily accomodate sufficient dopants even if only a small fraction of the dopants actually migrate out of the bonding zone during nitrox layer growth. Indeed, implantation of a buried layer typically uses an implant dose on the order of 1016 dopant atoms/cm2. Recall that nitrox is a diffusion barrier for various dopants. Bonding at 1000° C. will help diffuse the dopants in the silicon and may be useful with thicker silicon islands.
Of course, a high temperature bonding (e.g., H2 O2 alone) with these dopants would also yield buried layers, but the high bonding temperatures would diffuse the dopant much further into islands 322, 323, . . . and would not be useful for the case of very thin islands. For example, if islands 322, 323, . . . were only 1 μm thick, then a 2-6 hours bonding at 1150° C. would drive dopants throughout the islands.
FIGS. 5a-b show modifications of the starting wafers for first preferred embodiment wafer bonding method. In particular, FIG. 5a has device wafer 502 again with only native oxides, but handle wafer 512 has both 4000 A thick bottom thermal oxide 516 and 1000 A thick deposited nitrox layer 517. Nitrox layer 517 has the composition Siw Ox Ny with x approximately equal to 0.6 and y approximately equal to 0.4 and may be formed by decomposition of silane with ammonia and oxygen. Drop 505 is a solution of HNO3 to provide oxidation of wafer 502 and bonding at 800°-1000° C. The resulting bonded wafer illustrated in FIG. 5b includes bonded nitrox layer 515 of approximate thickness 500-800 A and composition Siw Ox Ny with x approximately equal to 0.8 and y approximately equal to 0.2. The stack of bonded nitrox layer 515 on deposited nitrox layer 517 provides the advantages of (1) specifying the thickness and stoichiometry of buried nitrox 517 before deposition, (2) allowing a transition nitrox layer with different stoichiometry for matching stress and coefficients of thermal expansion, and (3) providing a barrier to contaminant diffusion if nitrox layer 517 is doped. Of course, dopants either for buried layers in device wafer 502 or for radiation hardening the bonded nitrox 515 or both could be included in the oxidizer drop 505.
Deposited nitrox 517 could be replaced with deposited and steam densified aluminum oxide (pseudo-sapphire) also of thickness about 1000 A. The bonded wafers would then be separated by a stack of dielectrics: nitrox 515 on aluminum oxide 517 which is on thermal oxide 516. This inclusion of nitrox 515 on top of aluminum oxide 517 has the advantages of (1) increased radiation hardness of pseudo-sapphire layer, (2) the presence of a diffusion barrier (nitrox 515) to keep the aluminum in 517 from diffusing into the device silicon, and (3) a more closely matched thermal coefficient of expansion of nitrox 517 to the bonding nitrox layer and silicon device wafer than aluminum oxide 517.
FIG. 6 illustrates a variation of deposited nitrox/aluminum oxide layer 517 of FIG. 5a where additional silicon to aid the bonding has been included. In particular, handle wafer 612 has 4000 A thick bottom oxide 616, 500 A thick deposited nitrox or aluminum oxide 617, plus 300 A thick polysilicon layer 618. Again, drop 605 contains an oxidizing solution such as HNO3 plus H2 O2. Bonding liquid oxidizes polysilicon 618 to nitrox in a manner similar to the oxidation of the surface portion of wafer 602. In effect, the nitrox can form at both surfaces of the oxidizing liquid (drop 605 squeezed between the wafers). Drop 605 when uniformly spread over wafers 602 and 612 will form a layer about 6 μm thick and provide sufficient oxidizers to totally consume polysilicon layer 618 plus at least 300-500 A of device wafer 602. The advantage of polysilicon layer 618 is that (1) it supplied a source of silicon for the bonding liquid to react with to form nitrox in the bonding zone without consuming substantial amounts of device wafer 602 (which might be doped), (2) it can be polished to provide a smooth surface for bonding if the underlying deposited dielectrics are rough, and (3) it can be thermally oxidized before bonding to provide a layer of silicon oxide between the deposited dielectric, the bonding nitrox and device wafer 602.
Method with dielectric layers on both wafers
FIGS. 7a-b illustrate in cross sectional elevation views another preferred embodiment wafer bonding method; this method employs dielectric layers on both wafers and supplies the silicon for bonding as part of the bond process as follows.
(a) Begin with 6-inch diameter 600 μm thick silicon device wafer 702 and 6-inch diameter 600 μm thick silicon handle wafer 712. Device wafer 702 has the doping type and resistivity desired for eventual device fabrication. Grow thermal oxides 704 and 706 on device wafer 702 and oxides 714 and 716 on handle wafer 712. Oxide 716 will become the bottom oxide, so the oxide is grown to the desired bottom oxide thickenss; for example, 1 μm. Oxide 714 provides stress compensation to restrain warpage. Deposit 1000 A thick silane-rich nitrox layer 717 on oxide 716 and silane-rich nitrox layer 707 on oxide 706 by a decomposition of silane with ammonia and oxygen. Nitrox layers 717 and 707 have the composition Siw Ox Ny with x approximately equal to 0.6 and y approximately equal to 0.4 plus unreacted silane (SiH4). (Unreacted silane in the nitrox can be detected by infrared spectroscopy). Place drop 705 of oxidizing aqueous solution of HNO3 and H2 O2 on oxide 716; see FIG. 7a. Drop 705 is 50% by volume a 67% HNO3 solution and 50% by volume a 30% H2 O2 solution. Drop 705 has a volume of about 0.05 cc which implies 4.0 microliters per square inch of wafer surface and theoretically will spread out to a layer with thickness (if uniform) of 6 μm on oxide 716. Note that drop 705 wets the surface of nitrox 716. (Drop volume in the range of 4 to 10 microliters per square inch of wafer surface provides good bonding.)
(b) Press handle wafer 712 and device wafer 702 together with drop 705 of oxidizer on the surface of oxide 716. Let the pressed together wafers dry for 24 hours and then heat them to 800°-1000° C. in a 2-6 hour furnace cycle with an oxidizing ambient. This low temperature bonding does not drive rapid thermal oxidation as in the process of FIGS. 2a-c, but relies upon the electrochemical action of nitrate oxidizing the silicon of silane-rich nitrox 707 and 717 coupled with slow thermal oxidation. See FIG. 7b. Even though nitride is an oxidation barrier for silicon, the unreacted silane can diffuse from the film to react with the nitrate. The silane forms both silicon-oxygen and silicon-nitrogen bonds, and the water primarily evaporates. This creates bonded zone 715 of nitrox connecting nitrox 707 to nitrox 717, both now depleted of silane, and bonding the wafers. Bonded zone nitrox 715 has a thickness of roughly 500-800 Å μm and average values of x and y of roughly 0.8 and 0.2, respectively. Of course, increasing the ratio of HNO3 to H2 O2 will increase x and decrease y, and conversely for a decrease in the ratio.
(c) After bonding, remove the bulk of device wafer 702 and form isolated silicon islands for device fabrication as in the first preferred embodiment.
FIG. 8 illustrates the starting wafers for a further preferred embodiment method of wafer bonding. Device wafer 802 has thermal oxide layer 806 of thickness 0.1-0.4 μm and polysilicon layer 808 of thickness 500 Å. Similarly, handle wafer 812 has deposited or thermally grown dielectric layer 816 of thickness 1 μm and may have polysilicon layer 818 of thickness 500 Å. Drop 806 contains silicon oxidizer HNO3. When wafers 802 and 812 are pressed together and heated to 800°-1000° C. for 2-4 hours, the nitrate reacts with the polysilicon to form silicon-nitrogen and silicon-oxygen bonds (nitrox) linking oxide 806 to oxide 816 and bonding the wafers. The quantity of nitrate in drop 805 matches the quantity of polysilicon in layers 808 and 818 for stoichiometric nitrox, as follows. 1000 Å total thickness of polysilicon provides about 3×1017 atoms of silicon per cm2. With HNO3 the only oxidizer, the reaction generates nitrox 815 through the reaction:
4Si+2HNO3 →Si4 O5 N2 +H2 O
Thus about 1.5×1017 molecules of HNO3 are needed per cm2. With drop 805 of volume spreading out to about 4 microliters per cm2, the concentration of HNO3 in drop 805 must be about 4×1022 molecules per liter, or about 0.07M.
The use of polysilicon 808 and 818 as the source of silicon permits more rapid bonding because silicon need not diffuse through oxides 806 and 816 to react. Indeed, oxides 806 and 816 could be replaced in part by nitrides which would be barriers to oxidation of the underlying wafer silicon, but the bonding would still proceed using silicon from polysilicon 806 and/or 816.
Controlling the bonding liquid and overall dielectric thicknesses promotes unstressed chemical bonding gradients between the deposited dielectric(s) and the reacted dielectric. Maintaining minimum film thicknesses is critical in helping to eliminate localized stress caused by dissimilar dielectric materials. It is imperative that the bonding liquid provide the correct elements and oxidative potential to not etch the deposited dielectric, as well as create reacted layers with compatible coefficients of thermal expansion. This will allow a chemical bonding transition from the deposited dielectric(s) through the generated dielectric into the silicon. This is accomplished by controlling the elements in the bonding liquid, molar concentration ratios, solution volumes and bonding temperature.
Devices and integrated circuits fabricated in silicon-on-insulator of the bonded wafers of the preferred embodiment methods and then diced are schematically illustrated in cross sectional elevation view in FIG. 9 and have the following properties:
Radiation hardened buried insulators for increased radiation tolerance in military and space IC applications without the characteristics of implanted hardening: silicon crystal damage from implanting, conducting "pipes" in the buried dielectric which can result from surface particulates preventing the correct implant dosage from reaching the buried layer in the silicon to form a stoichiometric dielectric.
Tight buried layers due to no implant tailing, relatively low wafer bonding temperature, and no defect annealing.
Stress compensation due to incorporation of buried layers with closely matched thermal coefficients of expansion.
Layers which can function as diffusion barriers to limit the diffusion of mobile contaminants.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4878957 *||Mar 30, 1989||Nov 7, 1989||Kabushiki Kaisha Toshiba||Dielectrically isolated semiconductor substrate|
|US5187636 *||Apr 21, 1992||Feb 16, 1993||Rohm Co., Ltd.||Dielectric device|
|US5236546 *||Dec 12, 1991||Aug 17, 1993||Canon Kabushiki Kaisha||Process for producing crystal article|
|US5241211 *||Oct 11, 1991||Aug 31, 1993||Nec Corporation||Semiconductor device|
|US5294821 *||Oct 8, 1991||Mar 15, 1994||Seiko Epson Corporation||Thin-film SOI semiconductor device having heavily doped diffusion regions beneath the channels of transistors|
|US5322589 *||Apr 21, 1993||Jun 21, 1994||Fujitsu Limited||Process and apparatus for recrystallization of semiconductor layer|
|US5362667 *||Jul 28, 1992||Nov 8, 1994||Harris Corporation||Bonded wafer processing|
|US5387555 *||Sep 3, 1992||Feb 7, 1995||Harris Corporation||Bonded wafer processing with metal silicidation|
|US5442223 *||Apr 11, 1994||Aug 15, 1995||Nippondenso Co., Ltd.||Semiconductor device with stress relief|
|JPH0218961A *||Title not available|
|JPS5658269A *||Title not available|
|1||Burkhardt, "Composite Silicon Dioxide-Silicon Oxynitride Insulating Layer," IBM Technical Disclosure Bulletin, vol. 13, No. 1, Jun. 1970, p. 21.|
|2||*||Burkhardt, Composite Silicon Dioxide Silicon Oxynitride Insulating Layer, IBM Technical Disclosure Bulletin, vol. 13, No. 1, Jun. 1970, p. 21.|
|3||Haisma, et al., "Silicon-on-Insulator Wafer Bonding-Wafer Thinning Technological Evaluations", Japanese Journal Appl. Phys., vol. 28, No. 8, 1989, Japan.|
|4||*||Haisma, et al., Silicon on Insulator Wafer Bonding Wafer Thinning Technological Evaluations , Japanese Journal Appl. Phys., vol. 28, No. 8, 1989, Japan.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US5729038 *||Dec 15, 1995||Mar 17, 1998||Harris Corporation||Silicon-glass bonded wafers|
|US5783022 *||Oct 31, 1996||Jul 21, 1998||Samsung Electronics Co., Ltd.||Apparatus and methods for wafer debonding using a liquid jet|
|US5841171 *||Nov 18, 1996||Nov 24, 1998||Mitsubishi Denki Kabushiki Kaisha||SOI Semiconductor devices|
|US5863375 *||Apr 28, 1998||Jan 26, 1999||Samsung Electronics Co., Ltd.||Apparatus and methods for wafer debonding using a liquid jet|
|US5914280 *||Dec 23, 1996||Jun 22, 1999||Harris Corporation||Deep trench etch on bonded silicon wafer|
|US5939131 *||Jun 13, 1997||Aug 17, 1999||Samsung Electronics Co., Ltd.||Methods for forming capacitors including rapid thermal oxidation|
|US5982006 *||Dec 9, 1997||Nov 9, 1999||Texas Instruments Incorporated||Active silicon-on-insulator region having a buried insulation layer with tapered edge|
|US5985733 *||Jun 26, 1997||Nov 16, 1999||Hyundai Electronics Industries Co., Ltd.||Semiconductor device having a T-shaped field oxide layer and a method for fabricating the same|
|US6034403 *||Jun 25, 1998||Mar 7, 2000||Acer Semiconductor Manufacturing, Inc.||High density flat cell mask ROM|
|US6037634 *||May 21, 1997||Mar 14, 2000||Mitsubishi Denki Kabushiki Kaisha||Semiconductor device with first and second elements formed on first and second portions|
|US6096583 *||Aug 12, 1998||Aug 1, 2000||Mitsubishi Denki Kabushiki Kaisha||Semiconductor device and manufacturing method thereof|
|US6104081 *||May 18, 1998||Aug 15, 2000||U.S. Philips Corporation||Semiconductor device with semiconductor elements formed in a layer of semiconductor material glued on a support wafer|
|US6133610 *||Jan 20, 1998||Oct 17, 2000||International Business Machines Corporation||Silicon-on-insulator chip having an isolation barrier for reliability and process of manufacture|
|US6198150||Mar 10, 1999||Mar 6, 2001||Intersil Corporation||Integrated circuit with deep trench having multiple slopes|
|US6268630 *||Mar 16, 1999||Jul 31, 2001||Sandia Corporation||Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications|
|US6281095||Sep 4, 1998||Aug 28, 2001||International Business Machines Corporation||Process of manufacturing silicon-on-insulator chip having an isolation barrier for reliability|
|US6492684||Jun 11, 2001||Dec 10, 2002||International Business Machines Corporation||Silicon-on-insulator chip having an isolation barrier for reliability|
|US6531742 *||Dec 26, 2000||Mar 11, 2003||Hyundai Electronics Industries Co., Ltd.||Method of forming CMOS device|
|US6562694 *||Dec 21, 2000||May 13, 2003||Koninklijke Philips Electronics N.V.||Method of manufacturing a semiconductor device comprising semiconductor elements formed in a toplayer of a silicon wafer situated on a buried insulating layer|
|US6563173||May 16, 2001||May 13, 2003||International Business Machines Corporation||Silicon-on-insulator chip having an isolation barrier for reliability|
|US6633061 *||Aug 27, 2001||Oct 14, 2003||Infineon Technologies Ag||SOI substrate, a semiconductor circuit formed in a SOI substrate, and an associated production method|
|US6958282||May 17, 1999||Oct 25, 2005||Siemens Aktiengesellschaft||SOI semiconductor configuration and method of fabricating the same|
|US7075103||Dec 19, 2003||Jul 11, 2006||General Electric Company||Multilayer device and method of making|
|US7169683||Oct 14, 2003||Jan 30, 2007||S.O.I.Tec Silicon On Insulator Technologies S.A.||Preventive treatment method for a multilayer semiconductor structure|
|US7446018||Aug 22, 2006||Nov 4, 2008||Icemos Technology Corporation||Bonded-wafer superjunction semiconductor device|
|US7566631||Apr 26, 2006||Jul 28, 2009||International Business Machines Corporation||Low temperature fusion bonding with high surface energy using a wet chemical treatment|
|US7579667||Aug 13, 2008||Aug 25, 2009||Icemos Technology Ltd.||Bonded-wafer superjunction semiconductor device|
|US7595105||May 25, 2006||Sep 29, 2009||General Electric Company||Multilayer device and method of making|
|US7713837||May 28, 2008||May 11, 2010||International Business Machines Corporation||Low temperature fusion bonding with high surface energy using a wet chemical treatment|
|US7927972 *||Apr 19, 2011||Sumco Corporation||Method for producing bonded wafer|
|US8030133||Oct 4, 2011||Icemos Technology Ltd.||Method of fabricating a bonded wafer substrate for use in MEMS structures|
|US8253243||Jul 8, 2011||Aug 28, 2012||Icemos Technology Ltd.||Bonded wafer substrate utilizing roughened surfaces for use in MEMS structures|
|US8633542 *||Sep 12, 2011||Jan 21, 2014||Semiconductor Energy Laboratory Co., Ltd.||SOI substrate and manufacturing method thereof|
|US8884371||Dec 19, 2013||Nov 11, 2014||Semiconductor Energy Laboratory Co., Ltd.||SOI substrate and manufacturing method thereof|
|US20040126993 *||Dec 30, 2002||Jul 1, 2004||Chan Kevin K.||Low temperature fusion bonding with high surface energy using a wet chemical treatment|
|US20050026391 *||Oct 14, 2003||Feb 3, 2005||Bruno Ghyselen||Preventive treatment method for a multilayer semiconductor structure|
|US20050133781 *||Dec 19, 2003||Jun 23, 2005||General Electric Company||Multilayer device and method of making|
|US20060194414 *||Apr 26, 2006||Aug 31, 2006||International Business Machines Corporation||Low temperature fusion bonding with high surface energy using a wet chemical treatment|
|US20070063217 *||Aug 22, 2006||Mar 22, 2007||Icemos Technology Corporation||Bonded-wafer Superjunction Semiconductor Device|
|US20070069233 *||May 25, 2006||Mar 29, 2007||Min Yan||Multilayer device and method of making|
|US20080315247 *||Aug 13, 2008||Dec 25, 2008||Icemos Technology Corporation||Bonded-wafer superjunction semiconductor device|
|US20090258475 *||Apr 9, 2009||Oct 15, 2009||Sumco Corporation||Method for producing bonded wafer|
|US20100065946 *||Mar 30, 2009||Mar 18, 2010||Icemos Technology Ltd.||Bonded Wafer Substrate for Use in MEMS Structures|
|US20110316082 *||Dec 29, 2011||Semiconductor Energy Laboratory Co., Ltd.||Soi substrate and manufacturing method thereof|
|USRE40339||Dec 3, 2004||May 27, 2008||International Business Machines Corporation||Silicon-on-insulator chip having an isolation barrier for reliability|
|CN1531066B||Feb 10, 2004||Dec 15, 2010||台湾积体电路制造股份有限公司||Manufacture and structure of semiconductor on insulating layer with concave resistance|
|DE19821999A1 *||May 15, 1998||Nov 18, 1999||Siemens Ag||Silicon-On-Isolator semiconductor arrangement|
|WO2005013338A2 *||Jul 29, 2004||Feb 10, 2005||S.O.I.Tec Silicon On Insulator Technologies||Production of a structure comprising a protective layer against chemical treatment|
|WO2005013338A3 *||Jul 29, 2004||Jun 30, 2005||Soitec Silicon On Insulator||Production of a structure comprising a protective layer against chemical treatment|
|U.S. Classification||257/347, 257/E21.564, 257/E21.122, 257/349, 257/639|
|International Classification||H01L21/762, H01L21/20|
|Cooperative Classification||Y10S148/012, Y10S438/92, H01L21/2007, H01L21/76286, H01L21/76275, H01L21/76264, H01L21/76283|
|European Classification||H01L21/762D20, H01L21/20B2|
|Sep 27, 1999||AS||Assignment|
Owner name: INTERSIL CORPORATION, FLORIDA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HARRIS CORPORATION;REEL/FRAME:010247/0043
Effective date: 19990813
|Nov 8, 1999||AS||Assignment|
Owner name: CREDIT SUISSE FIRST BOSTON, AS COLLATERAL AGENT, N
Free format text: SECURITY INTEREST;ASSIGNOR:INTERSIL CORPORATION;REEL/FRAME:010351/0410
Effective date: 19990813
|Nov 12, 1999||FPAY||Fee payment|
Year of fee payment: 4
|Nov 14, 2003||FPAY||Fee payment|
Year of fee payment: 8
|Nov 14, 2007||FPAY||Fee payment|
Year of fee payment: 12
|Nov 19, 2007||REMI||Maintenance fee reminder mailed|
|May 5, 2010||AS||Assignment|
Owner name: MORGAN STANLEY & CO. INCORPORATED,NEW YORK
Free format text: SECURITY AGREEMENT;ASSIGNORS:INTERSIL CORPORATION;TECHWELL, INC.;INTERSIL COMMUNICATIONS, INC.;AND OTHERS;REEL/FRAME:024390/0608
Effective date: 20100427
|May 26, 2010||AS||Assignment|
Owner name: INTERSIL CORPORATION,FLORIDA
Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CREDIT SUISSE FIRST BOSTON;REEL/FRAME:024445/0049
Effective date: 20030306