|Publication number||US5517496 A|
|Application number||US 08/316,527|
|Publication date||May 14, 1996|
|Filing date||Sep 30, 1994|
|Priority date||Oct 20, 1993|
|Also published as||DE69415278D1, DE69415278T2, EP0652662A1, EP0652662B1|
|Publication number||08316527, 316527, US 5517496 A, US 5517496A, US-A-5517496, US5517496 A, US5517496A|
|Inventors||Pierre Boyer, Jean-Pierre Coudreuse, Michel Servel|
|Original Assignee||France Telecom|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (5), Referenced by (3), Classifications (15), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention concerns an input queueing system intended primarily for connection to the inputs of a space-division switching matrix.
Asynchronous time-division switching networks are divided into several classifications, among which two main categories stand out. The first is based on the use of non-blocking space-division switching matrices monitored by queues linked to outputs. "COPRIN" type switches are typical of this category. By contrast, the second category uses input queues monitored by non-blocking space-division switches, for example switching matrices of the "BATCHER BANYAN" type.
Networks in the first category have the undeniable advantage of minimizing idle time and dither, while being able to accept, on account of their design, a relatively high internal load.
However, the entire content of the cells must be transferred to what may be termed a supermultiplex, thus restricting the capacity for uninhibited switching when relatively high throughputs are used. For example, throughputs in the order of 20 Gbit/s may be envisaged when the most up-to-date technology is used. It should be noted that in many applications, this type of technology is satisfactory.
In excess of these throughputs, however, staging of the matrices is necessary, leading generally to a multiplication of the queues through which the cells must pass. Blocking when communication is established also occurs, but in view of the large multiplex throughput and the large number of multiplexed virtual circuits, this parameter does not pose too many problems.
The drawback of the second category of networks to date is that they do not allow for the possibility of cell distribution during switching, unless a large number of circuits are added for saving and copying the cells. Moreover, intrincisally, their admissible load is restricted to 0.59. They also produce a longer delay and traversal delay dispersion than the first category and require, depending on the design specifications, a greater number of interconnections in view of the greater number of stages.
Solutions of varying degrees of success have been proposed to overcome these limitations, but in many cases these proposals are extremely expensive. One of the more recent proposals is based on the use of a content addressable memory (CAM). This is more attractive than the others, in that it proposes to convert the input queue associated with a "BATCHER BANYAN" matrix into a queue in which the first input cell exits at a moment dependent on the resolution of conflicts caused by the various requests for access to the same output originating from other inputs. During a time slot, requests for access to outputs are directed to a request processing circuit which, during the above-mentioned time slot and for each input queue, provides the first available time slot interval at the requested output, taking into account all other requests.
This proposal is described in the article entitled "A Scheduling Content-Addressable Memory for ATM Space Division Switch Control", published in IEEE International Solid-State Circuits Conference, 1991, page 244, under the authorship of Masao Akata et al, NEC Corporation, Japan.
To put into perspective the performance of this device, its design--despite an improvement of the CAM memory--results in an analysis time triple that required for access to a dual-access static memory produced with the same technology. The drawback of this method is that it requires a specific circuit operating in a relatively complex manner which, as a consequence, restricts the overall switched throughput.
The present invention proposes an input queueing system of the second category, capable of performing close to the output order of the first network category, but able to operate at higher speeds than these networks. An attempt has thus been made to multiply fourfold the overall switched throughput using equivalent technology.
For this purpose, the inputs of a switching matrix are connected to an input queueing system designed in accordance with the invention, comprising a succession of input circuits in which the inputs receive cells of the type used in a data transmission and/or ATM system, and the outputs are connected respectively to the corresponding inputs of the switching matrix, each input circuit containing a further series of inputs in a one-to-one relation with the switch matrix outputs, each designed to carry, during each time slot, a series of availability signals to which are assigned time slots later than the current time slot, whereby each availability signal indicates an available condition at the matrix output corresponding to the input carrying it, for the emission of a cell at the time slot assigned to the signal, and each input circuit is capable of storing, in a memory pocket, one cell present at its input at an address in relation to a time slot assigned to an availability signal indicating an available condition for emission of the cell to the matrix output to which is it addressed, the availability signal then indicating, after the storing operation, a non-available status, and the memory being read at an address corresponding to the current time slot, such that the cell stored at that address is sent to the switching matrix.
Furthermore, in accordance with the invention, in each input circuit the availability signals carried by an input during a time slot are respectively present at this input during the micro-intervals that subdivide each time slot, and are respectively assigned time slots later than the current time slot.
Furthermore, in accordance with the invention, these micro-intervals are determined by signals emitted by a time base, whereby the storage address of the cell present at the input of the input circuit is determined from the value taken by the micro-interval time signals when the availability signal at the input corresponding to the switch matrix output to which the current cell is addressed indicates an available condition.
Furthermore, in accordance with the invention, each input circuit contains a memory for storing the cell present at its input, the memory being read addressed by a local time signal sent by the time base, then write addressed by the micro-interval time signals sent by the time base.
Furthermore, the invention comprises the means for preventing a cell that has already been stored from being stored again.
Furthermore, in accordance with the invention, each input circuit is provided with m outputs corresponding to m inputs, to which are sent updated availability signals, the m outputs of an input circuit being connected to m inputs of the next input circuit in the succession of input circuits.
Furthermore, the updated availability signals sent to the m outputs of an input circuit are transmitted to m inputs of the next input circuit in succession with a delay equal in duration to that of one micro-interval, the time base of an input circuit being offset by one micro-interval from one input circuit to the next.
Furthermore, in accordance with the invention, each input circuit contains an assignment circuit intended to scrutinize the availability signals present at the m inputs of the input circuit and send updated availability signals to the m outputs of the input circuit, plus a control signal which, when active, controls the storage of the cell present at the input of the input circuit.
Furthermore, in accordance with the invention, the assignment circuit contains inputs which receive outgoing direction signals indicating the switch matrix output to which the cell currently present at the input of the input circuit is addressed.
Furthermore, in accordance with the invention, the assignment circuit comprises a number of AND gates with at least two inputs, the first receiving outgoing direction signals and the second receiving availability signals. The gate outputs are connected respectively to the inputs of an OR gate, the output of which constitutes the output of the assignment circuit. The output of each gate of row j is also connected to one input of an OR gate, the second input of which receives an availability signal, while the OR gate outputs are connected respectively to the outputs of the assignment circuit sending the updated availability signals.
The above-mentioned characteristics of the invention, and others, can be more clearly understood by reading the following description of a sample application of the invention, to be read in conjunction with the enclosed diagrams, which are as follows:
FIG. 1 is a synoptic diagram of a switching network equipped with an input queueing system according to the invention,
FIG. 2 is a synoptic diagram of an input circuit constituting one element of an input queueing system according to the invention,
FIG. 3 is an operating diagram of an input circuit according to the invention,
FIG. 4 is a synoptic diagram of an assignment circuit incorporated in an input circuit of a system according to the invention, and
FIG. 5 is a synoptic diagram of a variant of the assignment circuit, allowing the capacity of a system according to the invention to be extended.
The switching network shown in FIG. 1 consists essentially of an input queueing management system comprising n input circuits CE1 to CEn, a time interval management unit UGIT, and a time base referred to as the system time base Bts. It also comprises a switching matrix MatCom.
Each input circuit CEi has an input Ei for receiving cells of the type used in a data transmission and/or ATM system, consisting of a header section in which information relating to the system is stored, in particular the number of the virtual circuit to which the cell belongs, and a section containing the messages to be transmitted. Cells such as these are described in the patent document EP-A-108 028.
Each input circuit CEi also has an output Si which is connected to one of n inputs in the switching matrix MatCom.
The matrix is the non-blocking type, more particularly a non-blocking space-division switching matrix such as the "BATCHER BANYAN" type, or more generally any non-blocking space-division switching matrix other than those based on simultaneous, single-output access conflicts. The switching matrix MatCom does not necessarily contain n outputs and, later in this description, consideration will be given to a matrix containing m outputs.
Each input circuit CEi also has m inputs Ea1 to Eam in a one-to-one relation with the m outputs of the switching matrix MatCom, and m outputs Sa1 to Sam corresponding to the m inputs. Each output Saj of an input circuit CEi is connected to the input Eaj of the next input circuit CEi+1 in the succession of input circuits CE1 to CEn.
The time interval processing unit UGIT for the one part comprises m outputs Sit1 to Sitm, connected respectively to m inputs Ea1 to Eam of the first input circuit CE1, and, for the other part, m inputs Eit1 to Eitm connected respectively to m outputs Sa1 to Sam of the last input circuit CEn.
The system time base Bts for the one part sends a clock signal Sh, the duration of which is k times less than that of a time slot T, and, for the other part, a synchronization signal CSY equal in duration to p times the duration of a time slot, for example eight times the duration of a time slot T. The clock signal Sh and the synchronization signal CSY are sent to the first input circuit CE1 and pass from one input circuit CEi to the next CEi+1. They are sent from the last input circuit CEn to the UGIT processing unit.
The function of the UGIT unit is explained below.
A description now follows of an input circuit CEi in conjunction with FIG. 2 which shows a schematic representation.
The input circuit CE shown comprises a register RegAdMtr, a translation memory Mtrad, a cell memory MC, a delay circuit RET, a time base BT, an assignment circuit CAF, and a toggle Basc.
The Mtrad memory is a random access memory in which storage pockets are assigned to the virtual circuits that the system can process. When the system is initialized, a translated label Et is stored in each of these pockets, corresponding to the virtual circuit assigned to the pocket, which can also include a self-addressing label supplement. Also stored in each of the pockets associated with a virtual circuit are "outgoing direction" bits Bd1 to Bdm equal in number m to the number of outputs in the switching matrix MatCom, which serve to specify, when positioned at one, the matrix output to which the cells carrying the number of the virtual circuit associated with the said pocket are addressed.
The bits Bd1 to Bdm together form an outgoing direction signal whose structure may differ in other methods of application of the invention, for example binary coding of m outgoing directions. The latter solution would make it possible to reduce the amount of translation memory required to translate information relating to the outgoing direction, but would require the use of a decoder which could, for example, be incorporated in the CAF assignment circuit.
Wires showing the number of the virtual circuit VCI to which the cell present at input E belongs are connected to the input of the register RegAdMtr, the output of which is connected to the read address input of the translation memory Mtrad. In read mode, this sends the translated label Et which is then passed to the input of the memory MC, in addition to bits Bd1 to Bdm which are sent to the corresponding inputs of the assignment circuit CAF.
Wires other than those showing the virtual circuit number are connected, via a delay circuit RET, to the input of the memory MC. The delay circuit RET is included to compensate for the time delays introduced by the memory Mtrad.
The memory MC has a number of pockets, each of which is intended to store all the bits of a particular cell.
The time base BT is controlled by the clock signal Sh received from the system time base Bts and is synchronized by the signal CSY sent by the preceding input circuit CE. Its function is to send a local time signal Hloc and a micro-interval local time signal Mtl. Whereas one time unit of the local time signal Hloc corresponds to a time slot To to Tn, the micro-interval time signal is subdivided into a time slot Ti, and into k time intervals taking the values Hloc+1 for the first, Hloc+2 for the second, and so on.
FIG. 3 shows three time slots T0, T1 and T2, each subdivided into micro-intervals t0 to t7. This identification of times is valid for the first input circuit CE1 and is offset by the duration of one micro-interval from one input circuit to the next, as shown by the thick stepped lines in FIG. 3.
It should be noted that k corresponds to the number of pulses of the clock signal Sh generated by the system time base Bts during one time slot T. As can be seen below, the number k corresponds to the depth of a virtual input queue.
The time base BT of an input circuit CEi is designed such that its local time signal Hloc is one micro-interval behind the time base BT of the preceding input circuit CEi-1. To do this, the time base BT of an input circuit CEi uses the synchronization signal CSY transmitted by the preceding input circuit CEi-1 and transmits to the next circuit CEi+1 a new synchronization signal CSY one micro-interval behind the old one.
In general, the value taken by the micro-interval time signal Mtl sent by the time base BT during the period ti of a time slot Tj is the value of the time cell Ti+j+1. Thus, during the time slot T0, the time interval signal takes the values T1 at time t0, T2 at time t1, etc. Similarly, during the time T1, it takes the values T2 at time t0, T3 at time t2, etc.
Each pocket of the memory MC is read addressed by the local time signal Hloc received from the time base BT and is write addressed by the output signal sent by a register REG, the input of which receives the micro-interval time signal Mtl transmitted by the time base BT. The register REG has a control input which is connected to an output S of the assignment circuit CAF.
The assignment circuit CAF has m inputs In1 to Inm which receive, via the registers Rin1 to Rinm (controlled respectively by the outgoing direction bits Bd1 to Bdm) the availability signals sd1 to Sdm sent by the preceding input circuit, or, if the input circuit in question is the first in succession, by the time interval processing unit UGIT. It also has m outputs Out1 to Outm, which send the updated availability signals sdr1 to sdrm to m inputs Ea1 to Eam of the next input circuit in succession or, if the input circuit in question is the last, to the corresponding inputs of the time interval processing unit UGIT. It has m inputs Ebd1 to Ebdm which receive respectively the m outgoing direction bits Bd1 to Bdm from the translation memory Mtrad. The output S of the circuit CAF is connected to the control input of the register REG. The circuit CAF has another input at which an assignment signal saf sent by the toggle Basc is present.
The toggle Basc has an input Es which is connected to the output S of the assignment circuit CAF and an output, for sending the assignment signal saf, connected to input E of the assignment circuit CAF. At its input Eh, it receives the signal Sh in such a way that it is synchronized with this signal and reset at the start of each time slot T. When a time slot, at time ti, is assigned to the cell present at input E of the input circuit CE, the signal saf output by the toggle Basc changes to one and this level is maintained until the end of the time slot.
An input circuit CE according to the invention operates as follows.
When a cell arrives at the input E, it is stored with its header (translated and sent by the memory Mtrad) in a pocket of the memory MC at an address determined as follows.
At the same time as it delivers the translated header Et, the memory Mtrad sends the outgoing direction bits Bd1 to Bdm, one of which is at one, thus indicating the matrix output where the incoming cell will be output.
During the time slot in question, inputs Ea1 to Eam are scrutinized by the assignment circuit CAF during each time interval t0 to tk of the current time slot.
Assuming that the cell currently being processed is addressed to the jth output of the switching matrix MatCom, the outgoing direction bit Bdj of row j will be at one.
If, during the time interval ti, the jth input Eaj is at one, this means that the time slot Ta+i+1 is occupied at the jth output, a being the row of the time slot currently being processed.
However, if the jth input Eaj is at zero in the time interval ti, this means that the time slot Ta+i+1 is free at the jth output of the switching matrix MatCom. At time ti, the assignment circuit CAF therefore sends from its output S a signal controlling the register REG. The latter then sends to the write input of the memory MC the time interval signal Mtl received from the time base which is, as was shown earlier, equal to Ta+i+1. The cell is therefore stored at the address of the memory MC corresponding to Ta+i+1. The assignment circuit CAF also sends, from its output Outj in row j, the signal sdrj which is now at one, thus indicating occupation of the time slot Ta+i+1.
When the assignment circuit CAF controls the register REG, the input Es of the toggle Basc is at one. The output signal saf therefore also changes to one and remains so until the end of the current time slot. The assignment circuit CAF therefore no longer assigns a time slot to the current cell.
During the time slot in question Ta, the memory MC receives from the time base BT a read address signal Hloc equal in value to Ta. The cell stored at this address in the memory MC is therefore sent to the corresponding input of the switching matrix MatCom which can then process it.
The availability signals sd are transmitted, with a delay equal in duration to that of one micro-interval, from one input circuit to the next and from the last input circuit to the time interval management unit UGIT. The delay of one micro-interval is carried out by the registers Rin1 to Rinm of each input circuit. This delay implies that local times sent by the time bases BT of the input circuits are, as discussed earlier, offset by the duration of one micro-interval.
FIG. 3 shows, by means of the arrows A, the exchange between the input circuits CE1 to CE6 of the words constituted by the concatenation of availability signals sd1 to sdm during the first micro-interval t0 and, by means of the arrows B, the exchange between the input circuits CE1 to CE6 of the words constituted by the concatenation of availability signals sd1 to sdm during the second micro-interval t1.
At the first micro interval t0 of a time slot T, the time interval management unit UGIT is designed to send the availability signals sd1 to sdm present at its inputs Eit1 to Eitm during the last micro-interval of the preceding time slot, to the corresponding outputs Sit1 to Sitm. This function of the UGIT unit is represented in FIG. 3 by the arrows C.
It will be noted in FIG. 3 that the number of micro-intervals exceeds the number of input circuits by one. This makes it possible to create an offset of one micro-interval, such that the word present during the first time interval of the next time slot always indicates a free condition.
FIG. 4 shows a logic diagram of an assignment circuit CAF. It comprises m AND gates AND1 to ANDm with three inputs. The first input of gate ANDj in row j is connected to the input Ebdj receiving the outgoing direction bit Bdj of row j, a second input receiving the availability bit sdj of row j, and a third inverter input connected to input E which is normally connected to the output of the toggle Basc. The outputs of gates AND1 and ANDm are connected respectively to the inputs of an OR gate ORg, the output of which constitutes the output S of the assignment circuit CAF.
The output of the gate ANDj of row j is also connected to the first input of an OR gate ORj, the second input of which receives the availability signal Sdj of row j. The outputs of gates OR1 to ORm are connected respectively to the outputs Out1 to Outm.
Let us assume that no time slot has yet been assigned to the incoming cell, such that the input E is at zero.
Let us assume that the cell currently being processed is addressed to the jth output of the switching matrix MatCom. The outgoing direction bit Bdj of row j at the input Ebdj is therefore at one, whereas the the other bits are at zero.
If the jth availability signal sdj is at one, the gate ANDj of row j sends a one, whereas the other gates send a zero.
The gate ORg then sends a one, which has the effect of controlling the register REG and changing the signal saf to one at the output of the toggle Basc, and therefore at the input E, until the end of the time slot. As a result, throughout this period, the outputs of all of the gates AND1 to ANDm are at zero.
It can be seen that the toggle Basc therefore prevents a single cell from being assigned to several different time slots, and, as a consequence, from being stored in several different addresses in the memory MC.
If, contrary to the above, the jth availability signal sdj is at zero, the gate ANDj of row j sends a zero and, as all the other gates AND1 to ANDm also send a zero, the gate ORg sends a zero. The cell is therefore not stored at the address corresponding to the micro-interval during which the above process takes place.
It will be noted that in order to limit the number of pockets required by the memory MC, an indirect address memory may be used to save the storage address in the memory MC of the incoming cell, which address is determined by an available address determination device. Details of a memory MC, indirect available address memory, and available address determination device such as this are described fully in the patent FR-A-2 617 302 and are in all respects equivalent in operation, within the framework of the present invention, to the memory MC described herein.
It will be noted that the assignment circuit may be comprised of several elementary circuits such as that shown in FIG. 4, including the registers Rin1 to Rinm. The figure shows an assignment circuit such as this containing K elementary assignment circuits CAF1 to CAFK and their interconnection to an input circuit CE.
The inputs E1 to EK of all the assignment circuits CAF1 to CAFK are connected in parallel to receive the assignment signal saf from the toggle Basc of the input circuit CE in question. An OR gate ORG has K inputs connected respectively to the outputs S of the basic assignment circuits, and an output connected to the control input of the register REG of the input circuit in question.
The availability signals sd1 to sdM, where M=K×m, are distributed over each of the basic circuits CAF1 to CAFK, and the latter send the updated availability signals sdr1 to sdrM, in number K×m.
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|Citing Patent||Filing date||Publication date||Applicant||Title|
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|U.S. Classification||370/415, 370/395.4|
|International Classification||H04Q3/00, H04Q3/52, H04L12/56|
|Cooperative Classification||H04L2012/5681, H04L12/5601, H04L49/106, H04L2012/5678, H04L49/1561, H04L49/1576|
|European Classification||H04L49/15E5, H04L49/10F1A, H04L49/15E1, H04L12/56A|
|Dec 21, 1994||AS||Assignment|
Owner name: FRANCE TELECOM, FRANCE
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BOYER, PIERRE;COUDREUSE, JEAN-PIERRE;SERVEL, MICHEL;REEL/FRAME:007330/0550
Effective date: 19941006
|Oct 28, 1999||FPAY||Fee payment|
Year of fee payment: 4
|Oct 27, 2003||FPAY||Fee payment|
Year of fee payment: 8
|Sep 25, 2007||FPAY||Fee payment|
Year of fee payment: 12
|May 28, 2008||AS||Assignment|
Owner name: FRANCE TELECOM, FRANCE
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BOYER, PIERRE;COUDREUSE, JEAN-PIERRE;SERVEL, MICHEL;REEL/FRAME:021010/0443
Effective date: 19941006
|Mar 6, 2009||AS||Assignment|
Owner name: GULA CONSULTING LIMITED LIABILITY COMPANY, DELAWAR
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FRANCE TELECOM SA;REEL/FRAME:022354/0124
Effective date: 20081202