Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS5528188 A
Publication typeGrant
Application numberUS 08/402,793
Publication dateJun 18, 1996
Filing dateMar 13, 1995
Priority dateMar 13, 1995
Fee statusLapsed
Publication number08402793, 402793, US 5528188 A, US 5528188A, US-A-5528188, US5528188 A, US5528188A
InventorsWai-Ming W. Au, Minh H. Tong
Original AssigneeInternational Business Machines Corporation
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Electrostatic discharge suppression circuit employing low-voltage triggering silicon-controlled rectifier
US 5528188 A
Abstract
A resistance capacitance (RC) coupled low-voltage triggering silicon-controlled rectifier (LVTSCR) suppression circuit is presented for protecting an integrated circuit from electrostatic discharges or other potentially damaging voltage transients occurring at an input and/or output node of the integrated circuit or integrated circuit chip. The suppression circuit includes a discharge circuit and a trigger circuit. The discharge circuit is electrically coupled to the input and/or output node for dissipating the electrostatic discharge, while the trigger circuit is electrically connected to the input and/or output node and to the discharge circuit. The trigger circuit provides direct low-voltage turn-on of the discharge circuit as the electrostatic discharge builds at the input and/or output node of the integrated circuit. The trigger circuit includes a transistor having a control gate, and an RC circuit connected to the control gate and to the input and/or output node such that the control gate is electrically coupled to the input and/or output node across a capacitance and to ground across a resistance.
Images(4)
Previous page
Next page
Claims(6)
We claim:
1. A suppression circuit for dissipating an electrostatic discharge at an input and/or output node of an integrated circuit, said suppression circuit comprising:
a silicon-controlled rectifier discharge circuit electrically coupled to the input and/or output node for dissipating the electrostatic discharge; and
a trigger circuit electrically connected to the input and/or output node and to the discharge circuit, said trigger circuit providing low-voltage turn-on of said discharge circuit as the electrostatic discharge builds at the input and/or output node of the integrated circuit to thereby prevent damage to the integrated circuit due to said electrostatic discharge, said trigger circuit including a transistor having a control gate, the transistor further having a substrate coupled to a control electrode of the silicon-controlled rectifier discharge circuit, the trigger circuit further including a passive resistance capacitance (RC) circuit connected to the control gate and to the input and/or output node such that said control gate is electrically coupled to the input and/or output node across a capacitance and to ground across a resistance, the passive RC circuit inhibiting turn-on of the discharge circuit during normal integrated circuit operation.
2. The suppression circuit of claim 1, wherein said transistor comprises a field-effect transistor, said field-effect transistor being connected to turn on with occurrence of said electrostatic discharge at the input and/or output node of the integrated circuit, turn-on of said field-effect transistor providing turn-on of said silicon-controlled rectifier discharge circuit.
3. The suppression circuit of claim 1, wherein said integrated circuit comprises an integrated circuit chip.
4. A suppression circuit for dissipating an electrostatic discharge at an input and/or output node of an integrated circuit, said suppression circuit comprising:
a discharge circuit electrically coupled to the input and/or output node for dissipating the electrostatic discharge, said discharge circuit including a first silicon-controlled rectifier and a second silicon-controlled rectifier, said first silicon-controlled rectifier being electrically coupled between the input and/or output node and a (Vdd) voltage supply node of the integrated circuit, and said second silicon-controlled rectifier being electrically coupled between the input and/or output node and a (Vss) voltage supply node of the integrated circuit; and
a trigger circuit electrically connected to the input and/or output node and to the first silicon-controlled rectifier and the second silicon-controlled rectifier of the discharge circuit, said trigger circuit providing low-voltage turn-on of one of said first silicon-controlled rectifier and said second silicon-controlled rectifier in response to the electrostatic discharge occurring at the input and/or output node of the integrated circuit to thereby dissipate the electrostatic discharge and prevent damage to the integrated circuit, said trigger circuit including a first transistor and a second transistor, a substrate of said first transistor being coupled to a control electrode of the first silicon-controlled rectifier and a substrate of said second transistor being coupled to a control electrode of the second silicon-controlled rectifier, a control gate of said first transistor and a control gate of said second transistor each being electrically coupled to the input and/or output node across a capacitance and to ground across a resistance, the capacitance and resistance forming a passive circuit, whereby depending upon the polarity of said electrostatic discharge, either said first transistor or said second transistor turns-on with said electrostatic discharge to turn on the first silicon-controlled rectifier or the second silicon-controlled rectifier, respectively, the passive circuit inhibiting turn-on of the first and second transistors during normal integrated circuit operation.
5. The suppression circuit of claim 4, wherein said integrated circuit comprises an integrated circuit chip having multiple input and/or output nodes, and wherein said suppression circuit is electrically coupled to at least one of said multiple input and/or output nodes for suppression of an electrostatic discharge occurring thereat.
6. An integrated circuit chip comprising:
an integrated circuit;
multiple input and/or output pads coupled to the integrated circuit for external connection thereto; and
multiple electrostatic discharge suppression circuits electrically coupled to said multiple input and/or output pads, each electrostatic discharge suppression circuit including
a silicon-controlled rectifier discharge circuit for dissipating an electrostatic discharge at a respective input and/or output pad of said multiple input and/or output pads, and
a trigger circuit electrically connected to said respective input and/or output pad and to said respective discharge circuit, said trigger circuit providing low-voltage turn-on of said respective discharge circuit with the electrostatic respective discharge at said input and/or output pad to thereby dissipate the electrostatic discharge and prevent damage to the integrated circuit, said trigger circuit including a transistor having a control gate, the transistor further having a substrate coupled to a control electrode of the silicon-controlled rectifier discharge circuit, the trigger circuit further including a passive resistance capacitance (RC) circuit connected to the control gate and to said respective input and/or output pad such that said control gate is electrically coupled to the respective input and/or output pad across a capacitance and to ground across a resistance, the passive RC circuit inhibiting turn-on of the respective discharge circuit during normal integrated circuit operation.
Description
TECHNICAL FIELD

This invention relates in general to protection of integrated circuits, and more particularly, to a resistance capacitance (RC) coupled low-voltage triggering silicon-controlled rectifier (LVTSCR) suppression circuit for protecting an integrated circuit from electrostatic discharges or other potentially damaging voltage transients occurring at an input and/or output node of the integrated circuit.

Background Art

Electrostatic discharge (ESD) is a phenomenon known to degrade or destroy electronic components. In particular, given the decreasing size of circuit features with ever improving process technology, static electricity can destroy or substantially harm many of today's integrated circuits. Electrostatic discharge can occur, for example, from human handling, automated circuit testing or as a packaged circuit slides on its pins across another surface. The circuits most susceptible to damage are unpackaged or packaged finished circuits which have not yet been installed into a finished product. Once installed, for example, onto a circuit card, other means exist to protect the circuits from damage.

Various techniques have been employed to protect integrated circuit chips handled by humans during the fabrication process. These methods include special handling procedures, use of grounding equipment, and the addition of protective components to the chip circuitry. Complementary metal-oxide semiconductor (CMOS) circuits are particularly subject to negative consequences of electrostatic discharges. In high density CMOS devices, an electrostatic discharge may develop an extremely high voltage which easily destroys the very thin gate oxides and very short channel devices of these circuits.

To protect CMOS devices against high voltages, a silicon-controlled rectifier (SCR) structure may be employed which is compatible with CMOS processing. FIG. 1 depicts one embodiment of a conventional SCR structure, denoted 10, compatible with CMOS processing. SCR 10 has a PNP bipolar transistor and an NPN bipolar transistor interconnected so that the emitter-collector circuit of each transistor conducts the base current for the other. When either transistor is turned on, it turns on the other and both stay on until the current is interrupted. Silicon-controlled rectifiers, such as SCR 10, have several advantages as ESD suppression circuits: they can handle high current; they have a low turn-on impedance; they dissipate low power; and they have a large volume for heat dissipation. Unfortunately, SCRs usually have a high turn-on voltage, which may be in a range that the suppression circuits should protect against. For example, the SCR structure of FIG. 1 turns on by development of a breakdown voltage across the N-well to substrate (P-) junction, which typically requires 15-50 volts. Such a voltage level is high for today's integrated circuits.

Due to this high SCR trigger voltage, a secondary ESD protection device is often employed in parallel when an SCR performs the primary ESD suppression function. For example, FIG. 2 depicts a secondary ESD protect device 12, comprising a resistor 14 and a series connected turn-on device 16, which is connected in parallel with an SCR 18 between an input and/or output pad 20 of an integrated circuit (not shown) and ground. In this configuration, turn-on device 16 could comprise a field-effect transistor (FET) or a reverse-biased diode. The overall suppression mechanism during occurrence of an ESD transient at the input and/or output pad (or node) is that secondary protect device 12 turns on first, and after the ESD current has increased to a certain level, the overall voltage drop across secondary ESD protect device 12 will trigger SCR 18. If turn-on device 16 comprises an FET, the triggering mechanism is a breakdown of the FET, which typically occurs at approximately seven volts for today's field-effect transistors. Thus, the turn-on voltage for SCR 18 is still somewhat high, i.e., greater than seven volts. Further, the addition of resistor 14 directly electrically connected to, for example, an output pad can degrade driver circuit performance, which is typically unacceptable in today's high speed circuit designs.

Recently, a low-voltage triggering silicon-controlled rectifier (LVTSCR) has been proposed, see for example Chatterjee et al., "A Low-Voltage Triggering SCR For On Chip ESD Protection At Output and Input Pads," IEEE EDL-12, No. 1, Jan. 1991. One embodiment of such an LVTSCR structure is depicted in FIG. 3. As shown, an N-channel field-effect transistor (NFET) is formed integral with (i.e., shares at least one semiconductor region with) the SCR. The control gate "G" and source "S" of the NFET are commonly connected to ground. In this implementation, the "snapback" mode of the FET is relied on for turn-on of the discharge circuit, i.e., the SCR. As is well known, the "snapback" phenomenon occurs by a triggering of the parasitic bipolar device of the FET.

More particularly, a voltage on pad 28 is directly coupled to the common N+ diffusion of the combined FET/SCR semiconductor device, i.e., the drain "D" of the FET in this embodiment. When sufficient voltage develops at the drain, the FET is triggered on, via the snapback phenomenon, notwithstanding that the transistor has a grounded control gate "G". In snapback mode, current flows through the FET, which will trigger the SCR. The SCR is triggered by the generated hole carriers originating from the grounded-gate breakdown of the FET. Since the grounded-gate breakdown voltage is relatively low, i.e., approximately seven volts, the SCR is triggered at a lower ESD voltage and thus the structure is referred to as a low-voltage triggering SCR. Unfortunately, for today's CMOS circuitry seven volts can be sufficient to breakdown gate oxide of the active devices. Thus, a need exists in the ESD suppression art for an even lower voltage triggered SCR.

Disclosure of Invention

Briefly summarized, the present invention comprises a suppression circuit for dissipating an electrostatic discharge occurring at an input and/or output node of an integrated circuit. The ESD suppression circuit includes a discharge circuit and a trigger circuit. The discharge circuit is electrically coupled to the input and/or output node for dissipating the electrostatic discharge, while the trigger circuit is electrically connected to both the input and/or output node and to the discharge circuit. The trigger circuit provides direct low-voltage turn-on of the discharge circuit as the electrostatic discharge builds at the input and/or output node of the integrated circuit, thereby preventing damage to the integrated circuit. The trigger circuit includes a transistor having a control gate, and a resistance capacitance (RC) circuit connected to the control gate and to the input and/or output node such that the control gate is electrically coupled to the input and/or output node across a capacitance and to ground across a resistance.

In another aspect, a suppression circuit in accordance with the present invention again includes a discharge circuit and a trigger circuit. In this implementation, the discharge circuit is electrically coupled to the input and/or output node for dissipating the electrostatic discharge. The discharge circuit includes a first silicon-controlled rectifier electrically coupled between the input and/or output node and Vdd, and a second silicon-controlled rectifier electrically coupled between the input and/or output node and ground of the integrated circuit. The trigger circuit is electrically coupled to the input and/or output node and to the first silicon-controlled rectifier and the second silicon-controlled rectifier. The trigger circuit provides direct low-voltage turn-on of either the first silicon-controlled rectifier or the second silicon-controlled rectifier with occurrence of an electrostatic discharge at the input and/or output node of the integrated circuit to thereby dissipate the electrostatic discharge and prevent damage to the integrated circuit. The trigger circuit includes a first transistor and a second transistor. The first transistor is formed integral with the first silicon-controlled rectifier and the second transistor is formed integral with the second silicon-controlled rectifier. The control gates of the first transistor and the second transistor are each electrically coupled to the input and/or output node across a capacitance and to ground across a resistance. Depending upon the polarity of an electrostatic discharge, either the first transistor or the second transistor turns-on with the electrostatic discharge to turn-on the first silicon-controlled rectifier or the second silicon-controlled rectifier, respectively.

In still another aspect, the invention comprises an integrated circuit chip. The integrated circuit chip includes an integrated circuit and multiple input and/or output pads coupled to the integrated circuit for external connection thereto. In this aspect, multiple electrostatic discharge suppression circuits are electrically coupled to the multiple input and/or output pads. Each electrostatic discharge suppression circuit includes a discharge circuit and a trigger circuit. The trigger circuit dissipates an electrostatic discharge at an input and/or output pad of the multiple input and/or output pads. The trigger circuit is electrically connected to the input and/or output pad and to the discharge circuit. This trigger circuit provides direct low-voltage turn-on of the discharge circuit with the electrostatic discharge at the input and/or output pad to thereby prevent damage to the integrated circuit. The trigger circuit includes a transistor having a control gate and a resistance capacitance circuit connected to the control gate and to the input and/or output pad such that the control gate is electrically coupled to the input and/or output pad across a capacitance and to ground across a resistance.

There are numerous advantages and features of a structure in accordance with the present invention. The novel suppression circuit of the present invention employs a low-voltage triggering silicon-controlled rectifier (LVTSCR). This suppression circuit provides protection against electrostatic discharges or potentially damaging voltage transients occurring at an input, an output or a power supply pad of an integrated circuit or integrated circuit chip. With the novel trigger circuit presented, ESD protection of active integrated circuits is ensured at lower voltages than otherwise attainable with prior approaches, and thus the level of ESD protection is higher. Further, there is no performance degradation resulting from addition of the trigger circuit. Due to the fast response of the RC-coupled LVTSCR to the ESD voltage rise time, the suppression circuit is extremely useful for protection against either machine or human induced ESD events. The triggering voltage is based on the low threshold voltage (VT) of the FET device, and not on a grounded-gate breakdown voltage. This suppression circuit can readily provide ESD protection to different power supply levels, including voltage levels Vdd and Vss (ground).

BRIEF DESCRIPTION OF DRAWINGS

These and other objects, advantages and features of the present invention will be more readily understood from the following detailed description of certain preferred embodiments of the invention, when considered in conjunction with the accompanying drawings in which:

FIG. 1 is a partial cross-sectional view of a conventional silicon-controlled rectifier (SCR) semiconductor device;

FIG. 2 is a simplified schematic of a conventional suppression circuit employing a silicon-controlled rectifier in parallel with a secondary protection circuit;

FIG. 3 is a partial cross-sectional view of another conventional suppression circuit comprising a low-voltage triggering silicon-controlled rectifier (LVTSCR);

FIG. 4a is a partial cross-sectional, partial schematic view of a suppression circuit in accordance with the present invention;

FIG. 4b is a schematic of the suppression circuit of FIG. 4a;

FIG. 5 depicts a characteristic graph for a prior art grounded-gate N-channel field-effect transistor (NFET) and a characteristic graph for an RC-coupled gate NFET for a suppression circuit in accordance with the present invention; and

FIG. 6 is a schematic of an alternate embodiment of a suppression circuit in accordance with the present invention employing multiple SCRs and multiple RC-coupled gate FETs.

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 4a depicts a suppression circuit, generally denoted 30, in accordance with the present invention. Structurally circuit 30 includes an integrated SCR and FET device similar to that discussed above in connection with FIG. 3, and a resistance capacitance (RC) circuit 32 coupled to the gate "G" of the FET device. RC circuit 32 is also electrically connected to one of the multiple input pads, output pads, or input/output pads (herein collectively referred to as input and/or output pads) of an integrated circuit or integrated circuit chip with which the suppression circuit is associated. These pads may comprise signal pads, control pads, power pads, etc. As shown, RC circuit 32 includes a capacitance "C" that couples the gate "G" of the FET to at least one input and/or output pad (or node) 34, and a resistance "R" electrically connected between the gate "G" of the FET and ground (Vss). Multiple pads 34-34n may each have connected thereto a respective discharge circuit (40-40n) and an RC circuit (32-32n).

The electrical connections are depicted in greater detail in FIG. 4b, wherein circuitry 40 comprises the SCR, and transistor Q1 comprises the NFET transistor depicted in FIG. 4a. Within the SCR, transistor T1 is an NPN bipolar transistor of which the collector "c" comprises the N-well of FIG. 4a, the base "b" comprises the P- substrate, and the emitter "e" comprises the grounded N+ diffusion. Transistor T2 is a PNP bipolar device having an emitter "e" comprising the P+ diffusion within the N-well of FIG. 4a, a base "b" comprising the N-well region and a collector "c" comprising the P- substrate region. Fabrication of the underlining LVTSCR structure depicted in FIG. 4a will be understood by one skilled in the art.

A significant difference between the prior art LVTSCR structure of FIG. 3 and that of the present invention depicted in FIG. 4a comprises the mode of operation of such suppression circuits. FIG. 5 depicts current-voltage characteristics for the grounded gate FET of FIG. 3 and the RC-coupled gate FET of FIG. 4a in accordance with the present invention. In particular, the solid line depicts operation of the grounded gate FET of FIG. 3, while the phantom line depicts operation of the RC-coupled gate FET of FIG. 4a. As noted above in connection with FIG. 3, the snapback phenonemon triggers that FET into a conducting state notwithstanding that its control gate "G" is grounded. Briefly explained, a voltage transient on pad 28 (FIG. 3) directly effects the voltage on the drain "D" diffusion of the FET. Thus, a high voltage on the pad will generate hole current (due to impact ionization) to flow through the substrate beneath the FET gate. This hole current in turn causes a potential greater than 0.7 volts beneath the gate which forward biases the grounded source "S" junction. Forward biasing of this junction injects electrons which are then collected by the N-well and when these electrons are sufficiently large, a negative potential is created at the P+ diffusion within the N-well. This potential forward biases the P+ N-well junction, thereby injecting additional holes into the N-well and hence the P- substrate. These additional holes ultimately force the PNPN SCR to trigger on.

By comparison, the RC-coupled LVTSCR in accordance with the present invention of FIG. 4b relies on direct turn-on of the FET through capacitive coupling of a transient voltage on pad 34 to the gate "G" of the FET. Upon turn-on of the FET, electron current flows within a current (I) channel beneath gate "G" between the drain "D" and source "S" diffusions. Impact ionization results in the generation of holes within the I channel and as shown by the characteristic in FIG. 5, the FET directly and smoothly transitions into a sustaining mode 44, with no snapback 42.

With a properly designed RC circuit 32, the FET device is "off" under normal operating conditions of the active integrated circuitry (not shown) connected to pad 34. However, during an ESD transient, the FET of the suppression circuit is turned "on" once the voltage at the FET gate exceeds the threshold voltage (VT), e.g., 0.5 V. This threshold is quickly reached due to the fast dV/dt of the ESD pulse on pad 34 which is coupled to the gate across the capacitor "C". Thus, a significant attribute of this gate-coupled FET is its fast turn-on characteristic whenever an ESD event occurs at the input and/or output pad of the integrated circuit.

Once the FET is turned on, hole generation is initiated due to impact ionization of the channel current (I-channel) at the drain "D" region of the NFET. The hole carrier generation forms the base current for the SCR. So a significant feature of this invention is that the SCR is easily triggered by the low threshold voltage (VT) of the NFET, not by the relatively high grounded-gate breakdown voltage as in the LVTSCR structure of FIG. 3. Further, it should be re-emphasized that the gate-coupled FET presented herein is not used in an ESD protect device as presented in FIG. 2, but rather, solely as a triggering device for the SCR. The SCR itself is the ESD discharge device that absorbs the ESD energy. Also, note that because this structure is operated based on the high dV/dt of an ESD voltage rise time, the structure will perform significantly better than other ESD structures, particularly for machine-induced ESD events.

FIG. 6 schematically depicts another ESD suppression circuit in accordance with the present invention which protects an integrated circuit connected to an input/output pad 48 by providing a shunt path to ground through SCR 52 or a shunt path to supply voltage Vdd via SCR 50. The triggering mechanism for SCR 50 comprises an FET Q2 which has its gate connected to an RC-coupled circuit 54 in accordance with the present invention. Similarly, SCR 52 is triggered by transistor Q3 that is also gated by RC circuit 54. Operationally, the structure of FIG. 6 is analogous to that discussed above in connection with FIG. 4a & 4b, except provision is made for suppression of either a positive or a negative polarity ESD event.

The novel suppression circuit of the present invention employs a low-voltage triggering silicon-controlled rectifier. This suppression circuit provides protection against electrostatic discharges or potentially damaging voltage transients occurring at an input, an output or a power supply pad of an integrated circuit or integrated circuit chip. With the novel trigger circuit presented, ESD protection of active integrated circuits is ensured at lower voltages than otherwise attainable with prior approaches, and thus the level of ESD protection is higher. Further, there is no performance degradation resulting from addition of the trigger circuit. Due to the fast response of the RC-coupled LVTSCR to the ESD voltage rise time, the suppression circuit is extremely useful for protection against machine or human induced ESD events. The triggering voltage is based on the low threshold voltage (VT) of the FET device, and not on a grounded-gate breakdown voltage. This suppression circuit can readily provide ESD protection pads to different power supply levels, such as Vdd and Vss (ground).

While the invention has been described in detail herein in accordance with certain preferred embodiments thereof, many modifications and changes therein may be effected by those skilled in the art. Accordingly, it is intended by the appended claims to cover all such modifications and changes as fall within the true spirit and scope of the invention.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US3603843 *Jun 17, 1970Sep 7, 1971Barber Colman CoTransient voltage protection circuit for gate turn on devices
US4400711 *Mar 31, 1981Aug 23, 1983Rca CorporationIntegrated circuit protection device
US4870530 *Jun 27, 1988Sep 26, 1989Advanced Micro Devices, Inc.Electrostatic discharge protection circuitry for any two external pins of an I.C. package
US4939616 *Nov 13, 1989Jul 3, 1990Texas Instruments IncorporatedCircuit structure with enhanced electrostatic discharge protection
US4956570 *Dec 21, 1988Sep 11, 1990Sgs-Thomson Microelectronics S.R.L.Pilot circuit with integrated circuit with preset firing delay for MOS power transistors
US5140401 *Mar 25, 1991Aug 18, 1992United Microelectronics CorporationCMOS ESD protection circuit with parasitic SCR structures
US5182220 *Apr 2, 1992Jan 26, 1993United Microelectronics CorporationCMOS on-chip ESD protection circuit and semiconductor structure
US5225702 *Dec 5, 1991Jul 6, 1993Texas Instruments IncorporatedSilicon controlled rectifier structure for electrostatic discharge protection
US5289334 *Nov 18, 1992Feb 22, 1994United Microelectronics CorporationCMOS on-chip ESD protection circuit and semiconductor structure
US5290724 *Sep 21, 1992Mar 1, 1994Texas Instruments IncorporatedMethod of forming an electrostatic discharge protection circuit
US5345357 *Jun 5, 1992Sep 6, 1994At&T Bell LaboratoriesESD protection of output buffers
US5359211 *Jul 18, 1991Oct 25, 1994Harris CorporationHigh voltage protection using SCRs
US5400202 *Jun 15, 1992Mar 21, 1995Hewlett-Packard CompanyElectrostatic discharge protection circuit for integrated circuits
US5430595 *Oct 15, 1993Jul 4, 1995Intel CorporationElectrostatic discharge protection circuit
Non-Patent Citations
Reference
1Chattrjee et al., "A Low-Voltage Trigger SCR For On-Chip ESD Protection At Output and Input Pads", IEE Electron Device Letters, vol. 12, No. 1, pp. 6-7, Jan. 1991.
2 *Chattrjee et al., A Low Voltage Trigger SCR For On Chip ESD Protection At Output and Input Pads , IEE Electron Device Letters, vol. 12, No. 1, pp. 6 7, Jan. 1991.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US5631793 *Sep 5, 1995May 20, 1997Winbond Electronics CorporationCapacitor-couple electrostatic discharge protection circuit
US5671111 *Oct 30, 1995Sep 23, 1997Motorola, Inc.Apparatus for electro-static discharge protection in a semiconductor device
US5781388 *Sep 3, 1996Jul 14, 1998Motorola, Inc.Non-breakdown triggered electrostatic discharge protection circuit for an integrated circuit and method therefor
US5825603 *Sep 2, 1997Oct 20, 1998Intel CorporaitonFor preventing damage to a circuit of an integrated circuit
US5835328 *Aug 18, 1997Nov 10, 1998Intel CorporationBreakdown-tiggered transient discharge circuit
US5862031 *Nov 26, 1997Jan 19, 1999Analog Devices, Inc.ESD protection circuit for integrated circuits having a bipolar differential input
US5877927 *Oct 1, 1996Mar 2, 1999Intel CorporationMethod and apparatus for providing electrostatic discharge protection for high voltage inputs
US5907462 *Sep 7, 1994May 25, 1999Texas Instruments IncorporatedOf an integrated circuit
US5940258 *Feb 5, 1997Aug 17, 1999Texas Instruments IncorporatedSemiconductor ESD protection circuit
US5959488 *Jan 24, 1998Sep 28, 1999Winbond Electronics Corp.Dual-node capacitor coupled MOSFET for improving ESD performance
US5959820 *Apr 23, 1998Sep 28, 1999Taiwan Semiconductor Manufacturing Co., Ltd.Cascode LVTSCR and ESD protection circuit
US5959821 *Jul 2, 1998Sep 28, 1999Xilinx, Inc.Triple-well silicon controlled rectifier with dynamic holding voltage
US5982217 *Feb 19, 1998Nov 9, 1999Texas Instruments IncorporatedPNP driven NMOS ESD protection circuit
US5982601 *Jul 30, 1998Nov 9, 1999Winbond Electronics Corp.Direct transient-triggered SCR for ESD protection
US6002567 *Oct 17, 1997Dec 14, 1999Lsi Logic CorporationESD protection for high voltage level input for analog application
US6055143 *May 5, 1998Apr 25, 2000Winbond Electronics CorporationElectrostatic discharge protection circuit triggered by EPROM
US6097114 *Aug 17, 1998Aug 1, 2000Nikon CorporationCompact planar motor having multiple degrees of freedom
US6125021 *Apr 30, 1997Sep 26, 2000Texas Instruments IncorporatedSemiconductor ESD protection circuit
US6147538 *Jun 3, 1999Nov 14, 2000Texas Instruments IncorporatedCMOS triggered NMOS ESD protection circuit
US6172861 *Nov 23, 1999Jan 9, 2001Citizen Watch Co., Ltd.Protection circuit for semiconductor device
US6177298Feb 2, 1998Jan 23, 2001Motorola, Inc.Electrostatic discharge protection circuit for an integrated circuit and method of manufacturing
US6249413 *May 20, 1999Jun 19, 2001Texas Instruments IncorporatedSemiconductor ESD protection circuit
US6249414Sep 28, 2000Jun 19, 2001Taiwan Semiconductor Manufacturing CompanyDisplacement current trigger SCR
US6256184Jun 16, 1999Jul 3, 2001International Business Machines CorporationMethod and apparatus for providing electrostatic discharge protection
US6268992Apr 15, 1999Jul 31, 2001Taiwan Semiconductor Manufacturing CompanyDisplacement current trigger SCR
US6310379Jun 3, 1999Oct 30, 2001Texas Instruments IncorporatedNMOS triggered NMOS ESD protection circuit using low voltage NMOS transistors
US6369994 *Jul 31, 1998Apr 9, 2002International Business Machines CorporationMethod and apparatus for handling an ESD event on an SOI integrated circuit
US6411480Mar 1, 1999Jun 25, 2002International Business Machines CorporationSubstrate pumped ESD network with trench structure
US6479872 *Dec 28, 1998Nov 12, 2002Taiwan Semiconductor Manufacturing CompanyDynamic substrate-coupled electrostatic discharging protection circuit
US6483337 *Jul 26, 2000Nov 19, 2002Advanced Micro Devices Inc.Method for achieving synchronous non-destructive latchup characterization
US6501632 *Aug 4, 2000Dec 31, 2002Sarnoff CorporationApparatus for providing high performance electrostatic discharge protection
US6512663 *May 23, 2000Jan 28, 2003Nec CorporationElectrostatic protection device and electrostatic protection circuit
US6590261 *Oct 10, 2001Jul 8, 2003Macronix International Co., Ltd.Electrostatic discharge protection structure
US6611028Oct 8, 2002Aug 26, 2003Taiwan Semiconductor Manufacturing CompanyDynamic substrate-coupled electrostatic discharging protection circuit
US6621673 *Jul 13, 2001Sep 16, 2003Vanguard International Semiconductor CorporationTwo-stage ESD protection circuit with a secondary ESD protection circuit having a quicker trigger-on rate
US6646840Aug 3, 2000Nov 11, 2003Fairchild Semiconductor CorporationInternally triggered electrostatic device clamp with stand-off voltage
US6650165 *May 2, 2002Nov 18, 2003Micrel, IncorporatedLocalized electrostatic discharge protection for integrated circuit input/output pads
US6671153Sep 11, 2000Dec 30, 2003Taiwan Semiconductor Manufacturing CompanyLow-leakage diode string for use in the power-rail ESD clamp circuits
US6714061 *Jul 17, 2002Mar 30, 2004Intel CorporationSemiconductor controlled rectifier / semiconductor controlled switch based ESD power supply clamp with active bias timer circuitry
US6861711Sep 19, 2003Mar 1, 2005Micrel, IncorporatedThick gate oxide transistor and electrostatic discharge protection utilizing thick gate oxide transistors
US6864537Jan 3, 2003Mar 8, 2005Micrel, IncorporatedThick gate oxide transistor and electrostatic discharge protection utilizing thick gate oxide transistors
US6888710Jan 3, 2003May 3, 2005Micrel, IncorporatedInsulated gate bipolar transistor and electrostatic discharge cell protection utilizing insulated gate bipolar transistors
US6894320 *Sep 16, 2002May 17, 2005Yamaha CorporationInput protection circuit
US6968157Aug 21, 2002Nov 22, 2005University Of MarylandSystem and method for protecting devices from interference signals
US6970335 *Jul 23, 2003Nov 29, 2005National Semiconductor CorporationLVTSCR ESD protection clamp with dynamically controlled blocking junction
US7005686Jul 26, 2005Feb 28, 2006International Business Machines CorporationMixed voltage tolerant electrostatic discharge protection silicon controlled rectifier with enhanced turn-on time
US7064393Feb 20, 2004Jun 20, 2006Sarnoff CorporationElectrostatic discharge protection structures having high holding current for latch-up immunity
US7075763 *Oct 31, 2002Jul 11, 2006Micron Technology, Inc.Methods, circuits, and applications using a resistor and a Schottky diode
US7110229 *May 7, 2004Sep 19, 2006Sheng-Chieh YangESD protection circuit and display panel using the same
US7119524 *Aug 3, 2004Oct 10, 2006Bank America, N.A.Control of DC/DC converters having synchronous rectifiers
US7230807 *Dec 15, 2004Jun 12, 2007Vice Michael WProtection circuit for a transistor
US7233475 *Apr 13, 2006Jun 19, 2007Novatek Microelectronics Corp.Integrated circuit with an electrostatic discharge protection circuit
US7295411 *Aug 9, 2004Nov 13, 2007Matsushita Electric Industrial Co., Ltd.Semiconductor integrated circuit device
US7369379May 3, 2006May 6, 2008Micron Technology, Inc.Methods, circuits, and applications using a resistor and a Schottky diode
US7405435 *Oct 4, 2004Jul 29, 2008Kabushiki Kaisha ToshibaSemiconductor device having electrostatic destruction protection circuit using thyristor as protection element
US7503775 *Sep 5, 2007Mar 17, 2009Atmel Germany GmbhIntegrated protection circuit
US7518841 *Nov 2, 2004Apr 14, 2009Industrial Technology Research InstituteElectrostatic discharge protection for power amplifier in radio frequency integrated circuit
US7589944 *Jul 26, 2004Sep 15, 2009Sofics BvbaElectrostatic discharge protection structures for high speed technologies with mixed and ultra-low voltage supplies
US7804670 *Jan 7, 2005Sep 28, 2010Semiconductor Components Industries, L.L.C.Hybrid ESD clamp
US7929262 *Sep 21, 2001Apr 19, 2011National Semiconductor CorporationMethod and structure for avoiding hot carrier degradation and soft leakage damage to ESD protection circuit
US8164112 *Mar 7, 2001Apr 24, 2012Macronix International Co., Ltd.Electostatic discharge protection circuit coupled on I/O pad
US8248741Sep 16, 2009Aug 21, 2012Integrated Device Technology, Inc.Apparatuses and methods for a SCR-based clamped electrostatic discharge protection device
USRE38222 *Nov 9, 1999Aug 19, 2003Winbond Electronics Corp.Electrostatic discharge protection circuit triggered by capacitive-coupling
USRE38319Sep 25, 2001Nov 18, 2003Winbond Electronics CorporationDual-node capacitor coupled MOSFET for improving ESD performance
CN100524758CDec 18, 2006Aug 5, 2009上海华虹Nec电子有限公司SCR antistatic protection structure
CN100530649COct 14, 2005Aug 19, 2009安华高科技无线Ip(新加坡)私人有限公司Protection circuit for a transistor and method for preventing transistor from electrostatic discharge current
DE19711431C1 *Mar 19, 1997Nov 12, 1998Schurter GmbhElectronic electrostatic discharge protection circuit for electronic circuits
EP0827252A2 *Aug 11, 1997Mar 4, 1998Motorola, Inc.Non-breakdown triggered electrostatic discharge protection circuit for an integrated circuit and method therefor
Classifications
U.S. Classification327/310, 361/56, 327/428
International ClassificationH01L27/02
Cooperative ClassificationH01L27/0259
European ClassificationH01L27/02B4F4
Legal Events
DateCodeEventDescription
Aug 5, 2008FPExpired due to failure to pay maintenance fee
Effective date: 20080618
Jun 18, 2008LAPSLapse for failure to pay maintenance fees
Dec 24, 2007REMIMaintenance fee reminder mailed
Sep 25, 2003FPAYFee payment
Year of fee payment: 8
Sep 8, 1999FPAYFee payment
Year of fee payment: 4
Nov 5, 1996CCCertificate of correction
Mar 13, 1995ASAssignment
Owner name: INTERNATIONAL BUSINSS MACHINES CORPORATION CORPORA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:AU, WAI-MING;TONG, MINH H.;REEL/FRAME:007389/0896
Effective date: 19950310