|Publication number||US5532758 A|
|Application number||US 08/165,865|
|Publication date||Jul 2, 1996|
|Filing date||Dec 14, 1993|
|Priority date||Sep 25, 1990|
|Publication number||08165865, 165865, US 5532758 A, US 5532758A, US-A-5532758, US5532758 A, US5532758A|
|Original Assignee||Canon Kabushiki Kaisha|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (13), Referenced by (12), Classifications (25), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a continuation of application Ser. No. 07/764,771 filed Sep. 24, 1991, now abandoned.
1. Field of the Invention
The present invention relates to an image processing apparatus and, more particularly, to a digital image signal processing apparatus.
2. Related Background Art
In a prestage of A/D conversion for performing digital signal processing, an input signal must be clamped to obtain a stable, accurate digital signal. Various types of conventional clamp schemes are available. A digital feedback clamp scheme is known as a clamp scheme for obtaining a stable signal almost free from temperature drifts and influences caused by variations in power source voltage.
FIG. 4 shows an arrangement of a conventional digital feedback clamp circuit. An operation of the conventional digital feedback clamp circuit will be described with reference to FIG. 4.
An input analog video signal is converted into a digital signal by an A/D (Analog-to-Digital) converter 10, and the digital signal is input to a comparator 12 through a latch circuit 11. The comparator 12 compares output data from the latch circuit 11 with reference data and outputs a comparison result. For example, if the reference data is set to be 01H (hexadecimal notation), when an output from the latch circuit 11 is 00H, an output from the comparator 12 goes to "H" (high level) to increase the clamp level. However, if the output form the comparator 12 is 01H, the output from the comparator 12 is set in a high-impedance state, thereby maintaining the present clamp level. If the output from the latch circuit 11 is 02H or more, the output from the comparator 12 goes to "L" (low level), thereby decreasing the clamp level.
A clamp gate circuit 13 outputs an output from the comparator 12 at a timing of a clamp pulse shown in FIG. 2B. An output from the clamp gate circuit 13 contains noise from a digital circuit. This noise is cut off by a low-pass filter (LPF) 14 to obtain a stable DC (Direct Current) level. The clamp level of an output from the LPF 14 is input to a clamp switch circuit 16 through a buffer 15. The clamp switch circuit 16 clamps the input signal (i.e., the analog video signal) in accordance with a pulse similar to the clamp pulse of the clamp gate circuit 13. The pedestal portion of the input analog video signal is kept at a predetermined level by the above operations, thereby performing a stable clamp operation.
In the conventional digital feedback clamp circuit described above, however, since comparison is performed by the comparator after the input signal is converted into the digital signal by the A/D converter, an error of about ±1 LSB corresponding to the least significant bit upon digital conversion occurs due to noise superposed on the input signal and quantization noise during A/D conversion. For this reason, when digital processing is to be performed with a smaller number of gradation bits caused by a reduction in memory capacity, one bit has a significant meaning. Even if digital feedback clamp is performed, the input signal as a whole varies within the range of ±1 bit. Therefore, digital processing with high precision cannot be performed, resulting in inconvenience.
It is an object of the present invention to provide an image processing apparatus capable of solving all the conventional problems described above.
It is another object of the present invention to provide an image processing apparatus capable of performing a clamp operation with high precision.
It is still another object of the present invention to provide an image processing apparatus suitable for processing primary color signals.
In order to achieve the above objects according to an aspect of the present invention, there is provided an image processing apparatus having an n-bit memory to perform digital signal processing, comprising a digital feedback clamp circuit for A/D-converting an input signal with gradation having n+1 or more bits, thereby performing a digital feedback clamp operation.
The above and other objects, features, and advantages of the present invention will be apparent from the following detailed description of preferred embodiments in conjunction with the accompanying drawings.
FIG. 1 is a block diagram showing an arrangement of a digital feed back clamp circuit according to an embodiment of the present invention;
FIGS. 2A and 2B are timing charts showing waveforms of signals at points A and B in the block diagram of FIG. 1;
FIGS. 3A, 3B and 3C are waveform charts showing clamp precision of the digital feedback clamp circuit when A/D conversion gradation bits are changed in the circuit shown in FIG. 1;
FIG. 4 is a block diagram showing an arrangement of a conventional digital feedback clamp circuit; and
FIG. 5 is a block diagram showing an arrangement of a digital feedback clamp circuit according to another embodiment of the present invention.
Preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 shows a circuit arrangement according to an embodiment of the present invention.
Referring to FIG. 1, a digital feedback clamp circuit of this embodiment includes an A/D converter 1, a latch circuit 2, and a comparator 3. The A/D converter 1 converts an input analog video signal into a digital signal with 8-bit gradation. The latch circuit 2 receives and outputs the digital signal in response to a clock having the same speed as that of a sampling clock. The comparator 3 compares data output from the latch circuit 2 with the least significant bit of the digital signal and outputs a state signal representing an "H" (Vcc potential), "L" (GND potential), or high-impedance state.
The digital feedback clamp circuit also includes a clamp gate circuit 4, a low-pass filter (LPF) 5, an output buffer circuit 6, and a clamp switch circuit 7. The clamp gate circuit 4 outputs an output from the comparator 3 at a timing of a clamp pulse shown in FIG. 2B. The LPF 5 eliminates a noise component contained in an output from the clamp gate circuit 4. The output buffer circuit 6 is connected to the output of the LPF 5. The clamp switch circuit 7 clamps the input signal at the same timing as that of the clamp pulse supplied to the clamp gate circuit 4.
The digital feedback clamp circuit further includes a memory 8, a D/A (Digital-to-Analog) converter 9, and a clamp capacitor 10. The memory 8 stores digital signals from the latch circuit 2 in a 7-bit gradation structure. The D/A converter 9 converts an output from the memory 8 into an analog signal.
FIGS. 2A and 2B show the input signal in FIG. 1 and timings of the clamp pulse for this input signal. More specifically, FIG. 2A shows a color bar luminance signal (Y+S), and FIG. 2B shows the clamp pulse. In the arrangement shown in FIG. 1, the digital feedback clamp circuit of this embodiment is operated in the same manner as described in the "Related Background Art". The pedestal portion of the input video luminance signal is maintained at the 01H level of the digital data.
Since the difference between 8-bit gradation data and 7-bit gradation data in digital processing of the luminance signal is almost not noticeable in a conventional industrial video camera, a system is provided in which digital signal processing including A/D conversion is performed by 7-bit gradation data so as to reduce the memory capacity. In this case, when the conventional digital feedback clamp operation is performed, an error of ±1 bit occurs in A/D-converted data of the pedestal portion of the input signal due to noise and quantization noise. When A/D conversion is performed in an input range of 2VP-P, the least significant bit (1LSB) has a level of about 16 mV. Therefore, a clamp operation having a variation of ±16 mV is performed. This variation of ±16 mV causes a 6-mV variation of the input signal as a whole, as shown in FIG. 3A. Precision of digital signal processing upon A/D conversion is degraded.
In this embodiment of the present invention, in order to improve precision of digital feedback clamp processing for performing digital signal processing using a 7-bit gradation memory, the A/D converter 1, the latch circuit 2, and the comparator 3 in FIG. 1 are assigned with 8-bit gradation. When the input signal is set to have a range of 2VP-P and 8-bit A/D conversion is performed, the 1LSB has a variation of ±8 mV, thereby greatly improving precision as compared with 7-bit A/D conversion.
At present, 8-bit A/D converters are available as general-purpose converters at low cost. Even if 7-bit gradation digital signal processing is to be performed, an 8-bit A/D converter can be used. In this case, 8-bit digital feedback clamp processing is almost no different from 7-bit digital feedback clamp processing. When digital signal processing is performed using the 7-bit gradation memory 8, the digital feedback clamp processing including A/D conversion is performed with 8-bit gradation, thereby obtaining excellent clamp precision requiring almost no change in the conventional circuit.
Another embodiment of the present invention will be described below.
In the first embodiment described above, in the system for performing digital signal processing using the 7-bit gradation memory 8, 8-bit gradation digital feedback clamp processing is performed to double the clamp precision. In general, in a system for performing digital signal processing using an n-bit gradation memory, clamp precision can be doubled by using an n+1 -bit gradation digital feedback clamp circuit.
In addition, in the system for performing digital signal processing using the n-bit gradation memory, when an n+2-bit gradation digital feedback clamp circuit is used, influences of variations upon clamping of the input signal on the digital signal can be reduced to zero by converting the n+2-bit gradation into n-bit gradation upon A/D conversion. More specifically, in this case, as shown in FIG. 3C, all variations in the input signal caused by clamp upon an n+2-bit gradation digital feedback clamp operation are included within the range of 1LSB of the 7-bit gradation. Therefore, an error caused by clamp variations does not adversely affect n-bit gradation digital signal processing at all, and high-precision digital processing can be performed.
According to this embodiment, as has been described above, in the digital feedback clamp circuit connected to the input to the A/D converter for performing digital signal processing, the error of ±1LSB caused by noise or an A/D conversion quantization error generally causes variations in the input signal. According to the present invention, however, data is stored in the memory after A/D conversion, A/D conversion is performed with a larger number of gradation bits than that of digital signal processing by one bit, and the digital feedback clamp processing is performed. Therefore, influences of variations in input signal during clamping can be eliminated, and high-precision digital signal processing can be performed.
Another embodiment of the present invention will be described with reference to FIG. 5.
The same reference numerals as in FIG. 1 denote the same parts in FIG. 5, and a detailed description thereof will be omitted.
A recording medium 10 comprises, e.g., a magnetic disk. A reproducing process circuit 12 processes a signal reproduced from the recording medium 10. A photoelectric conversion element 14 comprises, e.g., a CCD for photoelectrically converting a target color image into primary color (R, G, and B) signals. An image process circuit 16 processes the R, G, and B color signals output from the photoelectric conversion element 14. An external input terminal 18 processes an external video signal.
A control circuit 22 controls a selection state of a multiplexer 20 and generates a clamp pulse in accordance with a detected selection state of the multiplexer 20. The control circuit 22 generates the clamp pulse in response to a horizontal sync signal output from a sync separation circuit 24.
In this embodiment, since the signal reproduced from the recording medium 10 has a relatively high possibility of containing a noise or jitter component, the control circuit is operated such that a clamp pulse having a relatively long duration is generated and a clamp pulse having a duration shorter than that of the clamp pulse for the recording medium is supplied for a signal having a small number of jitter components and output from a CCD or the like.
A stable clamp operation can be achieved regardless of different input sources.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4660085 *||Sep 25, 1985||Apr 21, 1987||Rca Corporation||Television receiver responsive to plural video signals|
|US4707741 *||Apr 11, 1986||Nov 17, 1987||Harris Corporation||Video signal clamping with clamp pulse width variation with noise|
|US4853782 *||Mar 9, 1988||Aug 1, 1989||Sanyo Electric Co.||Clamping circuit for clamping video signal|
|US4965669 *||Apr 12, 1989||Oct 23, 1990||Rca Licensing Corporation||Apparatus for digitally controlling the D.C. value of a processed signal|
|US5003564 *||Apr 4, 1989||Mar 26, 1991||Rca Licensing Corporation||Digital signal clamp circuitry|
|US5019905 *||Sep 18, 1987||May 28, 1991||Vicon Industries, Inc.||Encoding and decoding of multiple video sources|
|US5057920 *||Jan 31, 1990||Oct 15, 1991||Sony Corporation||Video signal clamping circuit operating in the digital domain for removing excess noise on the black level and for providing d c restoration|
|US5084700 *||Feb 4, 1991||Jan 28, 1992||Thomson Consumer Electronics, Inc.||Signal clamp circuitry for analog-to-digital converters|
|US5087973 *||Nov 17, 1988||Feb 11, 1992||Matsushita Electric Industrial Co., Ltd.||Clamp signal processing apparatus|
|US5105276 *||Nov 15, 1990||Apr 14, 1992||Eastman Kodak Company||DC restoration of sampled imagery signals|
|US5134487 *||Nov 5, 1990||Jul 28, 1992||Canon Kabushiki Kaisha||Using common circuitry for different signals|
|US5191422 *||Jul 25, 1990||Mar 2, 1993||Nec Corporation||Clamp level setting method for television signals|
|JPS62208763A *||Title not available|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US5719638 *||Jul 7, 1995||Feb 17, 1998||Rohm Co. Ltd.||High speed image density converting apparatus|
|US5731771 *||Nov 21, 1995||Mar 24, 1998||Sgs-Thomson Microelectronics S.A.||Circuit for locking a signal to a reference value|
|US6580465 *||Jan 8, 1999||Jun 17, 2003||Pentax Corporation||Clamp voltage generating circuit and clamp level adjusting method|
|US7106231 *||Oct 27, 2004||Sep 12, 2006||Mstar Semiconductor, Inc.||Video signal processing system including analog to digital converter and related method for calibrating analog to digital converter|
|US7295234 *||May 23, 2003||Nov 13, 2007||Sony Corporation||DC level control method, clamp circuit, and imaging apparatus|
|US7589795 *||Mar 23, 2006||Sep 15, 2009||Novatek Microelectronics Corp.||Automatic clamping analog-to-digital converter|
|US7646412 *||Jan 12, 2010||Sony Corporation||DC level control method, clamp circuit, and imaging apparatus|
|US8269863 *||Oct 23, 2007||Sep 18, 2012||Sony Corporation||Solid-state image pickup device and image pickup apparatus|
|US20040008270 *||May 23, 2003||Jan 15, 2004||Yasuaki Hisamatsu||DC level control method, clamp circuit, and imaging apparatus|
|US20050093722 *||Oct 27, 2004||May 5, 2005||Sterling Smith||Video signal processing system including analog to digital converter and related method for calibrating analog to digital converter|
|US20070247533 *||Jun 11, 2007||Oct 25, 2007||Sony Corporation||DC level control method, clamp circuit, and imaging apparatus|
|US20080094489 *||Oct 23, 2007||Apr 24, 2008||Sony Corporation||Solid-state image pickup device and image pickup apparatus|
|U.S. Classification||348/694, 386/E09.005, 348/E05.071, 348/257, 348/695, 348/572, 348/697|
|International Classification||H04N19/59, H04N19/00, H04N19/80, H04N19/423, H04N19/85, H03K3/00, H04N5/14, H04N5/16, H04N11/04, H04N9/79, H03M1/12, H04N5/18|
|Cooperative Classification||H03M1/1295, H04N9/7904, H04N5/18|
|European Classification||H04N9/79D, H04N5/18, H03M1/12S4C|
|Dec 29, 1999||FPAY||Fee payment|
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|Dec 11, 2007||FPAY||Fee payment|
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