|Publication number||US5535223 A|
|Application number||US 08/390,827|
|Publication date||Jul 9, 1996|
|Filing date||Feb 17, 1995|
|Priority date||May 28, 1993|
|Publication number||08390827, 390827, US 5535223 A, US 5535223A, US-A-5535223, US5535223 A, US5535223A|
|Inventors||Jens Horstmann, James Testa|
|Original Assignee||Sun Microsystems, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (11), Referenced by (72), Classifications (16), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This is a continuation of application Ser. No. 08/068,985, filed May 28, 1993 now abandoned.
1. Field of the Invention
The present invention relates to a system for performing verification and testing of electrical circuits.
2. Art Background
The use of computer aided design (CAD) tools to design and physically test the designed electrical circuits have become quite popular. Using these tools, a circuit designer can develop a circuit, simulate the operation of the circuit to verify the circuit operation and subsequently generate the information necessary for a circuit testing apparatus to test the fabricated circuit.
Before fabrication of the electrical circuit, it is desirable to perform a verification of the operation of the system in order to determine whether the system designed would operate as intended. A variety of tools which perform a verification of an electrical circuit design often referred to as "switched level tools" presently exist, such as SPICE, provided by the University of California, Berkeley; MOTIVE, provided by Quad Design Technology Inc., Camarillo, Calif.; VERILOG, provided by Cadence, Inc., San Jose, Calif. and LSIM, provided by LSI Logic, Milpitas, Calif.
Typically, a simulation will perform a functional analysis and a timing analysis on the circuit. A functional analysis verifies that the logic of the circuit operates as intended. Timing verification determines that the components of the circuit operate within time constraints and are compatible with interconnected components. For example, as shown in FIG. 1a, the circuit may consist of one or more components 10, 15, 20 which communicate, for example, via bus 25, 30, with each other or input or output information.
The advances in circuit technology have rendered many of these tools inefficient and difficult to use. Circuits today are processing signals faster and faster. Signals are communicated along signal lines at very high speeds. However, with high speed signals, the lines interconnecting components can no longer be simply configured by RC modeling to simulate loading, but operate with the characteristics of transmission lines which have varying effects on the circuit timing and therefore must be modeled in order to accurately perform verification. Many logic verification programs are digital in nature and do not have the capability to accurately model a complex analog transmission line.
To address this problem existing tools have been modified to verify both the digital components and analog transmission lines. An example is MBSIM product provided by LSI Logic, Inc., or Verilog PLI provided by Verilog. In these mixed mode or "switched level" tools, a logical or digital verification is sequentially performed on a chip and carried through the analog environment of the transmission line to the input of the next chip at which time a digital or logical simulation is performed. This simulation requires a significant amount of time to perform as the digital and analog testing is serial in nature. Furthermore, the simulation requires a significant amount of memory in order to maintain the various states of the different components in the circuit.
Furthermore, the margins which specify the range of time values permitted for each signal have become narrower and thus less forgiving due to the increase in signal speeds. Therefore, the need to accurately and precisely verify a circuits' timing is even more important.
Typically each chip manufacturer has developed a set of tools to assist in the verification of designs using their components. However, compatibility among the different tools by different manufacturers is minimal at best. Previously, this was not a problem because a circuit would only include components provided by a single manufacturer and that, manufacturer's design tools would be utilized. However, today it is not at all uncommon to develop a circuit which includes components from a variety of manufacturers. To overcome incompatibility problems, a circuit designer may develop a behavior model of a component which is not compatible with the tools that are in use. However, these behavior models often do not precisely emulate the component, resulting in unforeseen results when the component is subsequently tested.
The overhead of a prior art system which attempts to perform both timing and functional testing is quite significant. The overhead is incurred due to the sequential nature of the verification operation. Functional and timing verification is performed on each component and interconnect of the circuit. This process is quite slow and requires a significant amount of memory to maintain the information for each component during verification of the circuit. This is better explained with reference to FIGS. 1b and 1c.
FIG. 1b illustrates portions of two components 35, 40 interconnected via a signal line 45 and system clock line 50. Referring to FIG. 1c, in order to verify proper timing between components 35, 40 the signal output by Chip 1 35 must be stable at the input of Chip 2 40 prior to the setup (and hold) time specified for Chip 2 40 and the propagation delay through buffer B2 55. The margin 60 identifies the amount of time between when the output signal is stable at the input of Chip 2 40 and when the output signal is latched by Chip 2 40. To determine the margin, propagation delay through the flip flop 60 and buffer 65 must be determined, as well as the delay caused by transmission line T1 70. Furthermore, the setup and hold time for the input to Chip 2 40 as well as the propagation delay through the buffer B2 55 is factored in.
The system of the present invention provides for the verification of electrical circuit designs and the generation of the information necessary to interface with computer aided testing equipment to physically test the fabricated circuits. The verification of the circuit is divided into two portions, functional verification and timing verification. To perform the timing verification, the components, or chips that are part of the circuit, are treated as black boxes having unit delays. The functional verification process verifies the function or logic of each component and circuit or system of interconnected components. As the timing component is eliminated, it is preferred that an exhaustive static simulation is performed. An analog circuit timing verification package, such as TLC or SPICE, may be used to verify the timing of the analog circuit comprised of chips having unit delays and transmission line interconnecting the different chips.
The timing and functional verification processes can be performed independently of each other. Based on the results of the independent timing and functional verification, the designers can adjust certain chip and system function and/or timing specifications in order to produce a circuit design that in simulation meets requirements.
Information generated during the verification using the separate functional and timing simulations are then combined into a single uniform or core structure which is easily converted to a variety of vendor specific environments and circuit testing apparatus which physically tests the fabricated circuit. To generate the core structure, the unit delays previously employed to perform the timing tests are adjusted according to chip timing specification setup and hold times specified. From this core structure, the test vectors required by the physical test apparatus to physically test a fabricated circuit are generated.
The advantages to this system are a significant increase in speed, minimal memory usage, and flexibility by enabling the chip designers to work somewhat independently of the circuit or system designers during the simulation and test of the electrical circuit. Less memory is required as the functional testing of the individual components does not have to be carried through the system timing test of the circuit. An increase in speed is achieved because many of the functional verification and the timing verification processes can be performed in parallel. Furthermore, the modularity of the system enables the system to be vendor independent and interface with a variety of vendor specific tools.
The objects, features and advantages of the present invention will become apparent to one skilled in the art in view of the following detailed description in which:
FIG. 1a is a block diagram illustration of an exemplary system to be simulated and tested; FIG. 1b and 1c illustrate exemplary test considerations for a circuit interconnect.
FIG. 2 is a block diagram representation of the process flow for simulation and verification in accordance with the present invention.
FIG. 3 is a block diagram representation of the system of the present invention for verification and testing.
FIGS. 4A and 4B-4F illustrate the core data structure utilized in the system and method of the present invention.
FIGS. 5A-5H provide simplified examples of a circuit and corresponding vectors list, timing envelope specification, and other information utilized and generated in accordance with the system and method of the present invention.
FIGS. 6a, 6b, 6c, 6d provide an illustrative manual page identifying inputs, outputs and options for the present embodiment.
FIGS. 7a, 7b, 7c illustrate the generation of the timing test vector file in accordance with the system and method of the present invention.
FIG. 8 is an exemplary timing diagram describing the masking function.
FIGS. 9a, 9b, 9c illustrate chip output load mapping performed in one embodiment of the method and apparatus of the present invention.
FIG. 10a, 10b, 10c illustrate load mapping performed in another embodiment of the method and apparatus of the present invention.
A system for the simulation verification and testing of electrical circuits is disclosed. In the following description for purposes of explanation, numerous details are set forth in order to provide a thorough understand of the present invention. However, it will be apparent to one skilled in the art that these specific details are not required in order to practice the invention. In other instances, well known electrical structures, circuits and systems are shown in block diagram form in order not to obscure the present invention unnecessarily.
The process can be generally described with reference to FIG. 2. The testing of the electrical circuit is divided into two parts: functional verification using functional simulation, step 100, and timing verification of the electrical circuit using static testing, step 110. The functional verification process simulates the circuit from a logic perspective to determine whether the components interact in the manner intended. Information regarding timing is not considered, rather, each element is considered to have a unit delay. Thus, signals will propagate through elements at each reference clock provided as part of the simulation. Functional verification can be performed using commercially available products to test the circuits. Typically, chip vendor specific simulation tools, such as third party tools, are used to test each component. The chip designer, based upon the output of the functional testing, can modify the design accordingly to optimize the functional operation of each component.
Independently of the functional verification, timing verification can be performed, step 110. In order to evaluate the circuit from a timing perspective, each component in the circuit is treated as a black box in which the internal elements of the component are not evaluated; rather, parameters identifying the strobe time and clock-to-output delay (also referred to as the clock-to-Q delay) through the component and the setup and hold times for each component are utilized. Thus, analysis may be focused on the propagation of signals through the circuit as a whole and, in particular, the effects of signal transmission lines on signal propagation. To perform the timing verification, packages such as HSPICE by Meta-Software, San Jose, Calif., may be used. Typically, timing verification is performed by simulating the circuit operations and comparing the timing of valid signals at the inputs of components to the setup and hold times specified in the timing specification for the component. This information is typically maintained in the timing envelope specifications for each of the components of the circuit. The timing envelope specifications are generated based upon such factors as electrical characteristics of transmission lines, bus specifications and chip specifications.
The flexibility achieved by separately verifying the circuit functionally and timing is readily realized. For example, if the timing verification indicates that certain time requirements are not met, the circuit designer can go back to the design and modify the circuit and re-perform in parallel the functional testing and timing testing. This redesign of the circuit will accordingly modify the parameters specified in the timing envelope specification and therefore the parameters as to whether the circuit design meets timing requirements. The chip designers may also modify the chip design or margin requirements for signal timing, which causes modification of the timing envelope specification, in order to meet timing requirements.
As functional testing is performed, test vectors are extracted at each reference clock, step 120, and a chip test vector file (CTV) is generated. These test vectors include an identification of the input/output pins of the component and the logic state of the pins at each clock. The test vectors and the timing envelope specifications are subsequently combined with signal masking information, step 115, into a core data structure, step 130, from which vendor specific data for each chip can be easily generated to perform dynamic timing verification using vendor specific tools, step 135, and timing test vector files which are compatible with test apparatus for the physical testing of the fabricated components, step 140.
A block diagram illustration of the system is shown in FIG. 3. The circuit 160 can be embodied in a plurality of different formats and data structures in accordance with the chip manufacturer's formats or system designer's formats for definition of the components and interconnection of the components. For example, the circuit may be defined in accordance with the Motive format specified in the MMP (Motive Model Processor) software provided by Quad Design Technology, Inc, Camarillo, Calif. In the present invention, a collar 170 surrounds each component 160. The collar 170 functions to extract the vector data for the test vector file during verification of each component. This can be easily implemented a number of ways including the reading and writing of certain registers or memory locations identified to be the input/output pins of the simulated component, or by using utilities provided with certain test programs. For example, using the Verilog language, manufactured by Cadence, Inc., the collar can be generated simply by including code to specify at each clock edge (either positive or negative) to write the state of identified pins to a file. Preferably the collar is provided access to the circuit layout file which identifies the input/output pins so that the pin naming is consistent with the pin names identified in the circuit layout file.
The timing verification module of subsystem 180 also utilizes certain circuit information such as the circuit layout identifying the interconnection of components and the characteristics of the interconnect between components and timing envelope specifications 200 for each of the components, and assumes that the timing requirements are as specified by the clock-to-output and setup/hold times specified in each component's timing envelope specification 200. Therefore, actual simulation can be focused, but not the functional aspects of each component, on the clock-to-output delays and signal timing such as effects of transmission lines which occur on signal propagating between components.
If the timing verification indicates that certain timing requirements are not met, a number of things may occur. For example, the chip designer may be required to modify a component's design or timing envelope specification. The system designer may also modify timing margins or the layout of the circuit. The verification-design process can then be performed in an iterative manner until the design is adequately verified.
Once the timing verification and functional verification are complete, the information from the chip test vector file (CTV file) and each component's timing envelope specifications are combined, block 190, to generate chip vendor specific information and a core structure from which the timing test vectors used by the test apparatus which physically tests fabricated components can be generated. As will be subsequently explained, the core data structure is generated by modifying the chip test vector file to include timing information. This timing information is extracted from the timing envelope specifications of the components.
In a preferred embodiment, the combination module itself is modular and can be viewed as consisting of three elements: the input element, core and output element. This is illustrated in FIG. 4a. The input element 445 receives the input data, in the present embodiment, the test vector file 430, the timing envelope specification 435 and masking information 440 and generates the data structure comprising the core 450. The core 450 remains consistent in format for a variety of inputs and outputs. Preferably the core 450 includes the following information such as is shown in FIGS. 4b-1-4b-5. The output module 455 references the core 450 to generate output files 460-465, 470 compatible with vendors of test and design equipment. By modifying the input module and output module to accommodate different vendor inputs, a flexibility to accommodate a variety of testing and simulation conditions is achieved.
FIGS. 5A through 5H provide a simplified illustration of the data utilized in the system of the present invention. It should be realized that other formats and data structures may be used. FIG. 5a illustrates a simple component having three inputs IA, IB and IC and three outputs OA, OB, OC. FIG. 5b illustrates an exemplary test vector file showing the identification of the input and output pins of the component and the vector list identifying the state of the pins at each reference clock. FIG. 5c is illustrative of a timing envelope specification accessed during the timing test simulation of the circuit. Included in the timing envelope specification is such information as the setup and hold times for each pin and the clock-to-Q delay through component. The test vector file and information from the timing envelope specification, such as the setup and hold times identified with respect to each pin of each component, is used to generate a core data structure, from which a timing test vector file can be generated. In the present embodiment, to initiate the process for combining functional information (test vectors) with the timing information from the timing envelope specifications, a command file, such as illustrated in FIG. 5d is used, a plurality of options, such as those shown in the manual page for the program may be selected. FIGS. 6a-6d are a listing of a manual page for the present embodiment. For example, the input timing and/or output timing can be adjusted as shown in the example of FIG. 5d. Furthermore, a mask file can be identified, as will be explained below, a mask file permits a user to identify certain pin signals to mask dynamically when certain other identified pin signals are in predetermined state. An example of a mask file is shown in FIG. 5e. Another input to the process is a chip specification file to identify loading information for certain testing equipment. For example, as shown in FIG. 5f, the loading on inputs IB, IC and output pins OA and OB are identified. Furthermore, loading can be tester specific whereby loading information can be derived from tester specification. FIGS. 5G and 5H provide a pin data information dump illustrating some of the information collected from the inputs to the combination module.
The process for combining the functional and timing information will be explained with reference to FIGS. 7a, 7b and 7c. FIG. 7a shows a vector list for two input signals, pins A and B and output pin C. Pin A at a first referenced clock has the state of 1, B has the state 0 and C has a state of zero. At the second referenced clock, both Pin A and Pin B are in a 1 state and C is in a 1 state. From the timing envelope specification, it is known that the Pin A has a setup and hold time of 5 seconds and 3 seconds respectively. Similarly, Pin B has a setup time of 7 nanoseconds and a hold time of 4 nanoseconds. Pin C has a clock to output of 20 nanoseconds. As shown in the table of FIG. 7b and the timing diagram of FIG. 7c, at the first rising edge of the reference clock, which occurs at twenty nanoseconds, the signal at Pin A is adjusted by subtracting 5 nanoseconds, the setup time for Pin A, from the 20 nanoseconds of the referenced clock. Thus, at 15 nanoseconds Pin A has a value of 1. At the end of the hold time, Pin A will be restored to the 0 state. An entry is therefore generated in which at 23 nanoseconds (3 nanosecond hold time beyond the 20 nanoseconds of the clock edge) Pin A reverts to a 0 state.
At the next clock, which occurs at 50 nanoseconds because the clock pulse is at 30 nanoseconds apart, both Pin A and Pin B go to a 1 state. However, they occur at different times. Specifically, Pin A has a setup time of 5 nanoseconds and Pin B has a setup time of 7 nanoseconds. Therefore, an additional entry is provided to separately identify the change of state of both pins. At 43 nanoseconds (50 nanoseconds minus 7 nanoseconds) Pin B is in a 1 state. The next entry is the setting of Pin A to a 1 state. This occurs at 45 nanoseconds. As the hold times for Pin A and Pin B are different, again two entries are provided for the indication of a change of state of the pins. Thus, an entry is entered at 53 nanoseconds to indicate that Pin A, having a hold time of 3 nanoseconds, reverts to 0, while Pin B still is in a 1 state. At 54 nanoseconds, Pin B similarly reverts to 0. At 45 nanoseconds both Pin A and Pin B are in one state, indicating that Pin C should change to a one state at a time clock-to-output nanoseconds later. Therefore at 65 ns, Pin C changes to a 1 state.
This information is preferably stored in a core data structure from which a tester file is generated for a specific testing apparatus which physically tests a fabricated circuit. Thus, the tester will know when to assert certain signals at the inputs and monitor the change of state of signals at the outputs. Preferably the file is generated in a print-on-change format compatible with most testing devices. However, it is apparent that any format can be generated.
In addition to combining the test vector file with timing information, the combination module further has the capability to perform a dynamic masking of certain strobe signals. The masking function is described with reference to FIG. 8. The output signal DOUT1 is shown having two data valid signals 610, 615 separated by a short period of time 620 during which data is invalid. Data is specified to be valid for Chip 1 by the Valid 1 signal. During testing of the fabricated chip, the tester will strobe the input pin of Chip 1, which receives as input DOUT1, at each clock interval, for example, 630, 635, 640, 645. At strobe 640, however, the tester will sample invalid data. Subsequent testing of best case and worse case may cause the window of valid data 615 to shift such that at strobe 640, valid data is sampled. In order to avoid these inconsistencies, it is desirable to mask the strobe signal. Most commercial testers provide for masking of certain strobe signals by inserting a mask character in the file at the pin and time to be masked. However, this is typically done manually by editing of the tester file. To avoid this cumbersome and time consuming task, an innovative method for dynamically masking the testing of certain strobe signals at certain input/output pins is provided. Although the dynamic masking method and system is described in conjunction with the simulation and test system described herein, it is readily apparent that the dynamic masking can be applied to other simulation and test systems.
Preferably, an interpreter is utilized to interpret code which generally identifies the pins and strobe signals to mask. As a test file can include thousands (even hundreds of thousands of . . . ) of test vectors, this advantage to this ability is easily realized. The code includes at least one logic statement which identifies the signal which is referred to to determine whether to mask the strobe signal and the particular pin which is masked. For example, referring to FIG. 8, the logic statement may read:
FOR VAILD1. EQ. 1 THEN TURN ON MASK CHIP1, PIN 1;
FOR VALID1. EQ. 0 THEN TURN OFF MASK CHIP1, PIN1.
or may be in a format such as:
Utilizing the timing information in the core data structure which identifies the timing of the strobe as well as the state of the VALID1 signal with respect to the strobe signal, the mask information can automatically be generated. Furthermore, the code can include multiple logic statements to identify masking with respect to a plurality of pins (see FIG. 5e).
In the preferred embodiment, a mask file, containing the code specifying the masking to be performed, is input to the combination module along with the test vector file and timing envelope specification. The combination module determines the masking information along with the timing information. At those pins and times at which masking is asserted, a code, such as a "*" or an "X" is inserted to identify a "don't care" with respect to the signal, thereby performing a masking function. When the test file is generated, this symbol is then converted to a mask symbol compatible with the tester format.
The combination module is further provided with the capability to accommodate loading which occurs when the fabricated circuit is tested. The system environment and simulation environment do not reflect the tester environment, particularly the loading which occurs when the circuit is connected to a tester for testing of the fabricated circuit. This is due to the problem that the simulation typically only provides for lumped capacitance and does not take into account the analog effects of loading on the transmission lines between components. The resultant effect is that the timing of a component may be different for each tester used.
To eliminate these discrepancies, load mapping is performed. This is explained with reference to FIGS. 9 and 10. For signal propagation access, for example, transmission lines a pair of measurements for best case and worse case in each environment are generated. These measurements are generated by modifying the environment parameters which affects the best case and worse case measurements, such as input voltages and temperature of operation, and measuring the delays caused by the variations. The measurements are plotted against each environment in order to determine a mapping between environments. Referring to FIG. 9a an illustrative system of three chips 905, 910, 915 connected by transmission lines 920, 925, 930 is shown. The loading 940 with respect to chip 1 905 is illustrated by FIG. 9b. FIG. 9c shows the mapping between the system and tester environments is generated as evidenced by the slope of the line 955 between the intersections of the best cases and worse cases in the system and tester environments. In the present example, an adjustment of the strobe time compensates for the loading of the tester. Therefore, if the tester strobe is adjusted to occur at 6.5 ns for tester loading, this ensure that the chip perform at a strobe time of 4 ns under system loading. Thus, the circuit in the system environment behaves as it will in the tester environment.
As noted above, a mapping can also be generated between the simulation and system environments. FIG. 10a illustrates the circuit in the system environment which includes components chip 1 1005, chip 2 1010, chip 3 1015 and transmission lines 1020, 1025, 1030. FIG. 10b illustrates the circuit with respect to chip 1 1005 and the loading due to the remainder of the circuit. In the example, the capacitance 1040 representing the loading of the remainder of the circuit is adjusted to match in both the system and simulation environments such that a curve mapping the timings of the two environments produce a curve having a slope of 45 degrees. This is illustrated by FIG. 10c which shows a plurality of mappings 1050, 1055, 1060, 1065 for different capacitance values. The capacitance is adjusted such that tΔ in the system and simulation environments match to produce a 45 degree curve, such as mapping 1055.
Although the present invention has been described in terms of the preferred embodiment, it will be appreciated that various modifications and alterations may be made by those skilled in the art without departing from the spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
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|U.S. Classification||714/744, 714/33, 716/106, 716/108, 716/134|
|International Classification||G06F17/50, G01R31/28, G01R31/3183|
|Cooperative Classification||G01R31/318357, G01R31/2882, G01R31/318307, G06F17/5022|
|European Classification||G01R31/28G3, G06F17/50C3, G01R31/3183A, G01R31/3183F3|
|Jan 4, 2000||CC||Certificate of correction|
|Jan 7, 2000||FPAY||Fee payment|
Year of fee payment: 4
|Jan 28, 2004||REMI||Maintenance fee reminder mailed|
|Jul 9, 2004||LAPS||Lapse for failure to pay maintenance fees|
|Sep 7, 2004||FP||Expired due to failure to pay maintenance fee|
Effective date: 20040709