|Publication number||US5536669 A|
|Application number||US 08/507,698|
|Publication date||Jul 16, 1996|
|Filing date||Jul 26, 1995|
|Priority date||Jul 26, 1995|
|Publication number||08507698, 507698, US 5536669 A, US 5536669A, US-A-5536669, US5536669 A, US5536669A|
|Inventors||Kuan-Cheng Su, Yi-Chung Sheng, Chen-Hui Chung|
|Original Assignee||United Microelectronics Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (3), Referenced by (11), Classifications (6), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates to a method for fabricating semiconductor memory devices, and more specifically, to a method for fabricating read-only-memory (ROM) devices with self-aligned code implants.
2. Description of the Prior Art
Semiconductor ROM devices are generally composed of a plurality of memory cells which are formed by intersecting a number of bit lines and word lines on semiconductor substrates. Since each memory cell of the ROM device corresponds to a transistor, its on/off states can be well-controlled by properly adjusting the dopant concentration of the transistor's channel region. That is, the ROM devices are programmed through a specific arrangement of code diffusion regions in the semiconductor substrates, thus deciding the conducting states of the channel regions and the on/off states of the memory cells. These will be described in detail as follows.
In general, the code diffusion regions are formed by implanting ions into the semiconductor substrates through code masks, thus the name "mask ROM." A conventional manufacturing process for a mask ROM device will now be described in accompaniment with the cross-sectional views of FIG. 1 through FIG. 3. In the present example, the ROM device is fabricated on a silicon substrate having a P-type conductivity, that is, each memory cell is an N-type transistor.
First referring to FIG. 1, a gate oxide layer 13 and a polysilicon layer 15 are subsequently formed over silicon substrate 11. Since polysilicon layer 15 contains impurities, it has high conductivity and is provided for the word lines of the ROM device. Therefore, through a photolithography step and an etching step, polysilicon layer 15 is patterned into a plurality of word lines 16, as is depicted in FIG. 2.
It is noted that the structure of FIG. 2 may be subjected to an ion implantation step to form a plurality of bit lines in the substrate before the formation of word lines 16. Since the cross-sectional views of FIG. 1 through FIG. 3 are taken along the channel regions of the memory cells, the bit lines are not shown in the figures.
Further referring to FIG. 3, another photolithography step is performed to form a photoresist layer 17 as a code implant mask over the structure of FIG. 2. Photoresist layer 17 covers all memory cells but the channel regions of off-state memory cells. Then through code implant windows 18 defined by photoresist layer 17, P-type ions, such as boron ions, are implanted into the exposed channel regions of the memory cells to form code diffusion regions 19 in substrate 11.
The aforementioned ROM device operates by changing the voltage of word lines 16 between a high level and a low Level. For the "on"-cells, when the voltage of word lines 16 is at a high level, the channel regions beneath the word lines in the substrate will be turned on and current flow through the bit lines will be sensed. The "off"-cells have code diffusion regions 19, giving their channel regions a higher dopant concentration than that of the "on"-cells, so they need a higher threshold voltage to turn on the channels. That is, unless the high level voltage of the word lines increases, the memory cells having the code diffusion regions in their channel regions will maintain in the "off" state. Therefore, the ROM device can be programmed to contain both the "on"- and "off"-cells as desired.
However, the above-mentioned code implant process will result in impurity diffusion. Since the code implant mask, i.e., photoresist layer 17 in FIG. 3, may shift away through mis-alignment in the photolithography step, code diffusion regions 19 in substrate 11 will also shift away. With the shrinkage of the ROM device, if code diffusion regions 19 are not in their intended location, they will be very close to the channel regions of other memory cells. Since boron ions have a high diffusion coefficient, and they are generally utilized for code implantation as stated above, they will probably diffuse to the channel regions of any nearby memory cells, changing the dopant concentration therein. Therefore, an original "on"-cell may fail to turn on, thus becoming an "off"-cell due to the diffusion of boron ions.
The programming errors caused by the mis-alignment of the code mask and diffusion of impurities will become more serious as the dimension of the semiconductor device decreases. Therefore, the yield of the ROM memory devices can not be improved without modifying the conventional code implant process.
Accordingly, the present invention provides a method for fabricating ROM devices with self-aligned code implants, concentrating the impurities of the code diffusion regions beneath the word lines, and thus preventing their diffusion to other cells.
The method for fabricating ROM devices with self-aligned code implants according to one preferred embodiment of the present invention comprises the steps of: forming an oxide layer over the silicon substrate; forming a plurality of deposition selecting strips over the oxide layer; forming a plurality of dielectric strips between each two of the deposition selecting strips; removing the deposition selecting strips; forming a number of code diffusion regions in the silicon substrate; and forming a plurality of word lines between each two of the dielectric strips. Since the code diffusion regions are formed by implanting ions through the dielectric strips, the shielding of the dielectric strips prevents the spreading out of impurities due to the mis-alignment of code mask. Therefore, the positions of code diffusion regions can be well controlled beneath the word lines.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The description is made with reference to the accompanying drawings in which:
FIG. 1 through FIG. 3 are cross-sectional views illustrating a prior art process for fabricating a ROM device;
FIG. 4 through FIG. 10 are cross-sectional views illustrating the process for fabricating a ROM device according to the preferred embodiment of the invention; and
FIG. 11 is a plan view illustrating the ROM device of the preferred embodiment of the invention; wherein the cross-sectional view of FIG. 10 is taken along the X--X line of the figure.
The cross-sectional views of FIG. 4 through FIG. 10 illustrate the fabrication process of a ROM device according to the preferred embodiment of the present invention. Even though the ROM device is fabricated on a P-type silicon substrate in the preferred embodiment, the method of the present invention can also be applied to form P-type memory devices on an N-type silicon substrate.
Referring to FIG. 4, a P-type silicon substrate (or a P-type well region in an N-type silicon substrate) 21 is subjected to an oxidation step to form an oxide layer 23 thereon. Then an ion implantation step may be carried out to form a plurality of bit lines in silicon substrate 21. Since the cross-sectional views from FIG. 4 to FIG. 10 are all taken for illustrating channel regions of the ROM device, the bit lines are not shown in the figures. Nevertheless, the bit lines will be observed in a plan view (FIG. 11) of the ROM device when the process is finished.
Next referring to FIG. 5, a plurality of deposition selecting strips 25 are formed over oxide layer 23. Deposition selecting strips 25 can be formed by photoresist or other materials that have good selectivity to the liquid-phase deposition (LPD) of silicon dioxide. In the preferred embodiment, a photoresist layer is formed over oxide layer 23 and then patterned in a photolithography step, thus forming deposition selecting strips 25.
Therefore, the liquid-phase deposition of silicon dioxide can be performed to form a plurality of dielectric strips 27 between every two deposition selecting strips 25, as depicted in FIG. 6. The LPD process is based on the following two equations.
H.sub.2 SiF.sub.6 +2H.sub.2 O=6HF+SiO.sub.2
H.sub.3 BO.sub.3 +4HF=BF.sub.4.sup.- +H.sub.3 O.sup.+ +2H.sub.2 O
Therefore, dielectric strips 27 are formed only over the surface of oxide layer 23 between the photoresist strips, and the surface of photoresist strips 25 will not be deposited with the dielectric material. Since it is preferable that deposition selecting strips 25 have a thickness between 10K and 20KÅ, the LPD process is carried out to form the dielectric layer to a thickness between 1500 and 5000 Å.
After removing deposition selecting strips 25, as depicted in FIG. 7, the code implant process can be performed through the shielding of dielectric strips 27. Referring to FIG. 8, a code mask 28 which can be a photoresist layer is formed over dielectric strips 27 and oxide layer 23 to expose a code implant window 30. An ion implantation step is then performed to form code diffusion region 29 in the substrate. The ion implantation step can be carried out by implanting boron ions (BF2) at an implanting energy between 30 KeV and 90 KeV.
Further referring to FIG. 9, the code mask layer is removed and a plurality of word lines 31 are formed between each two dielectric strips 27. As has been stated in the prior art, the voltage levels of word lines 31 control the on/off states of the memory device, that is, word lines 31 are provided for the gate electrodes of the ROM device. In order to improve the quality of the gate oxide layer, oxide layer 23 between the dielectric strips 27 has been removed, and a new gate oxide layer has been formed by another oxidation step before the formation of word lines 31. In the preferred embodiment, word lines 31 can be formed by depositing a polysilicon layer over oxide layer 23 and dielectric strips 27, and then etching back the polysilicon layer to a thickness between 1000 and 4000 Å inside trenches formed by the dielectric strips. The conductivity of word lines 31 can be improved by doping impurities in the polysilicon layer during the deposition process or after its completion.
The structure of FIG. 9 may further be covered by a passivation layer 33 and then subjected to other post-processes, as shown in FIG. 10. The passivation layer can be a layer of boron-phosphorous silicate glass (BPSG) and the like. The post-processes may include the formation of contact windows, metallization, packaging and so on.
A plan view of the final ROM device is illustrated in FIG. 11, wherein the cross-sectional view taken along the X--X line corresponds to FIG. 10. Referring to FIG. 11, a number of word lines 31 and bit lines 30 intersect to constitute the memory cells. There are also dielectric strips 27 between every two word lines 31. The region 29 encircled by dashed line is the code diffusion region which has been formed in the substrate by the code implant process. The location of region 29 will not shift away since the thickness of dielectric strips 27 is large enough to prevent ions from being implanted into the substrate due to the mis-alignment of the code implant mask during the code implant process. Therefore, impurities of the code diffusion region will concentrate beneath word lines 31, and their diffusion to the channel regions of other cells will not occur. That is, through the code implant process of the present invention, even the dimension of the ROM device is reduced, there will be no more programming errors due to impurity diffusion.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5200355 *||Nov 15, 1991||Apr 6, 1993||Samsung Electronics Co., Ltd.||Method for manufacturing a mask read only memory device|
|US5278078 *||May 12, 1992||Jan 11, 1994||Kabushiki Kaisha Toshiba||Method of manufacturing semiconductor device|
|US5449632 *||Aug 12, 1994||Sep 12, 1995||United Microelectronics Corporation||Mask ROM process with self-aligned ROM code implant|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US5585296 *||Feb 12, 1996||Dec 17, 1996||United Microelectronics Corporation||Method of fabricating memory cells with buried bit lines|
|US5668029 *||May 6, 1996||Sep 16, 1997||United Microelectronics Corporation||Process for fabricating multi-level read-only memory device|
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|US6133102 *||Jun 19, 1998||Oct 17, 2000||Wu; Shye-Lin||Method of fabricating double poly-gate high density multi-state flat mask ROM cells|
|US6420247 *||Apr 10, 2000||Jul 16, 2002||Motorola, Inc.||Method of forming structures on a semiconductor including doping profiles using thickness of photoresist|
|US6531365 *||Jun 22, 2001||Mar 11, 2003||International Business Machines Corporation||Anti-spacer structure for self-aligned independent gate implantation|
|US6562713||Feb 19, 2002||May 13, 2003||International Business Machines Corporation||Method of protecting semiconductor areas while exposing a gate|
|US6642147||Aug 23, 2001||Nov 4, 2003||International Business Machines Corporation||Method of making thermally stable planarizing films|
|US6649526 *||Nov 15, 2001||Nov 18, 2003||Macronix International Co., Ltd.||Method for implanting and coding a read-only memory with automatic alignment at four corners|
|US6673682 *||May 13, 2002||Jan 6, 2004||Macronix International Co. Ltd.||Methods of fabricating high density mask ROM cells|
|U.S. Classification||438/276, 257/E21.671, 438/291|
|Jul 26, 1995||AS||Assignment|
Owner name: UNITED MICROELECTRONICS CORPORATION, TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SU, KUAN-CHENG;CHUNG, CHEN-HUL;SHENG, YI-CHUNG;REEL/FRAME:007619/0229;SIGNING DATES FROM 19950705 TO 19950711
|Jan 5, 2000||FPAY||Fee payment|
Year of fee payment: 4
|Feb 4, 2004||REMI||Maintenance fee reminder mailed|
|Jul 16, 2004||LAPS||Lapse for failure to pay maintenance fees|
|Sep 14, 2004||FP||Expired due to failure to pay maintenance fee|
Effective date: 20040716