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Publication numberUS5552326 A
Publication typeGrant
Application numberUS 08/397,706
Publication dateSep 3, 1996
Filing dateMar 1, 1995
Priority dateMar 1, 1995
Fee statusPaid
Also published asUS5608254
Publication number08397706, 397706, US 5552326 A, US 5552326A, US-A-5552326, US5552326 A, US5552326A
InventorsSteven N. Frank, James F. Belcher, Charles E. Stanford, Robert A. Owen, Robert J. S. Kyle
Original AssigneeTexas Instruments Incorporated
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method for forming electrical contact to the optical coating of an infrared detector using conductive epoxy
US 5552326 A
Abstract
This is a system and method of forming an electrical contact to the optical coating of an infrared detector using conductive epoxy. The method may comprise: forming thermal isolation trenches 22 and bias contact vias 23 in a substrate 20; depositing a trench filler 24 in the thermal isolation trenches 22; depositing conductive epoxy 50 into the bias contact vias 23; replanarizing; depositing a common electrode layer 31 over the thermal isolation trenches 22 and vias 23; depositing an optical coating 26 above the common electrode layer 31; mechanically polishing a backside of the substrate 20 to expose the trench filler 24 and conductive epoxy 50; depositing a contact metal 34 on the backside of the substrate 20; etching the contact metal 34 and the trench filler 24 to form pixel mesas of the contact metal 34 and the substrate 20.
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Claims(6)
We claim:
1. A method of forming an electrical contact to a common electrode of an infrared detector using conductive epoxy, said method comprising:
forming thermal isolation trenches in a substrate;
forming bias contact vias around a periphery of said substrate;
depositing a trench filler in said thermal isolation trenches and depositing conductive epoxy in said bias contact vias;
depositing a common electrode layer on top of said substrate over said thermal isolation trenches and bias contact vias;
depositing an optical coating above said common electrode layer and said conductive epoxy;
thinning a backside of said substrate to expose said trench filler;
depositing a contact metal on said backside of said substrate;
etching said contact metal and said trench filler to form pixel mesas of said contact metal and said substrate; and
forming a bias contact with a portion of said contact metal, wherein said contact metal is electrically connected to said common electrode layer by the conductive epoxy filled bias contact via in said substrate.
2. The method of claim 1, wherein said method further includes planarizing said conductive epoxy in said bias contact vias before said common electrode is deposited.
3. The method of claim 1, wherein said depositing said conductive epoxy in said bias contact vias is before depositing said trench filler.
4. The method of claim 1, wherein said forming thermal isolation trenches and said forming bias contact vias etching include laser vaporization.
5. The method of claim 1, wherein said forming thermal isolation trenches and said forming biasing vias etching include ion milling.
6. The method of claim 1, wherein said method further includes planarizing said trench filler after depositing said trench filler.
Description
CROSS-REFERENCE TO RELATED APPLICATION

The following coassigned patent application is hereby incorporated herein by reference:

______________________________________Ser. No.      Filing Date                   TI Case No.______________________________________08/223,073    04/04/94  TI-1872608/223,087    04/04/94  TI-1784708/223,088    04/04/94  TI-18727______________________________________
CROSS-REFERENCE TO RELATED APPLICATION

The following coassigned patent application is hereby incorporated herein by reference:

______________________________________Ser. No.      Filing Date                   TI Case No.______________________________________08/223,073    04/04/94  TI-1872608/223,087    04/04/94  TI-1784708/223,088    04/04/94  TI-18727______________________________________
FIELD OF THE INVENTION

This invention generally relates to infrared (IR) detector arrays and means of fabrication.

BACKGROUND OF INVENTION

The novel IR devices and fabrication processes to be described are related to the types of IR detector arrays recorded in (1) U.S. Pat. No. 4,080,532, Hopper, March, 1978; (2) U.S. Pat. No. 4,745,278, Hanson, May, 1988; (3) U.S. Pat. No. 4,792,681, Hanson, December, 1988; (4) "LOW-COST UNCOOLED FOCAL PLANE ARRAY TECHNOLOGY", by Hanson, Beratan, Owen and Sweetser; presented Aug. 17, 1993 at the IRIS Detector Specialty Review; (5) cross-referenced patent application Ser. No. 08/223,087, filed Apr. 4, 1994, (6) cross-referenced patent application Ser. No. 08/223,088, filed Apr. 4, 1994, and (7) cross-referenced patent application Ser. No. 08/223,073, filed Apr. 4, 1994.

The physical requirements of uncooled arrays and a description of fabrication processes are covered in some detail in the above references. A line scanner may contain from several hundred to a few thousand and an area imager several thousand to tens of thousand individual picture elements (pixels.) Each of these pixels consists of a capacitor that has a heat (IR intensity) sensitive dielectric such as barium strontium titanate (BST.) The electronic connections to these capacitors are greatly simplified if one of the capacitor terminals is made common to all. Previously described in the references are methods to attach hundreds to tens of thousands of electrical connections between the other isolated terminals of the pixel capacitors and the electronic sensing circuit housed on an external integrated circuit (IC.) In addition, the pixel capacitors must be thermally isolated from each other while having one terminal connected to all the other common terminals.

The common connection to one side of the pixel capacitors consists of a front side thin film referred to as the optical coating. This may be a composite of a plurality of thin films having the desired physical properties, such as IR transparency, electrical conductivity, thermal conductivity, etc. The thicker heat sensitive dielectric substrate in this case can be barium-strontium-titanate (BST) which is a ceramic like material.

SUMMARY OF THE INVENTION

Most of the previous inventions are concerned with how to achieve thermally isolated pixels and attach them to a companion silicon integrated circuit without damage to the fragile IR sensing array circuitry. The IR sensing side of the array contains the previously mentioned optical coating. This typically consists of three or four layers. The outermost layer is a semitransparent thin metal film such as nichrome (NiCr). The underlying wavelength tuning layer has a thickness of an odd number of quarter wavelengths at the desired IR wavelength. This tuning layer is transparent to IR and may be parylene. The underlying metal completes the optical filter properties and may also be the sole electrical contact for a common electrical connection to all the pixels. Typically this layer is a thicker film of NiCr. An improved structure, such as described in the references, may have a more rugged fourth layer. Sometimes this fourth layer results in a structure referred to as an elevated optical coating.

Although much detail and many variants of the pixel isolation and connection processes are described in the references, not mentioned is the method whereby the common electrode of the optical layer is electrically connected to a voltage or current biasing supply. Heretofore this has been accomplished in a very primitive and unreliable manner by physically scraping away the top two coatings of the optical layer at the periphery of the IR sensing array and attaching a fine wire with electrically conducting epoxy.

This invention describes novel means of effecting this common electrode biasing connection in a more production worthy and reliable manner. This is a system and method of forming an electrical contact to the optical coating of an infrared detector using conductive epoxy. The method may comprise: forming thermal isolation trenches in a substrate; depositing a trench filler in the thermal isolation trenches; depositing a conductive epoxy in vias at the periphery of the substrate; replanarizing; depositing a common electrode layer over the thermal isolation trenches; depositing an optical coating above the common electrode layer; mechanically polishing a backside of the substrate to expose the trench filler; depositing a contact metal on the backside of the substrate, wherein said contact metal forms a bias contact with said conductive epoxy and said common electrode; and etching the contact metal and the trench filler to form pixel mesas of the contact metal and the substrate. This system and method may be applied to uncooled as well as cooled infrared detectors.

DESCRIPTION OF THE DRAWINGS

This invention can be best understood by reference to the following drawing(s), in which:

FIG. 1 shows a cross sectional sketch of an array after bias contact vias and thermal isolation trenches have been patterned and etched;

FIG. 2 shows a cross sectional sketch of an array after the bias contact vias have been filled with a conductive epoxy and the thermal isolation trenches have been filled with a trench filler and replanarized;

FIG. 3 shows the optical coating applied over the sensing and common biasing contact area;

FIG. 4 depicts the mechanically thinned composite array with biasing contact area and a layer of contact metal on the backside of the array;

FIG. 5 shows a cross sectional sketch of the sensing array after the trench filler has been removed;

FIG. 6 shows the final array structure after bonding to the companion IC.

Corresponding numerals and symbols in different figures refer to corresponding parts unless otherwise indicated.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

One preferred embodiment will be described with the aid of FIGS. 1-6 and TABLE 1. The figures have exaggerated layer thicknesses for descriptive purpose and are not to actual or relative scale to each other. In this embodiment, the BST substrate 20 is patterned from the front or optically sensitive side of the sensing array by the use of a laser to vaporize the substrate thereby forming thermal isolation trenches 22 between the thermally sensitive picture elements (pixels). As shown in FIG. 1, the vias 23 for the biasing contacts are formed in the same manner. These vias 23 are removed from the IR sensing area and have multiple locations around the border of the array. Although shown in these figures to be the same size as the thermal isolation trenches 22, these vias 23 may be larger if desired.

FIG. 2 exhibits the structure after several processing steps have been completed from FIG. 1. Trenches 22 have been filled with parylene 24 and the surface has been mechanically polished to planarize the front side of the IR detector. In addition, the bias contact vias have been filled with a conductive epoxy 50. The conductive epoxy may then be planarized. Of course, the order of deposition of the trench filler and conductive epoxy may be switched. Additionally, both materials may be planarized at one time after deposition.

After planarization, a three level optical coating 26 is deposited over all the pixels and bias contact vias 23 as shown in FIG. 3. The materials and thicknesses are shown in TABLE 1. The common electrode in this case is 31 and provides the functions of one side of the pixel capacitors and the electrical contact in the bias contact areas.

In FIG. 4, the substrate 20 has been thinned from the back side by mechanical polishing means to expose the parylene 24 and conductive epoxy 50.

FIG. 5 shows the array after removal of the parylene from the thermal isolation trenches. In addition, FIG. 5 shows the deposition of the back side contact metal 34 which typically consists of the alloys shown in TABLE 1. This metal 34 acts as a backside contact metal in the thermal sensing areas, as well as an bias contact metal in the bias contact areas.

After the use of standard photolithography, etching and cleaning techniques, and bumpbonding to the IC, the structure shown in FIG. 6 results. The capacitor pixel mesas 20 are defined by the optical coating 26, the thermally sensitive insulator 20 and the contact metal 34. IC bonding may now be performed to all the pixel mesas and the biasing pads. This establishes an electrical connection for the common pixel electrode bias voltage through 34 to 50 to 31. The IC elements are also described in TABLE 1.

              TABLE 1______________________________________ID#  Description   Material (dim)                          Alternates______________________________________20   Thermally sensitive              Barium stronti-substrate     um titanate22   Isolation trenches              Laser vaporized                          Ion milled23   Bias contact vias              Laser vaporized                          Ion milled24   Trench filler Parylene    Photoresist,                          PMMA, epoxy26   Optical coating              3 layered   1/4 IR wavelength28   Transparent coat              NiCr 50A    25-100 A30   1/4 wavelength              Parylene    1/4 wavelengthseparator coat              1.4 μm   at desired IR31   Electrical conduct-              NiCr 1000 A 500-2000 Aing coat34   Backside electrical              Multiple alloys                          4-layer composite ofcontact       suitable for IC                          15-60 μm In              bonding.    0.5-1.5 μm Au                          0.5-1.5 μm NiCr                          0.2-1.0 μm TiW50   Bias contact  Conductivematerial      Epoxy76   Ohmic connection              TiWfor pixels77   IC contact mesa for              Photosensitive                          PMMAsensing connection              polyimide,              Dupont 273478   IC via for sensingcircuit80   IC processor  Si or GaAs82   IC contact mesa for              Photosensitive                          PMMAbiasing connection              polyimide,              Dupont 273484   Ohmic connection              TiWfor bias connection86   IC via for biascircuit92   IC bias contact pad              Conductive              metal______________________________________

Whether the isolation trenches are formed by laser vaporization, ion milling or other means, similar trenches may be patterned at the periphery of the array at the same time. All variants and combinations of these structures are considered within the scope of this invention.

While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. It should be stressed again that the biasing vias shown in the illustrations were drawn for convenience and ease of description as if they were isolation trench type geometries. These vias are well removed from the sensing area and may be much larger or have many more to cover a more extensive area than shown in the figures. In some embodiments of these novel IR sensors, thermal isolation of the pixel capacitors is performed by partial etching from one side followed by etching to completion on the other side as has been described in the references. All of these methods can have the biasing vias patterned as a normal part of the process flow. In addition, this invention is not to be limited to uncooled infrared detectors. For example, this invention could be easily incorporated into the normal process flow for cooled infrared detectors as well.

Various modifications have already been described but other modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.

Patent Citations
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Non-Patent Citations
Reference
1J. F. Belcher et al., Texas Instr. Tech. J., 11,5(1994)27 "Uncooled Infrared Detector Processing" C. M. Hanson et al., Texas Instr. Tech. J. 11(5)(1994)2 Uncooled Thermal Imaging.
2 *J. F. Belcher et al., Texas Instr. Tech. J., 11,5(1994)27 Uncooled Infrared Detector Processing C. M. Hanson et al., Texas Instr. Tech. J. 11(5)(1994)2 Uncooled Thermal Imaging.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US5780204 *Feb 3, 1997Jul 14, 1998Advanced Micro Devices, Inc.Backside wafer polishing for improved photolithography
Classifications
U.S. Classification216/17, 438/65, 257/E21.508, 438/119, 438/66, 257/E31.125
International ClassificationH01L31/0224, H01L21/60
Cooperative ClassificationH01L2924/01022, H01L2924/10329, H01L2224/13099, H01L2924/01038, H01L2924/01033, H01L2924/01056, H01L2924/19041, H01L2924/01013, H01L24/11, H01L2924/01077, H01L31/022408, H01L2924/14, H01L2924/01079
European ClassificationH01L24/11, H01L31/0224B
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