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Publication numberUS5604458 A
Publication typeGrant
Application numberUS 08/457,445
Publication dateFeb 18, 1997
Filing dateJun 1, 1995
Priority dateFeb 5, 1993
Fee statusLapsed
Publication number08457445, 457445, US 5604458 A, US 5604458A, US-A-5604458, US5604458 A, US5604458A
InventorsGuoliang Shou, Weikang Yang, Sunao Takatori, Makoto Yamamoto
Original AssigneeYozan Inc., Sharp Corporation
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Scaler circuit
US 5604458 A
Abstract
A scalar circuit includes serially connected inverters connected to one another via a plurality of connecting lines. A plurality of input lines are provided to the input of a first inverter in the serially connected inverters. A plurality of feedback lines are provided between the input and output of each inverter. A capacitance and a switch is provided in each connecting line, input line and feedback line. The switch connects a terminal of the capacitance to ground while simultaneously disconnecting the ends of that line from one another. The switches are cooperatively actuated so that the effective composite capacitance in the feedback lines and the connecting lines are substantially equal. In addition, the composite capacitance of in the input lines and the connecting lines are substantially equal.
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Claims(2)
What is claimed is:
1. A scaler circuit comprising:
i) a plurality of input lines, each of said plurality of input lines having a first end and a second end, said first end of each of said plurality of input line being operatively connected to a same input voltage;
ii) a plurality of first capacitances, wherein one of said plurality of first capacitances is operatively provided in each of said plurality of input lines between said first end and second end thereof;
iii) a plurality of first switching devices, wherein one of said plurality of first switching devices is operatively provided in each of said plurality of input lines between said first and second end thereof and selectively connects a terminal of said first capacitance provided in that input line to ground while simultaneously disconnecting said first end from said second end of that input line;
iv) a first inverter having an input portion operatively connected to said second end of each of said plurality of input lines and an output portion;
v) a plurality of first feed back lines connected in parallel between said input portion and said output portion of said first inverter for feeding an output of said first inverter back to an input thereof, each of said plurality of first feed back lines having a first end and a second end, said first end of each of said plurality of first feed back line lines being operatively connected to said input portion of said first inverter, and said second end of each of said plurality of first feed back line lines being operatively connected to said output portion of said first inverter;
vi) a plurality of second capacitances, wherein one of said plurality of second capacitances is operatively provided in each of said plurality of first feed back lines;
vii) a plurality of second switching devices, wherein one of said plurality of second switching devices is operatively provided in each of said plurality of first feed back lines between said second capacitance provided in that first feed back line and said second end of that first feed back line and selectively connects a terminal of said second capacitance provided in that first feed back line to ground while simultaneously disconnecting said first end from said second end of that first feed back line;
viii) a plurality of connecting lines, each of said plurality of connecting lines having a first end and a second end, said first end of each of said plurality of connecting lines being operatively connected to said output portion of said first inverter;
ix) a plurality of third capacitances, wherein one of said plurality of third capacitances is operatively provided in each of said plurality of connecting lines between said first end and second end thereof;
x) a plurality of third switching devices, wherein one of said plurality of third switching devices is operatively provided in each of said plurality of connecting lines between said first end and second end thereof and selectively connects a terminal of said third capacitance provided in that connecting line to ground while simultaneously disconnecting said first end from said second end of that connecting line;
xi) a second inverter having an input portion operatively connected to said second end of each of said plurality of connecting lines and an output portion;
xii) a plurality of second feed back lines connected in parallel between said input portion and said output portion of said second inverter for feeding an output of said second inverter back to an input thereof, each of said plurality of second feed back lines having a first end and a second end, said first end of each of said plurality of second feed back line lines being operatively connected to said input portion of said second inverter, and said second end of each of said plurality of second feed back line lines being operatively connected to said output portion of said second inverter;
xiii) a plurality of fourth capacitances, wherein one of said plurality of fourth capacitances is operatively provided in each of said plurality of second feed back lines; and
xiv) a plurality of fourth switching devices, wherein one of said plurality of fourth switching devices is operatively provided in each of said plurality second feed back lines between said fourth capacitance provided in that second feed back line and said second end of that second feed back line and selectively connects a terminal of said forth capacitance provided in that second feed back line to ground while simultaneously disconnecting said first end from said second end of that second feed back line,
wherein each switching device in said plurality of second, third and fourth switching devices is cooperatively switched with other switching devices in said plurality of second, third and fourth switching devices so that an effective composite capacitance of said plurality of second capacitances, third capacitances and fourth capacitances becomes substantially equal, and wherein a sum of said plurality of first capacitances is substantially equal to a sum of said plurality of third capacitances.
2. A scaler circuit according to claim 1, wherein said first inverter and said second inverter each comprise a plurality of inverting elements.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation-in-part of U.S. patent application No. 08/191,495 filed Feb. 4, 1994 now U.S. Pat. No. 5,457,417.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a scaler circuit.

2. Description of the Art

In recent years, concerns have been raised about the limitations of a digital computer because of the exponential increase in the amount of money required for investments in equipment concerning a fine processing technology. Here, an analog computer is raising attention. Inventors have developed a weighted summing circuit by capacitive coupling parallelly connecting a plural number of capacitances in analog computer that realizes a multiplication circuit. However, the range of output does not fit the range of an input necessary, and a greater level of control of the output is needed. Conventionally, a circuit realizing highly accurate variable level control is not known.

SUMMARY OF THE INVENTION

The present invention solves the conventional problems and provides a highly accurate variable level control and a scaler circuit deleting offsetting influences.

A scaler circuit according to the present invention serially connects an inverter including a feed back capacitance, performs multiplication based on a proportion of an input capacitance and the first feed back capacitance and deletes offsets of the first inverter and the second inverter.

Other objects, features, and characteristics of the present invention as well as the methods of operation and functions of the related elements of structure, and the combination of parts and economies of manufacture, will become more apparent upon consideration of the following description and the appended claimed with reference to the accompanying drawings, all of which form a part of this specification, wherein like reference numerals designate corresponding parts in the various figures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a circuit according to a first embodiment of the present invention; and

FIG. 2 is a schematic diagram of a second embodiment of the present invention.

PREFERRED EMBODIMENT OF THE PRESENT INVENTION

Hereinafter an embodiment according to the present invention is described with reference the attached drawings.

In FIG. 1, a scaler circuit serially connects a first stage coupling capacitance CP1, a first stage inverter INV1, a second coupling capacitance CP2 and a second stage inverter INV2 with an input voltage Vin.

CP1 includes a plurality of parallel connected input lines L11, L12, L13 and L14 including capacitances C11, C12, C13 and C14. Capacitances C12, C13 and C14 are selectively connected with input lines L12, L13, L14 or ground by selector switches SW11, SW12 and SW13.

A composite capacitance of C11, C12, C13 and C14 is (C11 +C12 +C13 +C14) and the coupling capacitance connecting Vin to INV1, which is shown as an effective composite capacity below, is (C11 +ΣC1i). ΣC1i is the composite capacitance of capacitance C1i connected with an input line side by SW1i.

A plurality of feed back lines L21, L22, L23 and L24 feed back the output of INV1 to an input thereof. Capacitances C21, C22, C23 and C24 are established at L21, L22, L23 and L24. C22, C23 and C24 are selectively connected to feed back lines L22, L23, L24 or ground by selector switches SW21, SW22, SW23 and SW24.

A composite capacitance of C21, C22, C23 and C24 is (C21 +C22 +C23 +C24) and a coupling capacitance connecting an output and an input of INV1, which is shown by effective composite capacity, is (C21 +ΣC2i). ΣC2i is the composite capacitance C2i connected at a side of feed back line by SW2i.

CP2 is composed of a plurality of parallel connecting lines L31, L32, L33 and L34 including capacitances C31, C32, C33 and C34. C32, C33 and C34 are selectively connected with connecting lines L32, L33, L34 or ground by selector switches SW31, SW32 and SW33. A composite capacitance of C31, C32, C33 and C34 is (C31 +C32 +C33 +C34) and a coupling capacitance, which is shown by effective composite capacity, connecting INV1 and INV2 is (C31 +ΣC3i). ΣC3i is a composite capacitance C3i connected at a connecting line side by SW3i.

At INV2, a plurality of feed back lines L41, L42, L43 and L44 feed back the output of INV2 to an input thereof. At L41, L42, L43 and L44, capacitances C41, C42, C43 and C44 are established. C42, C43 and C44 are selectively connected with feed back lines L42, L43, L444 or ground by selector switches SW41, SW42, SW43. A composite capacitance of C41, C42, C43 and C44 is (C41 +C42 +C43 +C44) and a coupling capacitance C41, C42, C43 and C44, which is shown by effective composite capacity, connecting an output of INV2 and input of INV2 becomes (C41 +ΣC4i). ΣC4i is a composite capacitance C4i connected at feed back line side by SW4i.

INV1 and INV2 have a large enough gain to guarantee a linear characteristic between the input and output relations and to generate a result which corresponds to Vin multiplied by a proportion of the effective composite capacitance as expressed in Formula 1.

m=(C11 +ΣC1i)/(C21 +ΣC2i)  (1)

The proportion m can be controlled by switching SW11 to SW13 and SW21 to SW23. Because the accuracy of the circuit is given by the accuracy of the capacitance, which rate is not an absolute value, it easy to keep a relatively high accuracy in the LSI process.

With respect to CP2 and INV2, the capacitances therein are set according to formula (2).

C21 ═C31 ═C41, C22 ═C32 ═C42, C23 ═C33 ═C43, C24 ═C34 ═C44(2)

A group of switches SW21, SW31 and SW41, a group of switches SW22, SW32 and SW42, a group of switches SW23, SW33 and SW43 and a group of switches SW24, SW34 and SW44 successively switch.

Always, a relation expressed in formula (3) is guaranteed.

(C21 +ΣC2i)=(C31 +ΣC3i)=(C41 +ΣC4i)                                         (3)

Furthermore, formula (4) is set as follows.

(C11 +C12 +C13 +C14)=(C31 +C32 +C33 +C34)                                                (4)

If every offset voltage at the input side of INV1 and INV2 is Voff, a relation of input and output voltage Vin and Vout is calculated. Output voltage of INV1 is defined as V11.

From formulas (5) and (6), formula (7) is obtained. ##EQU1## From the relation of formulas (2) to (4), formula (8) is obtained, and offset is deleted. ##EQU2## The supposition mentioned above, i.e., that offset is equal at INV1 and INV2, is known and the similarity between INV1 and INV2 is comparatively good.

As mentioned above, a scaler circuit relating to the present invention serially connects an inverter including a feed back capacitance, performs multiplication based on a proportion of an input capacitance and the first feed back capacitance and deletes offsets of the first inverter and the second inverter so that it has an effective result of realizing a highly accurate variable level control and provides a scaler circuit deleting offset influences.

FIG. 2 illustrates a scaler circuit according to a second embodiment of the present invention. The circuit in FIG. 2 is similar in function to that discussed above with respect to FIG. 1. However, because the location of the switches and capacitors in the feedback loops are reversed in FIG. 2 as compared to FIG. 1, the capacitances do not need to be refreshed.

While the invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not to be limited to the disclosed embodiment, but on the contrary is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
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Non-Patent Citations
Reference
1Dorf, "The Electrical Engineering Handbook," pp. 1861-1865, CRC Press Inc., 1993.
2 *Dorf, The Electrical Engineering Handbook, pp. 1861 1865, CRC Press Inc., 1993.
3Masry, "Strays-Insensitive State-Space Switched-Capacitor Filters," IEEE Transactions on Circuits and Systems, vol. Cas-30, No. 7, Jul. 1983.
4 *Masry, Strays Insensitive State Space Switched Capacitor Filters, IEEE Transactions on Circuits and Systems, vol. Cas 30, No. 7, Jul. 1983.
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6 *Miyazaki, The Analog Usage Handbook, pp. 139 140, CQ Shuppan Kabushiki Kaisha, 1992.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US5936463 *May 20, 1997Aug 10, 1999Yozan Inc.Inverted amplifying circuit
US7656226 *Mar 31, 2006Feb 2, 2010Intel CorporationSwitched capacitor equalizer with offset voltage cancelling
EP0936748A2 *Feb 10, 1999Aug 18, 1999Yozan Inc.Matched filter bank CDMA communication
Classifications
U.S. Classification327/356
International ClassificationH03G1/00, G06G7/12, G06J1/00
Cooperative ClassificationG06J1/00, G06G7/12, H03G1/0094
European ClassificationH03G1/00B8S, G06J1/00, G06G7/12
Legal Events
DateCodeEventDescription
Apr 12, 2005FPExpired due to failure to pay maintenance fee
Effective date: 20050218
Feb 18, 2005LAPSLapse for failure to pay maintenance fees
Sep 8, 2004REMIMaintenance fee reminder mailed
Dec 10, 2002ASAssignment
Owner name: YOZAN INC., JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:YOZAN, INC. BY CHANGE OF NAME:TAKATORI EDUCATIONAL SOCIETY,INC.;REEL/FRAME:013552/0457
Effective date: 20021125
Owner name: YOZAN INC. 3-5-18 KITAZAWA 3-CHOMESETAGAYA-KU, TOK
Owner name: YOZAN INC. 3-5-18 KITAZAWA 3-CHOMESETAGAYA-KU, TOK
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:YOZAN, INC. BY CHANGE OF NAME:TAKATORI EDUCATIONAL SOCIETY,INC.;REEL/FRAME:013552/0457
Effective date: 20021125
Aug 4, 2000FPAYFee payment
Year of fee payment: 4
Aug 7, 1995ASAssignment
Owner name: SHARP CORPORATION, JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SHOU, GUOLIANG;YANG, WEIKANG;TAKATORI, SUNAO;AND OTHERS;REEL/FRAME:007620/0767
Effective date: 19950724
Owner name: YOZAN INC., JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SHOU, GUOLIANG;YANG, WEIKANG;TAKATORI, SUNAO;AND OTHERS;REEL/FRAME:007620/0767
Effective date: 19950724