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Publication numberUS5640035 A
Publication typeGrant
Application numberUS 08/555,550
Publication dateJun 17, 1997
Filing dateNov 9, 1995
Priority dateApr 14, 1992
Fee statusLapsed
Publication number08555550, 555550, US 5640035 A, US 5640035A, US-A-5640035, US5640035 A, US5640035A
InventorsAkira Sudo, Toshiharu Watanabe
Original AssigneeKabushiki Kaisha Toshiba
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
MOSFET having improved driving performance
US 5640035 A
Abstract
A gate oxide film is formed on the surface of a P-type silicon substrate. A gate electrode is formed on the gate oxide film. Phosphorus is ion-implanted into the P-type silicon substrate, using the gate electrode as a mask. Thus, N- -type layers of LDD regions are formed in the P-type silicon substrate. Sidewall regions of material having a high dielectric constant are formed on both sides of the gate electrode. The P-type silicon substrate is etched downward adjacent to both the sidewall regions. N+ -type layers of source and drain regions are formed in the etched surface of the P-type silicon substrate.
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Claims(9)
What is claimed is:
1. A semiconductor device comprising:
a semiconductor substrate having a surface with a first surface portion at a first level and a second surface portion at a second level:
an insulating layer formed only on said first surface portion of said semiconductor substrate;
a gate electrode formed on an upper surface of said insulating layer;
first sidewall spacers, each first sidewall spacer having a side portion contacting a sidewall of said gate electrode and a base portion contacting said upper surface of said insulating layer;
source and drain regions formed in said second surface portion of said semiconductor substrate;
first and second impurity regions formed in said first surface portion of said semiconductor substrate, said first impurity region being adjacent to said source region and having an impurity concentration lower than an impurity concentration of said source region, and said second impurity region being adjacent to said drain region and having an impurity concentration lower than an impurity concentration of said drain region; and
second sidewall spacers, each second sidewall spacer having a side portion contacting a step portion between said first and second surface portions of said semiconductor substrate, a base portion contacting a corresponding one of said source and drain regions, and an upper portion extending from said base portion, wherein a width of each second sidewall spacer is greater at said base portion than at said upper portion.
2. A semiconductor device comprising:
a semiconductor substrate having a surface with a first surface portion at a first level and a second surface portion at a second level;
an insulating layer formed only on said first surface portion of said semiconductor substrate;
a gate electrode formed on an upper surface of said insulating layer;
first sidewall spacers, each first sidewall spacer having a side portion contacting a sidewall of said gate electrode and a base portion contacting said upper surface of said insulating layer;
source and drain regions formed in said second surface portion of said semiconductor substrate;
first and second impurity regions formed in said first surface portion of said semiconductor substrate, said first impurity region being adjacent to said source region and having an impurity concentration lower than an impurity concentration of said source region, and said second impurity region being adjacent to said drain region and having an impurity concentration lower than an impurity concentration of said drain region;
second sidewall spacers, each second sidewall spacer having a side portion contacting a step portion between said first and second surface portions of said semiconductor substrate, a base portion contacting a corresponding one of said source and drain regions, and an upper portion extending from said base portion, wherein a width of each second sidewall spacer is greater at said base portion than at said upper portion; and
a silicide layer formed on each of said source and drain regions and contacting each of said second sidewall spacers.
3. The semiconductor device according to claim 2, wherein the width of each of said second sidewall spacers increases from said upper portion to said base portion.
4. The semiconductor device according to claim 3, wherein the second sidewall spacers are formed of a material having a high dielectric constant.
5. A semiconductor device comprising:
a semiconductor substrate;
source and drain regions located in said semiconductor substrate, an upper surface of each of said source and drain regions being lower in level than a surface of said semiconductor substrate;
a gate insulating layer located only on said surface of said semiconductor substrate between said source and drain regions;
a gate electrode located above said gate insulating film;
first and second corner portions each defined by said gate electrode and said gate insulating layer;
first sidewall spacers located in said first and second corner portions, respectively, on opposite sides of said gate electrode;
first and second impurity regions provided in the semiconductor substrate, said first impurity region being adjacent to said source region and having an impurity concentration lower than an impurity concentration of said source region, and said second impurity region being adjacent to said drain region and having an impurity concentration lower than an impurity concentration of said drain region;
third and fourth corner portions, said third corner portion defined by said upper surface of said source region and a side surface of said first impurity region and said fourth corner portion defined by said upper surface of said drain region and a side surface of said second impurity region;
second sidewall spacers located in said third and fourth corner portions, respectively, wherein said second sidewall spacers have base portions on said surfaces of said source and drain regions and upper portions extending from said base portions, wherein a width of each second sidewall spacer is greater at said base portion than at said upper portion; and
a silicide layer formed on each of said source and drain regions and contacting each of said second sidewall spacers.
6. The semiconductor device according to claim 5, wherein a distance between said second sidewall spacers is greater than a distance between said first sidewall spacers.
7. The semiconductor device according to claim 6, wherein the width of each of said second sidewall spacers increases from said upper portion to said base portion.
8. The semiconductor device according to claim 7, wherein the second sidewall spacers are formed of a material having a high dielectric constant.
9. The semiconductor device according to claims 8, wherein the first sidewall spacers are formed of said material having a high dielectric constant.
Description

This application is a continuation of application Ser. No. 08/348,950, filed Nov. 25, 1994, now abandoned, which is a continuation of application Ser. No. 08/045,732, filed Apr. 14, 1993, now abandoned.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a method for manufacturing the same and, more specifically, a MOSFET and a method for manufacturing the same.

2. Description of the Related Art

First a conventional LDD (lightly doped drain) transistor will be described. A gate oxide film is formed on the surface of a P-type silicon substrate, a gate electrode is formed on the gate oxide film, and sidewalls of SiO2 are formed on both sides of the gate electrode by CVD (chemical vapor deposition). Ions are implanted into an LDD region, using the gate electrode as a mask, to form an N- -type layer in the P-type silicon substrate, and ions are implanted into a source/drain region, using the gate electrode and the sidewalls as masks, to form an N+ -type layer in the P-type silicon substrate.

In the LDD transistor, even though a high voltage is applied to the drain side, a drain electric field is mitigated by the N- -type layer of the LDD region. Therefore, impact ionization is suppressed in the vicinity of the drain region, and hot carriers are reduced, resulting in high reliability of the transistor.

Since, in the LDD transistor described above, the ion concentration of the N- -type layer of the LDD region is low, the parasitic resistance is higher than that of a normal transistor, with the result that the LDD transistor deteriorates in driving performance. In order to prevent the driving performance from deteriorating, an LDD transistor having sidewalls formed of materials having a high dielectric constant, such as SiN, is proposed.

In the conventional LDD transistor, the electric field of the surface of the N- -type layer is strengthened by the sidewalls formed of materials having a high dielectric constant. The concentration of electrons of the N- -type layer is increased, and the parasitic resistance thereof is lowered. In this case, however, a gate fringing electric field is increased, and a large gate parasitic capacitance is generated between the gate electrode and the N+ -type layer of the source/drain region, thereby causing a drawback wherein the driving performance of the transistor is decreased and the power consumption thereof is increased.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a semiconductor device and a method for manufacturing the same which includes an LDD transistor whose sidewalls are formed of materials having a high dielectric constant to reduce the parasitic resistance of an N- -type layer of an LDD region but enable the gate parasitic capacitance between a gate electrode and a source/drain region to be decreased, thereby improving the driving performance of the transistor and lowering the power consumption thereof.

The above object is attained by the following constitution.

According to one aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising:

a first step of forming a gate electrode above a surface of a semiconductor substrate;

a second step of forming sidewall regions on both sides of the gate electrode;

a third step of downwardly etching the semiconductor substrate adjacent to both the sidewall regions; and

a fourth step of forming source and drain regions in the etched surface of the semiconductor substrate.

According to another aspect of the present invention, there is provided a semiconductor device comprising:

a gate electrode formed above a surface of a semiconductor substrate;

sidewall regions formed on both sides of the gate electrode;

step portions formed in the semiconductor substrate by downwardly etching the semiconductor substrate adjacent to both the sidewall regions; and

source and drain regions formed in the etched surface of the semiconductor substrate.

Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.

FIG. 1 is a cross-sectional view showing a step in methods for manufacturing a semiconductor device according to first to third embodiments of the present invention;

FIG. 2 is a cross-sectional view showing a step subsequent to the step shown in FIG. 1 in the manufacturing methods according to first to third embodiments of the present invention;

FIG. 3 is a cross-sectional view showing a step subsequent to the step shown in FIG. 2 in the manufacturing methods according to first to third embodiments of the present invention;

FIG. 4 is a cross-sectional view showing a step subsequent to the step shown in FIG. 3 in the manufacturing methods according to the first and third embodiments of the present invention;

FIG. 5 is a cross-sectional view showing a step subsequent to the step shown in FIG. 4 in the manufacturing method according to the first embodiment of the present invention;

FIG. 6 is a cross-sectional view showing a step subsequent to the steps shown in FIGS. 5 and 8 in the manufacturing methods according to the first and second embodiments of the present invention;

FIG. 7 is a cross-sectional view showing a step subsequent to the step shown in FIG. 3 in the manufacturing method according to the second embodiment of the present invention;

FIG. 8 is a cross-sectional view showing a step subsequent to the step shown in FIG. 7 in the manufacturing method according to the second embodiment of the present invention;

FIG. 9 is a cross-sectional view showing a step subsequent to the step shown in FIG. 4 in the manufacturing method according to the third embodiment of the present invention; and

FIG. 10 is a cross-sectional view showing a step subsequent to the step shown in FIG. 9 in the manufacturing method according to the third embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention will now be described, with reference to the accompanying drawings.

FIGS. 1 to 6 are cross-sectional views showing a method for manufacturing a semiconductor device according to the first embodiments of the present invention.

As shown in FIG. 1, a gate oxide film 2 having a thickness of about 100 Å is formed on the surface of a P-type silicon substrate 1 by thermal oxidation. A polysilicon layer is deposited on the surface of the gate oxide film 2 and etched using a photoetching method, with the result that a gate electrode 3 is formed on the gate oxide film 2.

As shown in FIG. 2, phosphorus is ion-implanted into the P-type silicon substrate 1 at a dose of 51013 cm-2, using the gate electrode 3 as a mask, to form N- -type layers 11 and 12 of LDD regions in the P-type silicon substrate 1.

After that, as shown in FIG. 3, an insulation layer of Si3 N4 having a thickness of about 1000 Å and a dielectric constant is deposited on the gate electrode 3 and the gate oxide film 2. The dielectric constant of the insulation layer is higher than that of the gate oxide film 2. Then, the insulation layer is etched anisotropically by RIE (Reactive Ion Etching) to form sidewall regions 13 of Si3 N4 on both sides of the gate electrode 3.

As shown in FIG. 4, the gate oxide film 2 and the P-type silicon substrate 1 are etched anisotropically by the RIE by 0.1 μm, using the sidewall regions 13 and gate electrode 3 as masks.

After that, as shown in FIG. 5, arsenic is ion-implanted into the P-type silicon substrate 1 at a dose of 51015 cm-2, using the sidewall regions 13 and gate electrode 3 as masks, to form N+ -type layers 14 and 15 of source and drain regions therein.

Next, as shown in FIG. 6, for example, titanium is deposited on the gate electrode 3 and the N+ -type layers 14 and 15. Then, the P-type silicon substrate 1 is thermally treated to form a titanium silicide layer 18 on the gate electrode 3 and N+ -type layers 14 and 15.

According to the first embodiment, since the P-type silicon substrate 1 is etched downwardly at both the sidewall regions 13, a distance between the gate electrode 3 and each of the source and drain regions can be lengthened. For this reason, gate parasitic capacitances 16 and 17 between the gate electrode 3 and the source and drain regions can be decreased even though the N- -type layers 11 and 12 of LDD regions can be reduced using a material having a high dielectric constant for the sidewall regions 13. Therefore, the driving performance of the LDD transistor can be improved and the power consumption thereof can be lowered.

Since the titanium silicide layer 18 is formed on the gate electrode 3 and the N+ -type layers 14 and 15, the parasitic resistances of the gate electrode 3 and N+ -type layers 14 and 15 can be reduced.

FIGS. 1 to 3 and 6 to 8 are cross-sectional views showing a method for manufacturing a semiconductor device according to the second embodiment of the present invention. The same structural elements as those of the first embodiment are denoted by the same reference numerals, and their descriptions are omitted.

As shown in FIG. 3, sidewall regions 13 of Si3 N4 are formed on both sides of a gate electrode 3.

Next, as shown in FIG. 7, arsenic is ion-implanted into a P-type silicon substrate 1 at a dose of 51015 cm-2, using the sidewall regions 13 and gate electrode 3 as masks, to form N+ -type layers 14 and 15 of source and drain regions therein.

Thereafter, as shown in FIG. 8, the P-type silicon substrate 1 and gate oxide film 2 are anisotropically etched by the RIE by 0.1 μm, using the sidewall regions 13 and gate electrode 3 as masks.

Next, as shown in FIG. 6, a titanium silicide layer 18 is formed on the gate electrode 3 and N+ -type layers 14 and 15.

The same advantage as that of the first embodiment can be obtained from the second embodiment.

FIGS. 1 to 4, 9 and 10 are cross-sectional views showing a method for manufacturing a semiconductor device according to the third embodiment of the present invention. The same structural elements as those of the first embodiment are denoted by the same reference numerals, and their descriptions are omitted.

As shown in FIG. 3, first sidewall regions 13 of Si3 N4 are formed on both sides of gate electrode 3.

After that, as shown in FIG. 4, a P-type silicon substrate 1 and a gate oxide film 2 are anisotropically etched by the RIE by 0.1 μm, using the first sidewall regions 13 and gate electrode 3 as masks. As a result, step portions 1a are formed in the P-type silicon substrate 1.

As shown in FIG. 9, an insulation layer of Si3 N4 having a high dielectric constant is deposited on the P-type silicon substrate 1 and gate electrode 3, and then etched anisotropically by the RIE, with the result that second sidewall regions 19 of Si3 N4 are formed on the step portions 1a. Then, arsenic is ion-implanted into the P-type silicon substrate 1 at a dose of 51015 cm-2, using the first and second sidewall regions 13 and 19 and gate electrode 3 as masks, to form N+ -type layers 14 and 15 of source and drain regions therein.

After that, as shown in FIG. 10, a titanium silicide layer 18 is formed on the gate electrode 3 and N+ -type layers 14 and 15. The second sidewall regions 13 and 19 include base portions on the surfaces of the N+ layers 14 and 15 and upper portions extending from the base portions. The width of each of the second sidewall regions 13 and 19 is greater at the base portion than at the upper portion, and particularly the width of each the second sidewall region increases from the upper portions to the base portions.

The same advantage as that of the first embodiment can be obtained from the third embodiment. Since, moreover, the arsenic is ion-implanted into the P-type silicon substrate 1 using the first and second sidewall regions 13 and 19 and the gate electrode 3 as masks, a distance between the N+ -type layers 14 and 15 formed on the P-type silicon substrate 1 can be lengthened. Therefore, in the LDD transistor, a punch through phenomenon can be prevented from appearing.

More specifically, if the N+ -type layers 14 and 15 are formed deeply in the P-type silicon substrate 1, since the impurity concentrations of these layers in the deep position are low, a depletion layer is easy to extend on the substrate 1 when the transistor is operated, with the result that the punch through phenomenon easily appears. If, however, the distance between the N+ -type layers 14 and 15 is lengthened, no punch through phenomenon appears, though the depletion layer extends.

Furthermore, when the gate oxide film 2 and the P-type silicon substrate 1 are etched downward, the substrate 1 in an element isolation region (not shown) is also etched downward, with the result that an element isolation withstanding voltage may decrease. Since, however, the sidewall regions (not shown) are formed on the step portions (not shown) of the P-type silicon substrate 1, the element isolation withstanding voltage can be prevented from decreasing.

Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details, representative devices, and illustrated examples shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.

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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US5801427 *Jun 11, 1997Sep 1, 1998Mitsubishi Denki Kabushiki KaishaSemiconductor device having a polycide structure
US5814861 *Oct 17, 1996Sep 29, 1998Mitsubishi Semiconductor America, Inc.Symmetrical vertical lightly doped drain transistor and method of forming the same
US5834810 *Oct 17, 1996Nov 10, 1998Mitsubishi Semiconductor America, Inc.Asymmetrical vertical lightly doped drain transistor and method of forming the same
US5932912 *Oct 7, 1997Aug 3, 1999Mitsubishi Denki Kabushiki KaishaSemiconductor device having LDD structure with a recess in the source/drain region which is formed during the removal of a damaged layer
US6071825 *Dec 4, 1997Jun 6, 2000Interuniversitaire Microelektronica Centrum (Imec Vzw)Fully overlapped nitride-etch defined device and processing sequence
US6162669 *Apr 9, 1999Dec 19, 2000Mitsubishi Denki Kabushiki KaishaMethod of manufacturing a semiconductor device having an LDD structure with a recess in the source/drain region formed during removal of a damaged layer
US6812103 *Jun 20, 2002Nov 2, 2004Micron Technology, Inc.Methods of fabricating a dielectric plug in MOSFETS to suppress short-channel effects
US6977419 *Sep 1, 2004Dec 20, 2005Micron Technology, Inc.MOSFETs including a dielectric plug to suppress short-channel effects
US7154146Nov 18, 2005Dec 26, 2006Micron Technology, Inc.Dielectric plug in mosfets to suppress short-channel effects
US7301193Jan 22, 2004Nov 27, 2007Spansion LlcStructure and method for low Vss resistance and reduced DIBL in a floating gate memory cell
US8258035 *May 4, 2007Sep 4, 2012Freescale Semiconductor, Inc.Method to improve source/drain parasitics in vertical devices
US20050035408 *Sep 1, 2004Feb 17, 2005Micron Technology, Inc.Methods of fabricating a dielectric plug in MOSFETs to suppress short-channel effects
CN100552897CDec 17, 2004Oct 21, 2009斯班逊有限公司Floating gate memory cell on substrate and its manufacture method
WO2005074018A1 *Dec 17, 2004Aug 11, 2005Kuo-Tung ChangStructure and method for low vss resisitance and reduced dibl in a floating gate memory cell
Classifications
U.S. Classification257/344, 257/336, 257/E29.267, 257/E21.431, 257/384, 257/413, 257/340, 257/408
International ClassificationH01L21/336, H01L29/78
Cooperative ClassificationH01L29/66636, H01L29/7834
European ClassificationH01L29/66M6T6F11E, H01L29/78F2
Legal Events
DateCodeEventDescription
Sep 28, 2000FPAYFee payment
Year of fee payment: 4
Feb 20, 2004ASAssignment
Feb 25, 2004ASAssignment
Owner name: VISHAY INFRARED COMPONENTS, CALIFORNIA
Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE AND ASSIGNEE ADDRESS PREVIOUSLY RECORDED AT REEL 014363 FRAME 0081. THE ASSIGNOR HEREBY CONFIRMS THE ASSIGNMENT OF THE ENTIRE INTEREST;ASSIGNOR:INFINEON TECHNOLOGIES NORTH AMERICA CORP.;REEL/FRAME:014373/0348
Effective date: 19990805
Sep 27, 2004FPAYFee payment
Year of fee payment: 8
Dec 22, 2008REMIMaintenance fee reminder mailed
Jun 17, 2009LAPSLapse for failure to pay maintenance fees
Aug 4, 2009FPExpired due to failure to pay maintenance fee
Effective date: 20090617