|Publication number||US5657208 A|
|Application number||US 08/508,731|
|Publication date||Aug 12, 1997|
|Filing date||Jul 28, 1995|
|Priority date||Jul 28, 1995|
|Also published as||DE19627663A1, DE19627663C2|
|Publication number||08508731, 508731, US 5657208 A, US 5657208A, US-A-5657208, US5657208 A, US5657208A|
|Inventors||Terry Noe, Leonard Weber|
|Original Assignee||Hewlett-Packard Company|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (2), Referenced by (13), Classifications (26), Legal Events (7)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention is related to printed circuit board design and manufacturing, in particular reliably interconnecting circuits implemented on printed circuit board substrates having different thermal coefficients of expansion.
For most RF and microwave circuits, only a portion needs to be implemented on a high performance printed circuit board substrate. These high performance substrates are expensive and difficult to process. For economic reasons, board designers prefer to implement as much of the circuit as practical on an inexpensive, easy-to-process substrate and use the high performance substrates only where needed to achieve RF or microwave operation.
As shown in FIG. 1, in one prior art example, the inexpensive substrate, or motherboard 1, has a hole 2 that is slightly larger in area than the high performance substrate, or daughterboard 3. The daughterboard 3 is seated within the hole 2, and the boards 1 and 3 are clamped together with a cast metal shield 4. Signals are routed from one to another with axial lead capacitors 5 which are soldered between the boards 1 and 3. This is not a cost-effective manufacturing process due to the need for the shield 4 and the manual labor required for assembly. The hole 2 also weakens the structural integrity of the motherboard 1. The characteristic impedance of the signal leads 5 is difficult to control. Furthermore, there is poor ground continuity between the motherboard 1 and the daughterboard 3.
FIG. 2 shows another prior art example in which solder paste 6 is manually applied to a motherboard 1 and a daughterboard 3 having substrates with matched thermal coefficients of expansion. In addition to increased manufacturing costs, the connections are prone to bridging because the solder is not shielded from overflow. Furthermore, self-registration of the daughterboard 3 to the motherboard 1 is not possible because there are no contact pads to aid alignment.
Moreover, the solder connections shown in FIG. 2 are provided primarily for ground plane and mechanical interconnection of the motherboard 1 and daughterboard 3. Consequently, these solder connections are few and large, and stress is concentrated at these solder connections. Therefore, if the motherboard 1 and daughterboard 3 were characterized by different thermal coefficients of expansion, the solder connections would be subject to failure when exposed to temperature variations. Accordingly, the prior art example shown in FIG. 2 is not readily susceptible to implementation of an RF or microwave circuit in which printed circuit board substrates having different thermal coefficients of expansion are used.
An efficient printed circuit board design methodology that promotes modular board design while accounting for the daughterboard as a design component is desirable. Also, any difference in the thermal coefficient of expansion for the substrate of the daughterboard with respect to the substrate of the motherboard should not affect the reliability of connections between the boards. The resulting board should also be easy and economical to manufacture.
A hybrid printed circuit board comprising two substrates having different thermal coefficients of expansion can be manufactured using automated surface mount techniques. A motherboard, consisting of an inexpensive material, is configured with a set of contact pads on its top surface. A daughterboard, having a corresponding pattern of contact pads on its bottom surface, is attached to the motherboard using standard automated surface mount techniques so that the contact pads on the daughterboard and motherboard are in proper registration.
The contact pads may be connected to signal traces. Alternatively, the contact pads on the motherboard can be connected to a ground plane contained within the motherboard. In addition to design flexibility, there is good ground continuity which improves the quality of interconnects. The characteristic impedance of the interconnects can be controlled by determining the size of stubs underlying the contact pads. This design methodology promotes modular design of printed circuit boards such that attaching different daughterboards customizes the functionality associated with the motherboard.
FIG. 1 illustrates a daughterboard positioned within a hole in a motherboard (prior art).
FIG. 2 illustrates a daughterboard connected along the perimeter to the motherboard (prior art).
FIG. 3 shows an isometric view of a hybrid printed circuit board in accordance with one embodiment of the invention.
FIG. 4 illustrates a cross-sectional view of the hybrid printed circuit board shown in FIG. 3.
FIG. 5 shows an alternate embodiment of the hybrid printed circuit board in accordance with the invention.
FIG. 6, comprising FIGS. 6A and 6B, shows an interconnect and the electrical circuit equivalent of the interconnect.
FIG. 3 shows a planar view of a hybrid printed circuit board 10 in accordance with one embodiment of the invention. A motherboard 12 has an array of contact pads 12A in a predetermined pattern on a top surface 12B. A daughterboard 14 has an array of contact pads 14A in the identical pattern on a bottom surface 14B. The daughterboard 14 can have passive or active components, such as a resistor 11A and amplifier 11B, mounted thereon. Solder compound 16 is preferably applied to the contact pads 12A on the motherboard 12. Alternatively, solder compound can be applied to the contact pads 14A on the daughterboard 14.
The motherboard 12 is typically an inexpensive printed circuit board material, such as a six-layer laminate of Getek manufactured by General Electric. When the substrate thickness of the motherboard 12 is 0.056" (0.142 cm), the associated thermal coefficient of expansion in the plane of the motherboard consisting of this material is 12-14 ppm/°C. The daughterboard 14 is formed of a high-performance substrate, such as Arlon CuClad 250. When the substrate of the daughterboard 14 is 0.060" (0.152 cm) thick, the associated thermal coefficient of expansion in the plane of the daughterboard consisting of this material is 9-10 ppm/°C. The first and second arrays of contact pads 12A, 14A are electrically conductive material, such as gold or copper traces plated with solder. The daughterboard 14 is attached to the motherboard 12 using standard automated surface mount techniques.
In this embodiment, solder compound 16 is stenciled to the motherboard 12 for attachment of the daughterboard 14 and additional components (not shown). Next, the components and daughterboard 14 are loaded on to the motherboard 12 using a pick-and-place machine, such as a Fuji IP-II. The contact pads 14A of the daughterboard 14 align with the contact pads 12A of the motherboard 12 so that there is self-registration of the daughterboard to the motherboard. The solder compound 16 is then reflowed to ensure the attachment of the components and daughterboard 14 to the motherboard 12. Since there are a plurality of contact pads 12A, 14A in the predetermined pattern over the surface 12B of the motherboard 12 and the surface 14B of the daughterboard 14, stress forces due to the difference in thermal coefficients of expansion of the substrates of the motherboard and daughterboard are distributed over a number of solder connections spaced throughout the interface between the boards. This provides higher reliability than provided by the prior art example shown in FIG. 2.
The resulting hybrid printed circuit board 10 promotes an efficient modular printed circuit board design that accounts for the daughterboard 14 as a design component. The motherboard 12 may be designed flexibly such that the daughterboard 14 with the components 11A, 11B customizes the functionality associated with the motherboard. The resulting hybrid circuit board 10 is also easy to manufacture.
FIG. 4 illustrates a cross-sectional view of the hybrid printed circuit board 10. Contact pads 14A can be positioned anywhere on the bottom surface 14B of the daughterboard 14. The contact pads 12A, 14A of the motherboard 12 and daughterboard 14 may be connected to signal traces 13 or to a ground plane 15 contained within the motherboard. The components 11A, 11B shown in FIG. 1 are in turn connected to the signal traces 13 on the daughterboard 14. Electrical connections between the contact pads 12A, 14A and signal traces 13 and between the contact pads and the ground plane 15 are provided by interconnects 17. The interconnects 17 can be plated through-holes. In addition to design flexibility, there is good ground continuity which improves the quality of the interconnections by controlling the characteristic impedance of the interconnects 17. This design methodology promotes modular design of printed circuit boards such that attaching the daughterboard 14 customizes the functionality associated with the motherboard 12.
FIG. 5 illustrates another embodiment of a hybrid printed circuit board 10'. An optional second daughterboard 18 or component (not shown) may be positioned on top of the daughterboard 14. The daughterboard 14 and the optional board 18 are attached using the solder compound and standard automated surface mount technique described earlier prior to the attachment of the daughterboard 14 to the motherboard 12.
FIGS. 6A and 6B show a preferred interconnect 17 and an equivalent circuit model therefor. FIG. 6A is an illustration of the interconnect 17. FIG. 6B shows an electrical model for the interconnect 17. This model is used to determine the size of stubs 19A, 19B needed to control the impedance of the transition formed by the interconnect 17.
As shown in FIG. 6A, an output transmission line 20 on the daughterboard 14 is connected to an input transmission line 22 on the motherboard 12. In this example, the input and the output transmission lines 20, 22 have a characteristic impedance Zo. Using Equation 1, the plated through-hole inductance, L, of the interconnect 17 is determined in microHenrys. ##EQU1## t is the thickness of the daughterboard 14 in centimeters. The daughterboard 14 also has a given dielectric constant dependent on the material from which the daughterboard is constructed. Rpth is the plated through-hole radius in centimeters. In Equation 2, the capacitance required to compensate for L is determined. ##EQU2## Zo is the desired characteristic impedance of the connection. Cc is the capacitance necessary to compensate for the plated through-hole inductance.
The stubs 19A, 19B, such as copper patches, are added to the daughterboard 14 such that the capacitance of each is Cc /2. The stub 19B preferably underlies the contact pad 14A of the daughterboard 14. The size of the stubs 19A, 19B necessary to achieve this capacitance will depend on the board thickness t and dielectric constant of the daughterboard material. It can be calculated numerically or analytically, or determined from experiment.
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|U.S. Classification||361/790, 439/91, 361/760, 361/784, 361/803, 361/779|
|International Classification||H05K1/14, H05K3/34, H05K1/11, H05K3/36, H05K1/02|
|Cooperative Classification||H05K2201/10666, H05K3/368, H05K2201/10734, H05K3/3436, H01L2924/3011, H05K1/0243, H01L2224/48091, H05K2201/0715, H05K1/141, H01L2924/01078, H01L2924/01079, H01L2924/30107, H01L2924/3025|
|European Classification||H05K1/02C4D, H05K1/14B|
|Oct 19, 1995||AS||Assignment|
Owner name: HEWLETT-PACKARD COMPANY, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:NOE, TERRY;WEBER, LEONARD;REEL/FRAME:007746/0256
Effective date: 19951013
|Apr 28, 2000||AS||Assignment|
Owner name: HEWLETT-PACKARD COMPANY, A DELAWARE CORPORATION, C
Free format text: MERGER;ASSIGNOR:HEWLETT-PACKARD COMPANY, A CALIFORNIA CORPORATION;REEL/FRAME:010841/0649
Effective date: 19980520
|May 30, 2000||AS||Assignment|
Owner name: AGILENT TECHNOLOGIES INC, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HEWLETT-PACKARD COMPANY;REEL/FRAME:010977/0540
Effective date: 19991101
|Feb 9, 2001||FPAY||Fee payment|
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|Jan 15, 2009||FPAY||Fee payment|
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|Sep 16, 2014||AS||Assignment|
Owner name: KEYSIGHT TECHNOLOGIES, INC., CALIFORNIA
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