|Publication number||US5659760 A|
|Application number||US 08/019,274|
|Publication date||Aug 19, 1997|
|Filing date||Feb 18, 1993|
|Priority date||Feb 18, 1992|
|Publication number||019274, 08019274, US 5659760 A, US 5659760A, US-A-5659760, US5659760 A, US5659760A|
|Original Assignee||Nec Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (8), Referenced by (15), Classifications (10), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to a microprocessor and, more particularly, to an improvement in an interrupt vector generation unit in a microprocessor for generating an interrupt vector in response to an interrupt request.
As is well known in the art, in order for a microprocessor or central processing unit (CPU) to perform an operation requested by a peripheral unit operating in asynchronism with the CPU, the CPU handles such an operation as an interrupt operation. Specifically, the peripheral unit, when requesting a data processing operation from the CPU, supplies an interrupt request signal to the CPU. In response thereto, the CPU suspends the execution of a current program and then initiates an interrupt program routine corresponding to the requested data processing operation.
There are provided a plurality of peripheral units in general. The CPU is therefore required to distinguish which peripheral unit has issued an interrupt request. For this purpose, a plurality of interrupt vectors are provided correspondingly to the peripheral units. When one of the peripheral units issues an interrupt request, the interrupt vector associated thereto is generated and supplied to the CPU. The CPU thus distinguishes the interrupt program routine to be initiated by the associated interrupt vector.
There are two types of techniques for generating the interrupt vector, the first one of which is to generate the interrupt vector outside of the CPU and the second one of which is to generate it inside of the CPU.
Referring to FIG. 1, there is shown a microprocessor system of the first type. A CPU 1 is interconnected to an interrupt controller 3 via address and data buses 6 and 7. The controller includes an interrupt request control unit 31 supplied with interrupt request signals IQR-1 to IQR-m from peripheral units 10-1 to 10-m. When one or more peripheral units 10 issue the interrupt request, i.e., when one or more interrupt request signals IQR is changed to an active level, the interrupt request control unit 31 selects one of the active interrupt signals IRQ in accordance with the priority levels of the interrupt requests and then produces interrupt level information INTL representative of the selected interrupt request. The interrupt level information INTL is supplied to an interrupt vector generation unit 32 which, in response thereto, generates an interrupt vector IV corresponding to an interrupt operation of the selected peripheral unit 10. The interrupt vector IV is supplied to an output controller unit 34 which in turn outputs it on the data bus 7 when an enable signal supplied thereto takes an active level.
The interrupt level information INTL is further supplied to an interrupt receiving unit 11 of the CPU 1 through a level hold unit 33. The interrupt receiving unit 11 accepts the interrupt request indicated by level IV only when a mask bit of a status register (not shown) corresponding to the supplied interrupt level stores non-mask information and an execution unit 13 is performing a program operation whose level is lower than the supplied interrupt level. The interrupt receiving unit 11 produces interrupt status information AST representing whether or not the supplied interrupt request is accepted and further transfers, when accepting the interrupt request, the interrupt level IV onto the address bus 6. In the case of accepting the interrupt request, the CPU 1 initiates a bus cycle for fetching the interrupt vector.
The interrupt status information AST is decoded by a decoder 4. When the status information AST represents the acceptance of the interrupt request, the decoder 4 changes its output to an active level to activate a decoder 5. The decoder 5 thereby decodes the interrupt level INTL supplied via the address bus 6 and then changes one of interrupt acknowledge signals IACK connected respectively to the peripheral units 10 to an active level to inform the acceptance of the interrupt request. The ORed output of the acknowledge signals IACK is supplied to the output control unit 34 to allow it to output the interrupt vector IV onto the data bus 7. The CPU-1, which is in the interrupt vector fetch bus cycle, thus fetches and supplies the interrupt vector IV to an execution unit 13 through a vector input unit 14. An interrupt program operation is thus initiated.
Referring to FIG. 2, there is shown another microprocessor system of the second type in which the same constituents as those shown in FIG. 1 are denoted by the same reference numerals to omit the further description thereof. In this system, an interrupt vector generation unit is incorporated in the CPU 1. In order to synchronize the generation between the interrupt vector IV and the interrupt acknowledge signal IACK, there is provided a vector control unit 9 which is activated by the active level of at least one of the interrupt request signals IQR and produces an active level vector-enable signal AV in synchronism with the ORed acknowledge signal. The vector generation unit 12 is thereby activated to give the execution unit 13 the interrupt vector IV.
Since the CPU 1 has the interrupt vector generation unit 12, the interrupt vector fetch cycle is not required, which would be otherwise required in the system of FIG. 2. The firmware of CPU 1 of FIG. 2 is therefore simplified compared to that of FIG. 1.
Although two types of the microprocessor systems according to the prior art are described above, each of them is based on a technical concept that the execution unit 13 receives the interrupt vector IV simultaneously with the interrupt acknowledge signal IACK being returned to the peripheral unit 10. For this reason, the initiation of the interrupt program operation is delayed. Moreover, hardware such as the decoders 4 and 5 for producing the active level interrupt acknowledge signal is required and the interrupt receiving control unit 11 is required to produce the interrupt status information AST and transfer the interrupt level INTL.
It is therefore an object of the present invention is to provide a microprocessor which initiates an interrupt program operation with a minimum time delay in response to an interrupt request from a peripheral unit.
It is another object of the present invention is to provide a microprocessor which decreases hardware necessary for an interrupt operation.
A microprocessor according to the present invention is coupled to a plurality of peripheral units through a system bus and comprises a first terminal supplied an interrupt-enable signal which takes an active level when at least one of the peripheral units issues an interrupt request, a set of second terminals supplied with interrupt level information representative of one of the peripheral units issuing the interrupt request, an interrupt vector generation unit coupled to the first and second terminals, the generation unit being activated by the active level of the interrupt-enable signal and generating interrupt vector information in response to the interrupt level information, an interrupt receiving unit coupled to the first and second terminals, the receiving unit being activated by the interrupt-enable signal to detect whether or not an interrupt operation is to be initiated in response to the interrupt level information and producing, when the interrupt operation is detected to be initiated, vector fetching command information, and an execution unit coupled to the interrupt vector generation unit and the interrupt receiving unit and fetching the interrupt vector information in response to the vector fetching command information to initiate an interrupt program operation designated by the interrupt vector information, the execution unit returning an interrupt acknowledge to the peripheral unit by executing the interrupt program operation.
The present invention is thus based on a technical concept that the operation for returning the acknowledge to the peripheral unit can be performed as one of operations for the interrupt request. Accordingly, the generation of the interrupt vector is carried out immediately in response to the issue of the interrupt request and the execution unit receives the interrupt vector thus generated without waiting the interrupt acknowledge. The initiation of the interrupt program operation is made fast accordingly. Moreover, no hardware is required to generate and return the interrupt acknowledge signal to the peripheral unit.
The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the drawings, in which
FIG. 1 is a block diagram representative of a microprocessor system according to prior art;
FIG. 2 is a block diagram representative of microprocessor system according to another prior art;
FIG. 3 is a block diagram representative of a microprocessor system employing a microprocessor according to an embodiment of the present invention;
FIG. 4 is a timing chart representing operation of the system shown in FIG. 1; and
FIG. 5 is a block diagram representative of a microprocessor system according to another embodiment of the present invention.
Referring to FIG. 3, a microprocessor or CPU 100 according to am embodiment of the present invention is fabricated as an integrated circuit device and includes a set of data terminals 31, a set of address terminals 132 and a set of control terminals 133. These terminals 131, 132 and 133 are coupled to a system bus consisting of a data bus 60, an address bus 70 and a control bus 80. Further coupled to the system bus are a program memory 150 storing a main program and a plurality of interrupt programs, a data memory 200 for temporarily storing operand data and a plurality of peripheral units 10-1 to 10-m such as a disk controller, a display controller and so forth.
When the peripheral unit 10 requests a data processing from the CPU 100, it issues an interrupt request to change the corresponding interrupt request signal IRQ to an active level. An OR gate 300 thereby produces an active level of an interrupt-enable signal INTE. The interrupt requests IRQ are further supplied to an interrupt request control unit 250 which in turn selects one of the interrupt requests IRQ, which are issued concurrently, in accordance with a priority order provided therein and then produces interrupt level information INTL representative of the selected interrupt request. It is of course that when only one interrupt request is issued, the interrupt level information INTL corresponding thereto is produced.
The INTE signal is supplied to a terminal 111 of the CPU 100 and the interrupt level information INTL is supplied to a set of terminals 121 of the CPU 100. The CPU 100 further includes an interrupt vector generation unit 110 and an interrupt receiving control unit 120 both connected to the terminals 111 and 121. The vector generation unit 110 is activated by the active interrupt-enable signal INTE and generates interrupt vector information IV responsive to the interrupt level information. The interrupt vector information is supplied to an instruction execution unit 130. The interrupt receiving unit 120 is also activated by the active interrupt-enable signal INTE to detect whether or not an interrupt request indicative of the interrupt level information INTL is acceptable. When a mask bit of a status register (not shown) provided in the execution unit 130 stores non-mask information and the execution unit 130 is executing a program operation whose priority level is lower than that of the interrupt operation indicative of the information INTL, the unit 120 judges that the interrupt request currently selected is to be accepted and then supplies the execution unit 130 with interrupt vector fetching command information IVF. In response thereto, the execution unit 130 suspends the execution of a current program and fetches the interrupt vector information IV to initiate an interrupt program operation designated by the interrupt vector IV.
Assume now that the peripheral units 10-1 and 10-2 issue an interrupt request by changing the interrupt request signals IRQ-1 and IRQ-2 to the active high level simultaneously with each other, as shown in FIG. 4. In response thereto, the interrupt-enable signal INTE is changed to the active high level through the OR gate 300. In response further thereto, the interrupt request control unit 250 produces, since the peripheral unit 10-2 has a priority order higher than the peripheral unit 10-1, the interrupt level information INTL representative of the peripheral unit 10-2, as shown in FIG. 4. The interrupt vector generation unit 110 thus generates the interrupt vector IV corresponding to an interrupt operation for the peripheral unit 10-2 irrespective of whether or not the interrupt request issued by the peripheral unit 10-2 is actually accepted by the CPU 100.
By the active level interrupt-enable signal INTE, the interrupt receiving unit 120 is also activated. Since the mask bit corresponding to the peripheral unit 10-2 represents interrupt-acceptable data and the execution unit 130 is executing the main program operation, the unit 120 produces and supplies the interrupt vector fetching command information IVF to the execution unit 130, as shown in FIG. 4. In response thereto, the execution unit 130 fetches the interrupt vector IV and suspends the execution of the main program. The execution unit 130 then initiates a bus cycle for fetching an instruction from the program memory 150 by use of the interrupt vector. That is, the CPU 100 starts accessing the memory 150 to execute the interrupt program. The interrupt program operation for the peripheral unit 10-2 is thereby initiated.
In the beginning of the interrupt program operation thus initiated, the execution unit 130 performs a bus cycle for returning interrupt acknowledge data to the peripheral unit 10-2. Namely, the unit 130 transfers onto the address bus 70 address information representative of an I/O port of the peripheral unit 10-2 and onto the data bus 60 interrupt acknowledge data, as shown in FIG. 4. The execution unit 130 advances to execute instructions in the interrupt program. On the other hand, the peripheral unit 10-2 changes the interrupt request signal IRQ-2 to the inactive low level in response to the interrupt acknowledge data supplied from the CPU 100.
Since the interrupt request by the peripheral unit 10-1 is not accepted, the unit 10-1 retains the request signal IRQ-1 at the active high level, as shown in FIG. 4. Further, since the interrupt request signal IRQ-2 is changed to the low level, the interrupt request control unit 250 produces the interrupt level IV corresponding to the peripheral unit 10-1, as also shown in FIG. 4. The interrupt vector generation unit 110 thereby generates the interrupt vector indicative of the peripheral unit 10-1. However, the interrupt operation for the peripheral unit 10-2 has the priority level higher than that for the peripheral unit 10-1, the interrupt receiving unit 120 does not produce the vector fetching command information IVF, as shorn in FIG. 4. The interrupt operation for the unit 10-1 is thereby held.
When the interrupt operation for the peripheral unit 10-2 is completed, the interrupt operation for the peripheral unit 10-1 is initiated. Of course, when another peripheral unit 10 having a priority order higher than the unit 10-1 but lower than the unit 10-2 issues its interrupt request IRQ during the interrupt operation for the unit 10-2, the interrupt operation for the unit 10-1 continues to be held. If the peripheral unit 10 having the priority order higher than the unit 10-2 issues the interrupt request, the operation for the unit 10-2 is suspended and an operation for the newly issued interrupt request is initiated. After the completion of the new interrupt operation, the operation for the unit 10-2 is resumed.
Referring to FIG. 5, there is shown a microprocessor system according to another embodiment of the present invention in which the same constituents as those shown in FIG. 3 are denoted by the same reference numerals to omit the further description thereof. In the above embodiment, each of the peripheral unit 10 is required to hold the active level of the interrupt request signal IRQ until the CPU 100 executes the bus cycle for returning an interrupt acknowledge to the peripheral unit 10. In order to allow each peripheral unit to produce the interrupt request signal in a one-shot pulse form, the system of the present embodiment further includes flip-flop circuits 400-1 to 400-m each having a set input terminal S supplied with the corresponding one of the interrupt request signals IRQ. Further provided in this system are a decoder 500 coupled to the address and data buses 60 and 70 to detect the bus cycle for returning the interrupt acknowledge. The decoder 500, when detecting such a bus cycle, provides an active level on one of the reset signals corresponding respectively to the flip-flops 400-1 to 400-m to reset it. Thus, each of the peripheral units 10-1 to 10-m can produce the interrupt request signal IRQ in a one-shot form.
It is apparent that the present invention is not limited to the above embodiments but may be changed or modified without departing from the scope and spirit of the invention.
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|U.S. Classification||710/269, 710/260, 712/38, 710/49, 710/50|
|International Classification||G06F9/22, G06F13/24, G06F9/48|
|Feb 18, 1993||AS||Assignment|
Owner name: NEC CORPORATION, JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:ENAMI, TOMOKAZU;REEL/FRAME:006453/0069
Effective date: 19930215
|Feb 1, 2001||FPAY||Fee payment|
Year of fee payment: 4
|Mar 9, 2005||REMI||Maintenance fee reminder mailed|
|Aug 19, 2005||LAPS||Lapse for failure to pay maintenance fees|
|Oct 18, 2005||FP||Expired due to failure to pay maintenance fee|
Effective date: 20050819