|Publication number||US5661663 A|
|Application number||US 08/409,757|
|Publication date||Aug 26, 1997|
|Filing date||Mar 24, 1995|
|Priority date||Mar 24, 1995|
|Publication number||08409757, 409757, US 5661663 A, US 5661663A, US-A-5661663, US5661663 A, US5661663A|
|Inventors||Ranko Scepanovic, James S. Koford, Valeriy B. Kudryavtsev, Alexander E. Andreev, Stanislav V. Aleshin, Alexander S. Podkolzin|
|Original Assignee||Lsi Logic Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (9), Non-Patent Citations (11), Referenced by (61), Classifications (6), Legal Events (8)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention generally relates to the art of microelectronic integrated circuits, and more specifically to a physical design automation system and method for producing a cell placement for an integrated circuit chip using hierarchical clusterization and placement improvement based on complete replacement of cell clusters.
2. Description of the Related Art
Microelectronic integrated circuits include large numbers of electronic components that are fabricated by layering several different materials on a silicon base or wafer. The design of an integrated circuit transforms a circuit description into a geometric description which is known as a layout. A layout consists of a set of planar geometric shapes in several layers.
The layout is then checked to ensure that it meets all of the design requirements. The result is a set of design files in a particular unambiguous representation known as an intermediate form that describes the layout. The design files are then converted into pattern generator files that are used to produce patterns called masks by an optical or electron beam pattern generator.
During fabrication, these masks are used to pattern a silicon wafer using a sequence of photolithographic steps. The component formation requires very exacting details about geometric patterns and separation between them. The process of converting the specifications of an electrical circuit into a layout is called the physical design. It is an extremely tedious and an error-prone process because of the tight. tolerance requirements and the minuteness of the individual components.
Currently, the minimum geometric feature size of a component is on the order of 0.5 microns. However, it is expected that the feature size can be reduced to 0.1 micron within several years. This small feature size allows fabrication of as many as 4.5 million transistors or 1 million gates of logic on a 25 millimeter by 25 millimeter chip. This trend is expected to continue, with even smaller feature geometries and more circuit elements on an integrated circuit, and of course, larger die (or chip) sizes will allow far greater numbers of circuit elements.
Each microelectronic circuit cell includes a plurality of pins or terminals, each of which is connected to pins of other cells by a respective electrical interconnect wire network or net. A goal of the optimization process is to determine a cell placement and routing such that all of the required interconnects can be made, and the total wirelength and interconnect congestion are minimized.
Existing placement methods based on hierarchical clusterization perform an exhaustive search over all possible configurations. Examples of such method as described in the following articles:
"SIMULTANEOUS FLOOR PLANNING AND GLOBAL ROUTING FOR HIERARCHICAL BUILDING-BLOCK LAYOUT", by W. Dai et al, IEEE Transactions on Computer-Aided Design, Vol. 6, No. 5, 1987, pp. 828-837.
"HIERARCHICAL PLACEMENT AND FLOORPLANNING IN BEAR", by W. Dai et al, IEEE Transactions on Computer-Aided Design, Vol. 8, No. 12, 1989, pp. 1335-1349.
"A NEW CLUSTERING APPROACH AND ITS APPLICATION TO BBL PLACEMENT", by M. Yu et al, IEEE Transactions on Computer-Aided Design, Vol. 9, No. 12, 1990, pp. 665-669.
As a result of the exhaustive search and exponential growth of possible configurations, the number of subclusters in each cluster is very limited (not greater than 4-5). At the same time, this real bound on the number of clusters in each hierarchical level ends up with a reduction of the placement quality.
Investigations in the above referenced article to Yu points out the necessity of using the largest possible groups of clusters and a smaller number of hierarchical levels.
The other disadvantage of known placement algorithms which are based on iterative improvement of an initial placement is the time consuming process of overcoming of the effect of local extrema. Examples of this kind of algorithm are simulated annealing and genetic algorithms which use stochastic principles to overcome the local extrema effect as described in the following articles:
"AN IMPROVED SIMULATED ANNEALING ALGORITHM FOR ROW-BASED PLACEMENT", by C. Sechen et al, IEEE Conference on Computer-Aided Design, 1987, pp. 478-481.
"GENETIC PLACEMENT", by J. Cohoon et al, IEEE International Conference on Computer-Aided Design, 1986, pp. 422-425.
In view of the above, there exists a need in the art for a physical design automation system which is able to generate large clusters without performing an exhaustive search of all possible combinations, while simultaneously overcoming of the effects of local extrema.
An important object of the present invention is the achievement of placement optimization based on clusterization in order to overcome the effect of local extrema.
A method of producing a placement of cells for a microelectronic integrated circuit in accordance with specified cell interconnects includes constructing a hierarchial cluster tree based on the interconnects in which a lowest level of the tree includes clusters of interconnected cells, and each successively higher level includes clusters of interconnected clusters from a successively lower level. Clusters in each level are merged by a min-cut operation.
Clusters of each successively lower level are then placed within clusters of each successively higher level in progressively decreasing order of levels. Clusters are placed in each level by computing a current gravity point for each cluster in accordance with the cells therein, computing a new gravity point for each cluster in accordance with the current gravity points and the interconnects, and moving each cluster from the current gravity point to the new gravity point.
Cells within clusters of the lowest level are then placed by calculating positions of the cells in a row direction, and placing the cells in columns in increasing order of the calculated positions in the row direction.
The method is implemented by a parallel processing system including a plurality of parallel processors, and is able to generate large clusters without performing an exhaustive search of all possible combinations, while simultaneously overcoming of the effects of local extrema.
These and other features and advantages of the present invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings, in which like reference numerals refer to like parts.
FIG. 1 is a simplified diagram illustrating a conventional rectilinear integrated circuit interconnect routing arrangement;
FIG. 2 is a block diagram illustrating a physical design automation system embodying the present invention;
FIG. 3 is a flowchart illustrating a method of producing a placement of cells for a microelectronic integrated circuit using the physical design automation system of FIG. 2;
FIG. 4 is a diagram illustrating a hypergraph including a simplified set of cells and interconnect nets for placement using the present invention;
FIGS. 5a to 5e are diagrams illustrating alternative methods of converting a hypergraph into a graph;
FIG. 6 is a diagram illustrating pre-clusterization;
FIGS. 7a to 7c are diagrams illustrating cluster merging;
FIGS. 8a to 8d are diagrams illustrating the construction of a cluster tree including four levels of clusters;
FIG. 9 is a diagram illustrating cluster re-placement for a cluster tree including four levels of clusters;
FIG. 10 is a diagram illustrating computation of a gravity point for cluster improvement;
FIG. 11 is a diagram illustrating cluster placement improvement for one cluster level;
FIG. 12 is a diagram illustrating cluster re-placement for the cluster level of FIG. 11;
FIG. 13 is a diagram illustrating cells in a lowest cluster level for re-placement; and
FIG. 14 is a diagram illustrating how the cells of FIG. 13 are re-placed in accordance with the invention.
An exemplary integrated circuit chip is illustrated in FIG. 1 and generally designated by the reference numeral 10. The circuit 10 includes a semiconductor substrate 12 on which are formed a number of functional circuit blocks that can have different sizes and shapes. Some are relatively large, such as a central processing unit (CPU) 14, a read-only memory (ROM) 16, a clock/timing unit 18, one or more random access memories (RAM) 20 and an input/output (I/O) interface unit 22. These blocks can be considered as modules for use in various circuit designs, and are represented as standard designs in circuit libraries.
The integrated circuit 10 further comprises a large number, which can be tens of thousands, hundreds of thousands or even millions or more of small cells 24. Each cell 24 represents a single logic element, such as a gate, or several logic elements that are interconnected in a standardized manner to perform a specific function. Cells 24 that consist of two or more interconnected gates or logic elements are also available as standard modules in circuit libraries.
The cells 24 and the other elements of the circuit 10 described above are interconnected or routed in accordance with the logical design of the circuit to provide the desired functionality. Although not visible in the drawing, the various elements of the circuit 10 are interconnected by electrically conductive lines or traces that are routed, for example, through vertical channels 26 and horizontal channels 28 that run between the cells 24.
FIG. 2 illustrates an integrated circuit physical design automation system 30 for producing an optimized placement of the cells 24 such as illustrated in FIG. 1 in accordance with a method of the present invention.
The system 30 receives inputs for a user specified integrated circuit design including a netlist, a library of standardized microelectronic elements or cells and functional units including combinations of cells, and a set of rules that define the objectives of the design.
The system 30 decomposes these inputs into a plurality of parallel processes or tasks that are executed simultaneously using individual processing units. In general, one or more processors coordinate the operation of other processors, which are optimized, evaluated and recombined to produce an optimal cell placement and routing that satisfy a predetermined performance objective.
The optimal cell placement and routing produced by the system 30 is used to generate masks for fabrication of the desired integrated circuit chip.
The system 30 comprises a global operating system 32 that generally controls and coordinates the operation of parallel processing software 34 and simultaneous processing architecture 36.
The architecture 36 includes a plurality of parallel processors and a memory structure for simultaneously executing methodologies or algorithms 38 for placement, routing and measuring the relative fitnesses of cell placements and optimizing the fitnesses. Implementation of the algorithms 38 is facilitated by a cell placement representation 40 and cost function or quality factor computation 42. The architecture 36 can be of any type, such as Distributed Shared Memory (DSM), that enables parallel processing in accordance with the method of the invention.
The architecture 36 collectively implements the functions of a tree construction means, cluster placement means, cell placement means, control means and other functional means by assigning different parallel processors to perform these functions and combining the results thereof as will become evident from the following description.
The general outline of the present method is illustrated in flowchart form in FIG. 3. The method will be described first concisely using mathematical set theory notation, and then in a narrative manner with reference to the figures of drawing.
The placement problem is specified as a set of functional microelectronic device cells, and a netlist including nets of interconnect wires that interconnect the cells to produce the required logical functionality. The cells can be of the same size, as in a gate array, or of various different sizes. The cells can have the same width and different heights, the same height and different widths, and/or different widths and heights.
The set of cells and netlist are represented as a hypergraph H, in which the cells constitute vertices and the interconnect wires of the nets constitute edges. The hypergraph does not have any specific spatial form, as the cells can be located anywhere and the interconnects can take a number of forms. The latter is because an interconnect net specifies cells that are to be electrically interconnected, but does not specify any particular configuration of wires to perform the interconnection.
As indicated as a step 50 in FIG. 3, the hypergraph H is converted into a graph G which includes the vertices of the hypergraph H. However, the nets of the hypergraph are replaced by discrete edges that are defined in a predetermined manner. Although the graph G still does not provide any particular geometric configuration, it specifies specific edges (wires) for interconnecting cells (vertices) which are lacking in the hypergraph H.
The graph G is constructed by substituting each hyperedge in the hypergraph H with an edge or edges of a cluster tree T. This tree can be a linear randomly chosen chain of edges. If simple nets (2-3 pins) predominate 85% in a netlist, the manner of transformation of H into G does not affect clusterization. In cases where the optimization goals are explicitly formulated, procedures of transformation of H into G can be applied that are based on these goals.
The vertices of the graph G are leaves of the tree T which are designated as the 0-th level of the tree T. All other vertices of the tree T are clusters such that a cluster of the i-th level is formed by all of its connections (edges of T) with elements from (i-1)-th level.
i=1, 2, . . . , p, where p is the index of the root of the tree T. If the (i-1)-th level of the tree has been already constructed, the construction of the i-th level consists of two steps: preclusterization as indicated as a step 52, and modification as indicated as a step 54.
For i=0, the pre-clusterization step 52, disjoint spheres are created with radius equal to 1 of vertices of G (i.e., all vertices adjacent to a given vertex) as preclusters of the 0-th level. When i≧1, clusters are taken from the previous level as clusters of the i-th level. After forming clusters, they are modified using a min-cut type algorithm such as described in an article entitled "A LINEAR-TIME HEURISTIC FOR IMPROVING NETWORK PARTITIONS", by C. Fiduccia and R. Mattheyses, Proceedings of the 19th Design Automation Conference, 1982, pp. 175-181. The steps 52 and 54 create the cluster tree T in which the clusters (preclusters) of the lowest level are formed of cells (vertices), and the highest level consists of a single cluster. Step 54 is repeated for each level until the highest level is reached as indicated by a loop including steps 56 and 58.
The clusterization steps 52 and 54 create clusters for re-placement in subsequent steps. The significance of this phase is in extracting from the graph G sufficiently "natural" compact groups of vertices with comparable weak upper bounds for their number of elements (e.g., not more than 50-100 elements).
After constructing the cluster tree, regions for placing clusters of p-th, (p-1)-th, . . . , 1-st level of the tree are determined in descending order of levels. If regions for placing clusters of the i-th level have been determined, a sequence of their complete re-placement is applied. Assuming that a rectangular region P has been determined for placing of the cluster K from the i-th level of the tree, following steps are iteratively repeated in order to improve the placement of subclusters of the cluster K within the region P.
Starting with an initial placement (which can be random), the next step 60 is to calculate the coordinates (x1, Y1), . . . , (xn, Yn) of the gravity points of first time random subclusters of P which are determined from the previous iterative step for placing subclusters Kn, . . . Kn of the cluster K.
The desired geometric configuration of the placement of subclusters is then determined in a step 61 by computing new respective gravity points (x1 ', y'1), . . . , (x'n, yn ') according to the following formulas: ##EQU1## where m1 is the number of edges connecting a vertex of the subcluster Kj with a vertex of the subcluster Kj1.
In other words, for the new gravity point of a subcluster, the gravity point of all edges connecting the subcluster with other subclusters is computed. The new gravity points constitute a plan of complete re-placement of the tree T of subclusters which characterize their relative positions in terms of relations "left-right" and "up-down".
According to the re-placement plan, subclusters of K in the region P are placed by halving the rectangle P such that the halves P1 and P2 are as close as possible to squares and corresponding partitions of K are as close as possible in terms of sums of areas (or only heights if widths of all cells are equal) of cells which belong to the partitions. The halving process is continued until single subclusters of K are reached.
This process is repeated in descending order of levels of the cluster tree T as indicated by a loop including steps 62, 64 and 66. When the lowest level is reached in which the clusters include cells, the cells are placed "column by column" as indicated in a step 68.
First, the group of new gravity points of the re-placement plan which are further left from others are extracted, which have the sum of the corresponding cell heights equal to the column height. These points are placed according to the y-coordinates of their plan points. The operation proceeds in the same manner to fill all columns form left to the right.
The present invention provides a constructive placement method which does not involve an exhaustive search of possible combinations, and is therefore not susceptible to the effects of local extrema. A more detailed description of the present invention will now be presented with reference to the additional figures of drawing.
A graph 70 that was constructed from a specified set of cells and an interconnect netlist is illustrated in FIG. 4. The graph 70 includes cells (vertices) 72 to 100 that are interconnected by wires (edges) 102 to 122.
The cells 72 and 74 are interconnected a two-pin net that consists of the single wire 102. Thus, only one interconnection is possible. The other cells are interconnected by nets consisting of more than one wire, and can be interconnected in different ways as specified by the hypergraph (netlist). FIG. 4 illustrates only one possible graph 70 based on the hypergraph.
Step 50 of FIG. 3 comprises converting a hypergraph into a graph, in which the nets are replaced by discrete edges. The edges can be defined in any known manner in accordance with the invention. For example, FIG. 5a illustrates a grouping 130 of seven cells 132 to 144 that are specified as being interconnected by a single interconnect wire net in the netlist (hypergraph). The net of the hypergraph is converted into discrete form as a linear chain of edges 146 to 158 that lead from the cell 132 to the cell 144 as shown.
The order of chain connected edges can be selected at random, or using any other method. Rather than the illustrated arrangement, for example, in which the cells 138, 140, 142 and 144 are connected in order, these cells could be chain connected by edges in the order 138, 142, 140 and 144.
FIG. 5b illustrates a grouping 160 of the cells 132 to 144 in which the net is converted into a star configuration with the cell 142 at the center of the star. The other cells are connected to the cell 142 by edges 132 to 172 as shown.
FIG. 5c illustrates another grouping 180 in which the cells 132 to 144 are interconnected in a star configuration by edges 184 to 196 which join at a virtual point 182. A similar grouping 200 is illustrated in FIG. 5d as a star configuration including two virtual points 202 and 204 and edges 206 to 220.
The graph can also represent the nets in the form of trees as in a grouping 230 illustrated in FIG. 5e. The cell 132 is the root of the tree, with the cell 136 being connected thereto by an edge 232 which constitutes a branch. The cells 134 and 138 are branched from the cell 132 by edges 234 and 236, whereas the cell 142 is branched from the cell 138 by an edge 238. The cells 140 and 144 branch from the cell 142 via edges 240 and 242.
Various tree configurations can be constructed in accordance with the present invention, such as minimum Steiner trees. The particular method of converting a hypergraph into a graph is not the particular subject matter of the invention, and can be performed using any suitable algorithm or function. The purpose of the step 50 is to produce a discrete set of cell interconnections for operation thereon in subsequent steps.
The pre-clusterization step 52 is illustrated in FIG. 6. A grouping 250 consisting of cells 252 to 264 is interconnected by a net that is represented by edges 266 to 276. The grouping 250 is preferably divided into two pre-clusters 278 and 280 which include the cells 252 to 258 and 260 to 264 respectively. The pre-clusters 278 and 280 are formed such that each includes a selected cell (vertex) that is connected to each other cell in the cluster by a single edge (radius=1).
As illustrated, the cluster 278 includes a selected cell 256 which is connected to the cells 252, 254 and 258 by the single edges 266, 268 and 270 respectively. The cluster 280 includes a selected cell 260 which is connected to the cells 262 and 264 by the single edges 274 and 276 respectively.
The step 54 of modifying clusters in each level is illustrated in FIGS. 7a to 7c. In FIG. 7a, a cluster 300 includes cells 302 to 306, whereas a cluster 308 includes cells 310 to 314. The cells 302 to 314 are interconnected by edges 316 to 332 as shown. Some of the edges (intra-cell edges) interconnect cells within a cluster, whereas other edges (intercell edges) interconnect cells in different clusters. For example, the edge 316 in FIG. 7a is an intra-cell edge, whereas the edge 320 is an inter-cell edge.
The clusters in each level are modified (some are merged together) using a min-cut type function. Preferably, each cell (vertex) is considered separately, and the numbers of intra-cell edges and inter-cell edges that are connected thereto are calculated. If the number of inter-cell edges is larger than the number of intra-cell edges, the cell is moved from its current cluster to a cluster to which it is connected by the largest number of inter-cell edges. If the numbers are the same, the cell can be left in place or moved randomly.
In FIG. 71, the cell 302 is connected to the cell 304 by the intra-cell edge 316 and to the cell 310 by the inter-cell edge. Since the numbers of intra- and inter-cell edges are the same, the cell 302 is not moved.
The cell 304 has two intra-cell edges 316 and 318, and three inter-cell edges 322, 324 and 326. It is therefore moved from the cluster 300 to the cluster 308 as illustrated in FIG. 7b. The cell 306 has one intra-cell edge 318 and one inter-cell edge 328, and is not moved in this step.
Although the example of FIGS. 7a to 7c does not include updating the status of the clusters after each cell movement, it is within the scope of the invention to do so.
In FIG. 7b, each cell 302 and 306 has no intra-cell edges in the cluster 300 and two inter-cell edges leading to the cluster 308. Thus, in the next iteration, the cells 302 and 306 are moved to the cluster 308 as illustrated in FIG. 7c, leaving the cluster 300 empty. The empty cluster is deleted from the list of clusters for the next highest level.
FIGS. 8a to 8d illustrate how the clustering process proceeds from one level to a successively higher level of the cluster tree. In each level, the cluster modification step 54 can be performed once for each cell, or iteratively repeated until a predetermined criterion is satisfied. In a preferred form of the invention, the step 54 is iteratively performed until the average number of elements (cells or clusters from lower levels) in each cluster is approximately 50-100.
The steps 56 and 58 constitute a loop for constructing successively higher levels of clusters. After performing step 54 to form one level, the clusters in this level are used as the input for forming the next level. When the highest level is reached, which consists of a single cluster, the method continues to the next step 60.
FIG. 8a illustrates a level 340 consisting of clusters A to D. Performing the step 54 for the level 340 results in merging of the clusters A and B to form a cluster F, and merging the clusters C and D to form a cluster G. The next higher level 342 as shown in FIG. 8b consists of the clusters E, F and G.
Performing the step 54 on the level 342 results in merging the clusters E and G to form a cluster H consisting of the clusters E and G in a level 344 as illustrated in FIG. 8C. The level 344 consists of the clusters F and H.
The clusters F and H are merged by performing the step 54 on the clusters F and H such that a level 346 consists of a single cluster I including the clusters F and H.
The re-placement portion of the present method is illustrated conceptually in FIG. 9. A cluster tree 350 is symbolically represented as a pyramid with five exemplary levels of clusters. LEVEL 4 is a single cluster including all of the clusters of LEVEL 3. An exemplary cluster 352 of LEVEL 3 includes a group 354 of clusters of LEVEL 2. An exemplary cluster 356 of the group 354 includes a group 358 of clusters of LEVEL 1, whereas an exemplary cluster 360 of LEVEL 1 includes a group 362 of cells 364 of LEVEL 0. The other clusters of LEVEL 0 TO LEVEL 2 are not shown for simplicity of illustration.
In general, the re-placement operation of the invention generates an efficient placement of subclusters (of the successive lower level) of each cluster in each level. This is performed from the top down, so that the entire surface of the integrated circuit chip is covered hierarchically in a progressively increasing level of detail. Since the plan for a successively lower level is provided by the successively higher level, the re-placement plan is complete, efficient, and avoids local extrema.
Prior to performing the placement portion of the method, the clusters and cells do not have any particular geometric arrangement relative to each other. As illustrated in FIG. 3, for each cluster in each level starting with the highest level (the clusters of LEVEL 3 in FIG. 9), an initial placement of the subclusters in the cluster is generated in any suitable manner (e.g. random). This is the beginning of the complete replacement method of the invention which provides an efficient geometric placement of each cluster and ultimately each cell.
Since clusters represent groups of clusters or cells, a current gravity point is computed for each cluster so that it can be represented by a single point in an orthogonal coordinate system in the step 60. The manner in which the gravity point is computed is illustrated in FIG. 10. The center of gravity computation is illustrated for an exemplary cluster consisting of two cells 370 and 372.
The location of the cell 370 is represented in an orthogonal system of x and y coordinates as x1,y1, whereas the location of the cell 372 is represented as x2,y2. The x component of the center of gravity 374 of the cells 370 and 372 is computed as the average of the x components of the locations the cells 370 and 372, more specifically as (x1+x2)/2. The y component of the center of gravity CG is computed as the average of the y components of the locations of the cells 370 and 372, more specifically as (yl+y2)/2.
Although the computation for only two cells is illustrated in FIG. 10, it will be understood that the operation can be generalized for a cluster comprising any number of cells. It will be further understood that rather than computing the gravity point of each cluster, the scope of the invention includes computing a "centroid"0 for each cluster, which is a general term that can alternatively specify center of gravity, mass, force, area, etc.
The step of FIG. 61 includes modifying the initial placement to produce an improved placement. This is preferably performed by computing a new gravity point for each cluster, and moving the cluster to the new gravity point.
The step 61 utilizes the concept of "force directed placement" in which the clusters (vertices) are modeled as masses and the edges are modeled as springs pulling the clusters together. The gravity point for a given cluster in a given configuration is that point for which all the spring forces acting on that cluster would go to zero if the cluster were moved there. All clusters are assumed to be fixed in their current positions except for the cluster that is selected.
The desired geometric configuration of the placement of subclusters is determined by computing new respective gravity points (x1 ', y'1), . . . , (x'n, yn ') according to the following formulas: ##EQU2## where m1 is the number of edges connecting a vertex of the subcluster Kj with a vertex of the subcluster Kj1.
In other words, for the new gravity point of a subcluster, the gravity point of all edges connecting the subcluster with other subclusters is computed.
After the clusters are placed, an interconnect routing is performed based on the netlist. Step 61 is preferably iteratively repeated as indicated by the step 62 until a predetermined end criterion is reached. This is accomplished by computing a quality factor for each placement iteration which is typically the total length (interconnect wirelength) of all edges in the respective cluster. The end criterion is satisfied when the wirelength for a current iteration has not improved from that of a previous iteration by more than a predetermined value.
After the subclusters are moved to their new gravity points, they are arranged within the area of the placement which was determined for the cluster in the successively higher level. FIG. 11 illustrates an area 380 in which subclusters 382 to 396 of a cluster (not designated) of a successively higher level in the cluster tree are to be placed. The subclusters 382 to 396 have new gravity points 382a to 396a which were computed in the manner described above.
As shown in FIG. 11, the subclusters 382 and 396 have different sizes and partially overlap each other. The subclusters 382 to 396 are re-placed in the area 380 in a manner which removes the overlap. First, a "median interval" is computed in the vertical direction such that the area of the cells above the median interval 398 is equal to the area of the cells below the median interval 398. As shown, the subclusters 382, 384, 390 and 392 are located above the median interval 398, whereas the subclusters 386, 388, 394 and 396 are located below the interval 398.
A similar median interval 400 is then computed in the horizontal direction, such that the cells 382,384, 386 and 388 are located leftward of the interval 400, whereas the cells 390, 392, 394 and 396 are located rightward of the interval 400.
In this manner, the area 380 has been partitioned into four sections by the intervals 398 and 400, with the subclusters 382 and 384 to be located in the upper left section, the subclusters 390 and 392 to be located in the upper right section, the subclusters 386 and 388 to be located in the lower left section and the subclusters 394 and 396 to be located in the lower right section. The four sections are then partitioned again by median intervals 402 to 408.
The result of the re-placement operation is illustrated in FIG. 12, in which an individual subsection or partition is provided for each subcluster. After the computation of the partitioning is completed, the subclusters are moved to their respective partitions as illustrated.
This operation is performed for all clusters in all of the levels. The top-down planning provided by the present hierarchial clusterization method ensures that each cell is placed in a position that is pre-planned and provides efficient routing based on the specified netlist. A loop provided by the steps 64 and 66 results in progressive placement of the clusters in each level as symbolically illustrated in FIG. 9.
The cell placement step 68 is illustrated in FIGS. 13 and 14, which places the cells in the preclusters in the lowest level of the cluster tree. FIG. 13 illustrates a placement of cells 502 to 532 in an area 500 that was performed using the gravity point placement operation described above. The cells 502 to 532 are illustrated as having the same width for simplicity of description, but the invention is not so limited.
As with the case of cluster placement, the force directed gravity point method results in cells that partially overlap. The cells are ordered from left to right in accordance with their horizontal (row) position. For example, the cell 502 is the leftmost in FIG. 13, with the cell 504 being the next rightward of the cell 502, etc.
After ordering in the horizontal direction, the cells are arranged vertically in columns in order of their horizontal positions. As illustrated in FIG. 14, a leftmost column includes the cells 502 to 506 which have the leftmost positions in FIG. 13. The next four leftmost cells 510 to 516 are placed in the next right column. The cells 518 to 524 and 526 to 532 are placed in the remaining columns as shown.
In general, after one column has been filled up, the next column begins to be filled with the next leftmost cells, etc. The number of cells that will be placed in each column can vary depending on the heights of the cells, with the sum of the heights of the cells in each column being equal to or less than the height of the column.
In summary, the present invention provides a physical design automation system which is able to generate large clusters without performing an exhaustive search of all possible combinations, while simultaneously overcoming of the effects of local extrema.
Various modifications will become possible for those skilled in the art after receiving the teachings of the present disclosure without departing from the scope thereof.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4577276 *||Sep 12, 1983||Mar 18, 1986||At&T Bell Laboratories||Placement of components on circuit substrates|
|US4815003 *||Jun 19, 1987||Mar 21, 1989||General Electric Company||Structured design method for high density standard cell and macrocell layout of VLSI chips|
|US4908772 *||Mar 30, 1987||Mar 13, 1990||Bell Telephone Laboratories||Integrated circuits with component placement by rectilinear partitioning|
|US4918614 *||Jun 2, 1987||Apr 17, 1990||Lsi Logic Corporation||Hierarchical floorplanner|
|US5202840 *||Dec 19, 1990||Apr 13, 1993||Vlsi Technology, Inc.||Method for partitioning of connected circuit components before placement in one or more integrated circuits|
|US5239465 *||May 7, 1991||Aug 24, 1993||Hitachi, Ltd.||Method and system for layout design of integrated circuits with a data transferring flow|
|US5521837 *||Jan 19, 1995||May 28, 1996||Xilinx, Inc.||Timing driven method for laying out a user's circuit onto a programmable integrated circuit device|
|US5557533 *||Apr 19, 1994||Sep 17, 1996||Lsi Logic Corporation||Cell placement alteration apparatus for integrated circuit chip physical design automation system|
|US5568636 *||Sep 13, 1994||Oct 22, 1996||Lsi Logic Corporation||Method and system for improving a placement of cells using energetic placement with alternating contraction and expansion operations|
|1||*||Carl Sechen and Kai Win Lee; An Improved Simulated Annealing Algorithm for Row Based Placement; IEEE, 1987, pp. 478 481.|
|2||Carl Sechen and Kai-Win Lee; An Improved Simulated Annealing Algorithm for Row-Based Placement; IEEE, 1987, pp. 478-481.|
|3||*||CHAMP: Chip Floor Plan for Hierarchical VLSI Layout Design.|
|4||*||James P. Cohoon and William D. Paris; Genetic Placement; IEEE, 1986, pp. 422 425.|
|5||James P. Cohoon and William D. Paris; Genetic Placement; IEEE, 1986, pp. 422-425.|
|6||*||M.Y. Yu, X.L. Hong, Y.E. Lien, Z.Z. Ma, J.G. Bo and W.J. Zhuang; A New Clustering Approach and Its Application to BBL Placement; IEEE, 1990; pp. 665 669.|
|7||M.Y. Yu, X.L. Hong, Y.E. Lien, Z.Z. Ma, J.G. Bo and W.J. Zhuang; A New Clustering Approach and Its Application to BBL Placement; IEEE, 1990; pp. 665-669.|
|8||*||Wayne Wei Ming Dai, Bernhard Eschermann, Ernest S. Kuh and Massoud Pedram; Hierarchical Placement and Floorplanning in BEAR; IEEE Transactions on Computer Aided Design, vol. 8, No. 12, Dec. 1989, pp. 1335 1349.|
|9||Wayne Wei-Ming Dai, Bernhard Eschermann, Ernest S. Kuh and Massoud Pedram; Hierarchical Placement and Floorplanning in BEAR; IEEE Transactions on Computer-Aided Design, vol. 8, No. 12, Dec. 1989, pp. 1335-1349.|
|10||*||Wei Ming Dai and Ernest S. Kuh; Simultaneous Floor Planning and Global Routing for Hierarchical Building Block Layout; IEEE Transactions on Computer Aided Design, vol. CAD 6, No. 5, Sep. 1987, pp. 828 837.|
|11||Wei-Ming Dai and Ernest S. Kuh; Simultaneous Floor Planning and Global Routing for Hierarchical Building-Block Layout; IEEE Transactions on Computer-Aided Design, vol. CAD-6, No. 5, Sep. 1987, pp. 828-837.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US5859782 *||Feb 11, 1997||Jan 12, 1999||Lsi Logic Corporation||Efficient multiprocessing for cell placement of integrated circuits|
|US5870311 *||Jun 28, 1996||Feb 9, 1999||Lsi Logic Corporation||Advanced modular cell placement system with fast procedure for finding a levelizing cut point|
|US5872718 *||Jun 28, 1996||Feb 16, 1999||Lsi Logic Corporation||Advanced modular cell placement system|
|US5875118 *||Feb 11, 1997||Feb 23, 1999||Lsi Logic Corporation||Integrated circuit cell placement parallelization with minimal number of conflicts|
|US5887155 *||Jul 25, 1996||Mar 23, 1999||Microunity Systems Engineering, Inc.||Vertex based geometry engine system for use in integrated circuit design|
|US5892688 *||Jun 28, 1996||Apr 6, 1999||Lsi Logic Corporation||Advanced modular cell placement system with iterative one dimensional preplacement optimization|
|US5898597 *||Feb 11, 1997||Apr 27, 1999||Lsi Logic Corporation||Integrated circuit floor plan optimization system|
|US5914888 *||Jun 28, 1996||Jun 22, 1999||Lsi Logic Corporation||Advanced modular cell placement system with coarse overflow remover|
|US5926398 *||Mar 3, 1997||Jul 20, 1999||Nec Corporation||Semiconductor device layout method capable of arranging functional cells with data signal lines and control signal lines having a proper length and configuration|
|US5963455 *||Jun 28, 1996||Oct 5, 1999||Lsi Logic Corporation||Advanced modular cell placement system with functional sieve optimization technique|
|US6026223 *||Jun 28, 1996||Feb 15, 2000||Scepanovic; Ranko||Advanced modular cell placement system with overlap remover with minimal noise|
|US6052517 *||Jun 30, 1998||Apr 18, 2000||Ball Semiconductor, Inc.||Spherical cell design for VLSI circuit design on a spherical semiconductor|
|US6058254 *||Aug 6, 1997||May 2, 2000||Lsi Logic Corporation||Method and apparatus for vertical congestion removal|
|US6067409 *||Feb 11, 1997||May 23, 2000||Lsi Logic Corporation||Advanced modular cell placement system|
|US6068662 *||Aug 6, 1997||May 30, 2000||Lsi Logig Corporation||Method and apparatus for congestion removal|
|US6070108 *||Aug 6, 1997||May 30, 2000||Lsi Logic Corporation||Method and apparatus for congestion driven placement|
|US6075933 *||Aug 6, 1997||Jun 13, 2000||Lsi Logic Corporation||Method and apparatus for continuous column density optimization|
|US6085032 *||Jun 28, 1996||Jul 4, 2000||Lsi Logic Corporation||Advanced modular cell placement system with sinusoidal optimization|
|US6123736 *||Aug 6, 1997||Sep 26, 2000||Lsi Logic Corporation||Method and apparatus for horizontal congestion removal|
|US6154874 *||Apr 17, 1998||Nov 28, 2000||Lsi Logic Corporation||Memory-saving method and apparatus for partitioning high fanout nets|
|US6161214 *||Sep 6, 1996||Dec 12, 2000||Matsushita Electric Industrial Co., Ltd.||Method of generating data on component arrangement|
|US6175950 *||Apr 17, 1998||Jan 16, 2001||Lsi Logic Corporation||Method and apparatus for hierarchical global routing descend|
|US6182272||Jul 16, 1998||Jan 30, 2001||Lsi Logic Corporation||Metal layer assignment|
|US6186676||Aug 6, 1997||Feb 13, 2001||Lsi Logic Corporation||Method and apparatus for determining wire routing|
|US6195789 *||Sep 30, 1998||Feb 27, 2001||Ball Semiconductor, Inc.||Method for circuit design on a spherical semiconductor having critical dimensions|
|US6223334 *||Oct 1, 1998||Apr 24, 2001||Mentor Graphics Corporation||Automatic topology synthesis and optimization|
|US6230306||Apr 17, 1998||May 8, 2001||Lsi Logic Corporation||Method and apparatus for minimization of process defects while routing|
|US6247167||Apr 17, 1998||Jun 12, 2001||Lsi Logic Corporation||Method and apparatus for parallel Steiner tree routing|
|US6249902 *||Jan 9, 1998||Jun 19, 2001||Silicon Perspective Corporation||Design hierarchy-based placement|
|US6253363||Apr 17, 1998||Jun 26, 2001||Lsi Logic Corporation||Net routing using basis element decomposition|
|US6260183 *||Apr 17, 1998||Jul 10, 2001||Lsi Logic Corporation||Method and apparatus for coarse global routing|
|US6289495||Apr 17, 1998||Sep 11, 2001||Lsi Logic Corporation||Method and apparatus for local optimization of the global routing|
|US6292929||Nov 22, 1999||Sep 18, 2001||Lsi Logic Corporation||Advanced modular cell placement system|
|US6324674||Apr 17, 1998||Nov 27, 2001||Lsi Logic Corporation||Method and apparatus for parallel simultaneous global and detail routing|
|US6370677 *||Jan 20, 2000||Apr 9, 2002||Xilinx, Inc.||Method and system for maintaining hierarchy throughout the integrated circuit design process|
|US6381731 *||Jan 19, 1999||Apr 30, 2002||Laurence W. Grodd||Placement based design cells injection into an integrated circuit design|
|US6442743 *||Jun 12, 1998||Aug 27, 2002||Monterey Design Systems||Placement method for integrated circuit design using topo-clustering|
|US6466946 *||Jun 7, 2000||Oct 15, 2002||Hewlett-Packard Company||Computer implemented scalable, incremental and parallel clustering based on divide and conquer|
|US6557145||Mar 6, 2001||Apr 29, 2003||Monterey Design Systems, Inc.||Method for design optimization using logical and physical information|
|US6766502 *||Dec 30, 1999||Jul 20, 2004||Intel Corporation||Method and apparatus for routing using deferred merging|
|US6851099||Feb 23, 2000||Feb 1, 2005||Synopsys, Inc.||Placement method for integrated circuit design using topo-clustering|
|US6961916||May 1, 2002||Nov 1, 2005||Synopsys, Inc.||Placement method for integrated circuit design using topo-clustering|
|US6971080||Apr 29, 2002||Nov 29, 2005||Grodd Laurence W||Placement based design cells injection into an integrated circuit design|
|US7146583 *||Aug 6, 2004||Dec 5, 2006||Xilinx, Inc.||Method and system for implementing a circuit design in a tree representation|
|US7210113 *||Apr 23, 2004||Apr 24, 2007||Lsi Logic Corporation||Process and apparatus for placing cells in an IC floorplan|
|US7360177||Aug 6, 2004||Apr 15, 2008||Xilinx, Inc.||Method and arrangement providing for implementation granularity using implementation sets|
|US8099702 *||Jul 30, 2008||Jan 17, 2012||Synopsys, Inc.||Method and apparatus for proximate placement of sequential cells|
|US8141010||Feb 8, 2008||Mar 20, 2012||Xilinx, Inc.||Method and arrangement providing for implementation granularity using implementation sets|
|US8296690||Oct 23, 2012||Xilinx, Inc.||Method and arrangement providing for implementation granularity using implementation sets|
|US8572540 *||Jun 6, 2011||Oct 29, 2013||Cadence Design Systems, Inc.||Method and system for approximate placement in electronic designs|
|US8661388||Oct 1, 2009||Feb 25, 2014||Mediatek Inc.||Method of packing-based macro placement and semiconductor chip using the same|
|US20020124232 *||Apr 29, 2002||Sep 5, 2002||Grodd Laurence W.||Placement based design cells injection into an integrated circuit design|
|US20020138816 *||May 1, 2002||Sep 26, 2002||Majid Sarrafzadeh||Placement method for integrated circuit design using topo-clustering|
|US20050240889 *||Apr 23, 2004||Oct 27, 2005||Lsi Logic Corporation||Process and apparatus for placing cells in an IC floorplan|
|US20070157146 *||Dec 8, 2006||Jul 5, 2007||Mediatek Inc.||Method of packing-based macro placement and semiconductor chip using the same|
|US20100023910 *||Oct 1, 2009||Jan 28, 2010||Mediatek Inc.||Method of packing-based macro placement and semiconductor chip using the same|
|US20100031214 *||Jul 30, 2008||Feb 4, 2010||Synopsys, Inc.||Method and Apparatus for Proximate Placement of Sequential Cells|
|US20110239177 *||Sep 29, 2011||Cadence Design Systems, Inc.||Method and system for approximate placement in electronic designs|
|CN102955869A *||Aug 30, 2011||Mar 6, 2013||国际商业机器公司||Method and device for evaluating clock skew|
|CN102955869B *||Aug 30, 2011||Apr 8, 2015||国际商业机器公司||Method and device for evaluating clock skew|
|WO2001022301A1 *||Sep 22, 1999||Mar 29, 2001||Ball Semiconductor, Inc.||Method for circuit design on a spherical semiconductor having critical dimensions|
|U.S. Classification||716/122, 716/124, 716/123|
|Mar 24, 1995||AS||Assignment|
Owner name: LSI LOGIC CORPORATION
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SCEPANOVIC, RANKO;KOFORD, JAMES S.;KUDRYAVTSEV, VALERIY B.;AND OTHERS;REEL/FRAME:007420/0811;SIGNING DATES FROM 19950127 TO 19950217
|Oct 19, 2000||FPAY||Fee payment|
Year of fee payment: 4
|Sep 2, 2004||FPAY||Fee payment|
Year of fee payment: 8
|Feb 20, 2009||FPAY||Fee payment|
Year of fee payment: 12
|May 8, 2014||AS||Assignment|
Owner name: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AG
Free format text: PATENT SECURITY AGREEMENT;ASSIGNORS:LSI CORPORATION;AGERE SYSTEMS LLC;REEL/FRAME:032856/0031
Effective date: 20140506
|Jun 6, 2014||AS||Assignment|
Owner name: LSI CORPORATION, CALIFORNIA
Free format text: CHANGE OF NAME;ASSIGNOR:LSI LOGIC CORPORATION;REEL/FRAME:033102/0270
Effective date: 20070406
|Apr 3, 2015||AS||Assignment|
Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LSI CORPORATION;REEL/FRAME:035390/0388
Effective date: 20140814
|Feb 2, 2016||AS||Assignment|
Owner name: AGERE SYSTEMS LLC, PENNSYLVANIA
Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031);ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT;REEL/FRAME:037684/0039
Effective date: 20160201
Owner name: LSI CORPORATION, CALIFORNIA
Free format text: TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031);ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT;REEL/FRAME:037684/0039
Effective date: 20160201