|Publication number||US5671257 A|
|Application number||US 08/468,921|
|Publication date||Sep 23, 1997|
|Filing date||Jun 6, 1995|
|Priority date||Jun 6, 1995|
|Also published as||EP0920759A1, EP0920759A4, WO1998012835A1|
|Publication number||08468921, 468921, US 5671257 A, US 5671257A, US-A-5671257, US5671257 A, US5671257A|
|Inventors||Bruce A. Cochran, Ronald D. McCallister|
|Original Assignee||Sicom, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (4), Non-Patent Citations (19), Referenced by (42), Classifications (15), Legal Events (8)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates generally to the field of digital communications. More specifically, the present invention relates to synchronizing digital receivers to symbol timing.
In digital communication receivers, component cost, reliability, and power consumption improvements may be realized by operating at lower clock rates or by requiring fewer components. However, the purpose of a digital communication receiver is to recover transmitted information, and greater amounts of information may be recovered when receivers detect data at higher data rates. Conventionally, operation at higher data rates requires operating at higher clock rates or increasing the number of components while simultaneously operating parallel channels.
One particularly troublesome feature of digital communication receivers has been symbol synchronization. A symbol is a discrete interval of time within which a received signal conveys a unit of data. The unit of data may include one or more bits, and the resulting data rate is proportional to the symbol rate. Conventional digital communication receivers compute symbol synchronization timing errors by detecting points where quadrature components of complex signals experience zero-crossings. Unfortunately, these points are difficult to detect. Consequently, symbol synchronization in conventional digital communication receivers has required an incoming analog signal to be sampled at a rate of two or more complex samples per symbol. However, once symbol synchronization has been achieved only one complex sample per symbol is actually required for data detection. Thus, the symbol synchronization feature has conventionally required digital receivers to operate at a greater clock rate than is required for data detection.
Moreover, the zero-crossing points are the worst possible sampling points within the symbols. Consequently, symbol synchronization occurs when sampling points are driven as far from the zero-crossing points as possible. Unfortunately, this technique leads to sub-optimum operation because the detected feature (i.e. zero-crossing points) is not the signal feature which defines optimal sampling points.
A few prior digital receivers have achieved symbol synchronization using only one complex sample per symbol. However, such digital receivers have been extremely sensitive to carrier synchronization and frequency offsets, such as may be caused by Doppler. In other words, such receivers have been useful only in situations which required carrier synchronization along with rigid control of frequency offsets. These receivers are virtually useless in situations which require fast acquisition or operation in the presence of significant frequency offsets.
Accordingly, it is an advantage of the present invention that an improved symbol synchronization apparatus and method are provided.
Another advantage is that the present invention may digitally recover symbol timing based upon less than two complex samples per symbol.
Another advantage is that the present invention tolerates significant frequency offsets.
Another advantage is that the present invention quickly acquires symbol timing.
The above and other advantages of the present invention are carried out in one form within a digital communication receiver by a method of recovering symbol synchronization timing from an analog signal configured as a stream of symbols. The method generates a clock signal which defines symbol timing. The analog signal is sampled in response to the clock signal to generate a complex sample for each symbol. Magnitude attributes of the complex samples are separated from phase attributes of the complex samples so that the magnitude attributes are substantially insensitive to phase changes. The symbol timing defined by the clock signal is adjusted in response to at least a portion of the magnitude attributes.
A more complete understanding of the present invention may be derived by referring to the detailed description and claims when considered in connection with the Figures, wherein like reference numbers refer to similar items throughout the Figures, and:
FIG. 1 shows a block diagram of a digital communication receiver configured in accordance with the present invention;
FIG. 2 shows a phase constellation diagram;
FIG. 3 shows a timing diagram of an exemplary magnitude signal; and
FIG. 4 shows a timing diagram of an exemplary magnitude signal and a delayed estimate of the magnitude signal.
FIG. 1 shows a block diagram of a digital communication receiver 10. Receiver 10 recovers digital data from an incoming analog carrier signal 12. Carrier signal 12 is configured as a stream of discrete symbol intervals, called symbols below. The symbols are of equivalent duration, and each symbol conveys a unit of data. A unit of data conveys one or more bits. Desirably, signal 12 is modulated using some form of non-constant-envelope modulation, such as M-ary PSK, N-QAM, and the like.
Signal 12 is received at an antenna 14. Antenna 14 couples to an RF section 16. RF section 16 may include RF filtering, a fixed frequency oscillator, down conversion circuits, and other components conventionally included in RF sections of radio receivers. RF section 16 preferably generates an essentially baseband, analog form of signal 12. An output of RF section 16 couples to an input of an analog precondition circuit 18. Circuit 18 includes anti-aliasing filtering, automatic gain control (AGC), and other circuits commonly used to condition an analog signal for digitizing. An output of precondition circuit 18 couples to a signal input of an analog-to-digital (A/D) converter 20. A/D converter 20 digitizes the baseband form of signal 12 into samples which characterize the amplitude of the baseband form of signal 12 at various sampling instants.
An output of a voltage controlled oscillator (VCO) 22 generates a clock signal that defines the timing at which A/D converter 20 samples signal 12. In the preferred embodiment, VCO 22 oscillates at less than two times the symbol rate for signal 12, and preferably at approximately one times the symbol rate. A/D converter 20 takes less than two and preferably just one complex sample for each symbol. A symbol synchronizer configured in accordance with the present invention adjusts the symbol timing so that the complex sample taken for each symbol occurs at a desirable point within the symbol.
An output of A/D converter 20 couples to a quadrature data generator 24. Quadrature data generator 24 converts the digital samples of signal 12 into digital rectangular coordinate characterizations of the signal's I and Q quadrature components. The preferred embodiment uses a well known Hilbert transformation technique to convert sampled carrier data pairs into I and Q data values, but other techniques known to those skilled in the art may be used as well. These I and Q data values express I and Q quadrature components in accordance with a rectangular coordinate system. In the preferred embodiment, quadrature data generator 24 produces one complex sample which includes I and Q data values for each symbol.
Quadrature data generator 24 has an I output and a Q output, each of which couples to a rectangular to polar converter 26. Converter 26 generates phase angle (φ) and magnitude (M) attribute values which correspond to phase relationships expressed between the I and Q quadrature values provided by quadrature data generator 24. In the preferred embodiment, a Cordic conversion process is used in separating phase attributes of complex samples from magnitude attributes, but those skilled in the art can adapt other techniques, such as table look-ups and the like, in particular applications. Converter 26 preferably makes one conversion for each symbol.
A phase output of converter 26 couples to a phase processor 28 and to a data detector 30. Phase processor 28 processes phase values apart from magnitude values to aid in recovering symbol timing. For PSK forms of modulation, data detector 30 uses the phase values obtained from the complex samples to recover the data conveyed by signal 12. For QAM forms of modulation, data detector 30 may additionally use magnitude values, or data detector 30 may alternatively use I and Q values. An output from data detector 30 provides a stream of data corresponding to the data conveyed by signal 12. In addition, data detector 30 may provide soft decision data.
A magnitude output of converter 26 couples to a magnitude processor 32. Magnitude processor 32 processes magnitude values to aid in recovering symbol timing. In particular, magnitude processor 32 receives an enabling input from phase processor 28. This enabling input identifies when to allow magnitude attribute data to influence adjustments made to symbol timing. An output from magnitude processor 32 couples to a running average filter 34, an output of which drives a digital-to-analog (D/A) converter 36. D/A converter 36 has an output which couples to an input of a loop filter 38, and an output of loop filter 38 couples to a control input of VCO 22.
FIG. 2 shows a phase constellation diagram for QPSK modulation. Those skilled in the art will appreciate that FIG. 2 illustrates QPSK modulation as a mere example which aids teaching the present invention and that the present invention is not limited to this form of modulation. FIG. 2 depicts four complex points 40a, 40b, 40c, and 40d. Points 40a-40d illustrate theoretically ideal relationships between inphase (I) and quadrature (Q) components of signal 12 for the purpose of conveying two bits of data in a single symbol. Only one of the relationships depicted by complex points 40a-40d is conveyed during any single symbol. A/D converter 20, quadrature data generator 24, and rectangular to polar converter 26 (see FIG. 1) together generate a complex sample for each symbol which desirably resembles one of points 40a-40d. However, this complex sample invariably fails to precisely equal any of points 40a-40d due to the presence of noise and other factors. Data detector 30 (see FIG. 1) identifies the particular two bits of data being conveyed during a symbol by determining which one of the complex points 40a-40d the complex sample most closely resembles.
In addition to noise, symbol timing is one of the factors that determines how closely the complex samples resemble points 40a-40d. Transition tracks 42, 44, and 46 depict exemplary changes which can occur in I-Q relationships as data conveyed by signal 12 (see FIG. 1) changes from one symbol to the next. If symbol timing is not approximately correct, the complex samples upon which receiver 10 (see FIG. 1) operate may correspond to any location on a transition track 42, 44, or 46 rather than to points 40a-40d. Consequently, the farther a sampling instant is within a symbol from approximately correct symbol timing, the more likely that data detector 30 will generate bad data.
FIG. 2 illustrates that both phase and magnitude attributes of the complex relationship change as signal 12 transitions among points 40a-40d. Unfortunately, the phase attribute may further change due to other normally encountered factors, such as frequency offsets caused by imperfect carrier synchronization, Doppler, and the like. The influence of frequency offsets on the phase attribute makes the use of phase information to determine proper symbol timing undesirable. A significant portion of phase information may characterize frequency offsets rather than legitimate transitions between points 40a-40d. On the other hand, the magnitude attribute changes as signal 12 transitions between points 40a-40d but remains relatively insensitive to frequency offsets.
FIG. 3 shows a timing diagram of an exemplary magnitude component 48 of signal 12 as it transitions from a symbol T-3, through symbols T-2, T-1, and T. FIG. 3 illustrates a particular set of data conveyed by signal 12 during symbols T-3 through T as an example for the purpose of teaching the present invention. Those skilled in the art will appreciate that the present invention is not limited to any particular data combinations. The exemplary data combination depicted in FIG. 3 transitions 0 radians in phase between symbols T-3 and T-2, π2 radians in phase between symbols T-2 and T-1, and π radians between symbols T-1 and T. Thus, magnitude component 48 depicts the magnitude attribute of transition tracks 42, 44, and 46, respectively, shown in FIG. 2.
Desirably, sampling instants 50 are centrally located within the symbols and occur in receiver 10 when signal 12 most closely exhibits the I-Q relationships depicted by points 40a-40d (see FIG. 2). Generally, magnitude changes little when phase changes little, but magnitude generally decreases then increases between sampling instants 50 as phase changes are encountered. Moreover, the amount of decrease and increase becomes more pronounced as the amount of phase change increases.
During transition track 42, magnitude information does not suggest how to adjust the VCO clock signal which defines symbol timing. Moreover, as illustrated in FIG. 3, magnitude may even exhibit a slight increase followed by a slight decrease during track 42, which is opposite to the magnitude signal behavior exhibited during tracks 44 and 46 where greater amounts of phase change are encountered. Accordingly, during track 42, any adjustment to symbol timing based upon magnitude attributes is at least as likely to diverge away from optimum sampling instants as it is to converge toward optimum sampling instants 40. Accordingly, magnitude change situations like those demonstrated by track 42 are defined not to be clock adjustment opportunities.
On the other hand, tracks 44 and 46 illustrate a consistent signal behavior. As sampling instants 50 generally approach the points in time where the magnitude attribute reaches a maximum and move away from the points in time where the magnitude attribute reaches a minimum, then sampling instants 50 are roughly converging upon the optimum points. However, as illustrated at point 52, sampling instants 50 are desirably not timed precisely where the magnitude attribute is maximized. In PSK modulation formats, overshoot or ringing often causes the magnitude attribute to reach a maximum after passing an optimum sampling instant 50. In QAM modulation formats, some data states are conveyed at a reduced magnitude compared to others. Accordingly, magnitude change situations like those demonstrated by tracks 44 and 46 are defined to be clock adjustment opportunities.
Referring back to FIG. 1, phase processor 28 evaluates phase attributes to distinguish clock adjustment opportunities from intervals which are not clock adjustment opportunities. However, phase processor 28 operates upon differential phase, which is relatively insensitive to frequency offsets. In particular, phase values for each symbol are supplied to a one symbol delay element 54 and to a positive input of a subtractor 56. An output of delay element 54 couples to a negative input of subtractor 56. An output of subtractor 56 couples to an absolute value element 58, and an output of absolute value element 58 couples to a "B" input of a comparison element 60. A constant threshold value is applied at an "A" input of comparison element 60. An output of comparison element 60 activates when a phase change value at the "B" input is greater than the threshold value at the "A" input. This output couples to magnitude processor 32.
At a current instant, delay element 54 provides a phase value which was valid for a past instant. In particular, the past instant is one symbol delayed from the current instant. Thus, subtractor 56 determines changes in phase attributes between consecutive symbols. These changes are relatively insensitive to frequency offsets because any frequency offset occurring over an interval of only a single symbol typically causes only a minor phase error. Absolute value element 58 strips away any positive or negative sign information so that raw phase change data are provided to comparison element 60.
Phase processor 28 identifies clock adjustment opportunities in response to phase changes. Larger amounts of phase change occurring in a given unit of time (i.e. one symbol delay) are defined to be clock adjustment opportunities while smaller amounts of phase change are defined not to be clock adjustment opportunities. The threshold value supplied to the "A" input of comparison element 60 sets the threshold which defines the difference between clock adjustment opportunities and "not" clock adjustment opportunities. The precise value for this threshold is not a critical parameter in the present invention. Acceptable results appear to be obtainable so long as the threshold is set greater than π/4 radians, with even better results when the threshold is set to greater than π/2 radians.
The better results are a consequence of greater phase changes. Referring back to FIG. 3, during symbol T, maximum magnitude point 52 occurs significantly after desired sampling instant 50. For amounts of phase change greater than π/2 radians, point 52 occurs at approximately 3/4 the duration of symbol T after the beginning of symbol T.
FIG. 4 shows a timing diagram of exemplary magnitude signal 48 during symbol T (see FIG. 2) while signal 48 follows transition track 46 (see FIGS. 2 and 3). In addition, FIG. 4 shows a delayed estimate 64 of magnitude signal 48. The intersection of delayed estimate signal 64 and magnitude signal 48 occurs approximately in the center of symbol T and is approximately coincident with desired sampling instant 50.
Referring back to FIG. 1, magnitude processor 32 includes a delay element 66 and a subtractor 68. A positive input of subtractor 68 and an input of delay element 66 each receive magnitude attributes of the I-Q relationship for each symbol. An output of delay element 66 couples to a negative input of subtractor 68. An output of subtractor 68 couples to a data input of a data switch 70. The enabling signal provided by comparison element 60 of phase processor 28 is routed to an enable input of data switch 70, and an output of data switch 70 couples to an input of running average filter 34.
For each current instant, delay element 66 produces an estimate of the value exhibited by magnitude signal 48 (see FIG. 4) at a past instant. In the preferred embodiments, delay element 66 is an interpolator which has a fixed delay of one-half the symbol duration. Thus, for each symbol, delay element 66 provides an estimate of the value magnitude signal 48 would have exhibited had it been sampled one-half of a symbol earlier. In the preferred embodiment, a Farrow interpolation structure is used to estimate magnitude between samples, but those skilled in the art can adapt other interpolation and filtering techniques in particular applications. Consequently, delay element 66 generates delay estimate 64 (see FIG. 4) during symbol T.
Referring to FIGS. 1 and 4, those skilled in the art will appreciate that interpolator 66 need not precisely estimate a delayed version of magnitude signal 48 (see FIG. 4). For example, precise magnitude values are less important than the shape of delayed estimate 64 in response to various sampling instants throughout symbol T. For example, this shape causes delayed estimate to reach a maximum value prior to desired sampling point 50 and to reach a minimum value after desired sampling point 50 for the large phase change situation depicted by symbol T.
Subtractor 68 detects changes occurring in magnitude attributes over at least portions of symbols. This magnitude change between the estimated delayed magnitude and the current magnitude is fed through data switch 70 when enabled by phase processor 28. As discussed above, phase processor 28 enables data switch 70 during clock adjustment opportunities. Magnitude processor 32 and running average filter 34 are configured so that magnitude changes occurring while not a clock adjustment opportunity have substantially no influence over symbol timing.
The magnitude change data occurring during clock adjustment opportunities are used in a phase locked loop to adjust symbol timing. In particular, polarities are arranged so that decreasing magnitude changes urge VCO 22 to delay the clock signal so that sampling instant 50 is moved later within a symbol. The decreasing magnitude situation is depicted in the region to the left of desired sampling point 50 in FIG. 4. Likewise, increasing magnitude changes urge VCO 22 to advance the clock signal so that sampling instant 50 is moved earlier. The increasing magnitude situation is depicted in the region to the right of desired sampling point 50 in FIG. 4.
Running average filter 34 and loop filter 38 together insure that the results from any single symbol have only a minor influence over symbol timing and general trends detected by magnitude processor 32 are used to control symbol timing.
In summary, the present invention provides an improved symbol synchronization apparatus and method. The present invention may digitally recover symbol timing based on less than two complex samples per symbol. Significant frequency offsets are tolerated because symbol timing adjustments are based primarily upon magnitude attributes which have been separated from phase attributes of complex samples. Due to tolerance of frequency offsets and to identification of clock adjustment opportunities, the present invention quickly acquires symbol timing.
The present invention has been described above with reference to preferred embodiment. However, those skilled in the art will recognize that changes and modifications may be made in these preferred embodiments without departing from the scope of the present invention. For example, those skilled in the art will appreciate that the digital portions of the present invention may be implemented either using discrete components or within a digital signal processor. In addition, those skilled in the art will appreciate that the duration over which magnitude change is estimated may be extended or reduced, and that if extended, clock adjustment opportunities may be defined as particular phase changes occurring over more than one symbol. These and other changes and modifications which are obvious to those skilled in the art are intended to be included within the scope of the present invention.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4704582 *||Oct 7, 1986||Nov 3, 1987||Motorola, Inc.||Gated demodulator for shaped BPSK signals|
|US4941155 *||Nov 16, 1989||Jul 10, 1990||Bell Communications Research, Inc.||Method and circuitry for symbol timing and frequency offset estimation in time division multiple access radio systems|
|US5151920 *||Sep 10, 1991||Sep 29, 1992||Ncr Corporation||Radio LAN station with improved frame delimiter detection in a spread spectrum environment|
|US5440265 *||Sep 14, 1994||Aug 8, 1995||Sicom, Inc.||Differential/coherent digital demodulator operating at multiple symbol points|
|1||"Intepolation in Digital MOdems-Part I: Fundamentals Gardner, IEE Trans. on Comm " vol. 41, No. 3, Mar. 1993.|
|2||"Interpolation in Digital Modems -Part II: Implementation and Performance. Erup, Gardner, Harris, IEEE " vol.41 No. 6 Jun. 1993.|
|3||"Symbol Synchronizer Performance affected by Non-Ideal Interpolation in Digital Modems in Digital Modems" Bucket and Moeneclaey, IEEE 0-7803-1825 04.|
|4||"Timing Recovery in Digital Synchronous Data Receivers" Mueller and Muller, IEEE Trans. On Comm. vol. 24, No. 5 May 1976.|
|5||*||A Continuously Variable Digital Delay Element. Farrow, C.W. IEEE CH2458 8 88 0000 2641 1988.|
|6||A Continuously Variable Digital Delay Element. Farrow, C.W. IEEE CH2458-8-88-0000-2641 1988.|
|7||*||A New Variable Fractional Sample Delay Filter with Non Linear Interpolation. Liu & Wei. IEEE Trans vol. 39 No. 2 1992.|
|8||A New Variable Fractional Sample Delay Filter with Non-Linear Interpolation. Liu & Wei. IEEE Trans vol. 39 No. 2 1992.|
|9||EDN "Undersmapling Reduces data-acquisition costs for Select Applications" by jeff Kristen et al., pp. 217-228 1990.|
|10||*||EDN Undersmapling Reduces data acquisition costs for Select Applications by jeff Kristen et al., pp. 217 228 1990.|
|11||*||Intepolation in Digital MOdems Part I: Fundamentals Gardner, IEE Trans. on Comm vol. 41, No. 3, Mar. 1993.|
|12||*||Interpolation in Digital Modems Part II: Implementation and Performance. Erup, Gardner, Harris, IEEE vol.41 No. 6 Jun. 1993.|
|13||*||On Sampling Rate, Analog Prefiltering, and Sufficient Statistics for Digital Receivers. Meyr, Oerder, Polydoros IEEE Trans on Comm. vol. 42 No. 12, Dec. 1994.|
|14||*||Symbol Synchronizer Performance affected by Non Ideal Interpolation in Digital Modems in Digital Modems Bucket and Moeneclaey, IEEE 0 7803 1825 0/94.|
|15||*||The Effect of Interpolation on the BER Performance of Narrowbank BPSK and (O) QPSK on Rician FAding Channels Bucket and Moeneclaey. IEEE Trans on Comm. vol 42 11 Nov. 1994.|
|16||The Effect of Interpolation on the BER Performance of Narrowbank BPSK and (O) QPSK on Rician-FAding Channels Bucket and Moeneclaey. IEEE Trans on Comm. vol 42 #11 Nov. 1994.|
|17||*||The Performance of Two Symbols Timing Recovery Algorithms for PSK Demodulators. Cowley and Sabel, IEEE 0090 678/94 1994.|
|18||The Performance of Two Symbols Timing Recovery Algorithms for PSK Demodulators. Cowley and Sabel, IEEE 0090-678/94 1994.|
|19||*||Timing Recovery in Digital Synchronous Data Receivers Mueller and Muller, IEEE Trans. On Comm. vol. 24, No. 5 May 1976.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US5764102 *||Feb 13, 1997||Jun 9, 1998||Sicom, Inc.||Multi-stage symbol synchronization|
|US5862191 *||Jun 10, 1996||Jan 19, 1999||U.S. Philips Corporation||Digital communications receiver that includes a timing recovery device|
|US5892803 *||Aug 5, 1996||Apr 6, 1999||U.S. Philips Corporation||Determination of symbol sample timing using soft decisions|
|US5905767 *||Oct 31, 1996||May 18, 1999||Mitsubishi Denki Kabushiki Kaisha||Timing recovery apparatus and a diversity communication apparatus using the same|
|US5943369 *||Sep 25, 1996||Aug 24, 1999||Thomson Consumer Electronics, Inc.||Timing recovery system for a digital signal processor|
|US6002728 *||Apr 17, 1997||Dec 14, 1999||Itt Manufacturing Enterprises Inc.||Synchronization and tracking in a digital communication system|
|US6041088 *||Jun 10, 1998||Mar 21, 2000||Sicom, Inc.||Rapid synchronization for communication systems|
|US6049575 *||Aug 11, 1998||Apr 11, 2000||U.S. Philips Corporation||Digital communications system comprising a receiver that includes a timing recovery device|
|US6052423 *||Jul 8, 1999||Apr 18, 2000||Itt Manufacturing Enterprises, Inc.||Synchronization and tracking in a digital communication system|
|US6104762 *||Dec 16, 1998||Aug 15, 2000||Mitsubishi Denki Kabushiki Kaisha||Timing recovery apparatus and a diversity communication apparatus using the same|
|US6154510 *||May 3, 1999||Nov 28, 2000||Sicom, Inc.||Symbol timing recovery based on adjusted, phase-selected magnitude values|
|US6377634||Dec 15, 1998||Apr 23, 2002||Nec Corporation||Circuit for reproducing bit timing and method of reproducing bit timing|
|US6377642||Feb 26, 1999||Apr 23, 2002||Cisco Technologies, Inc.||System for clock recovery|
|US6389088||Feb 22, 2000||May 14, 2002||Itt Manufacturing Enterprises, Inc.||Synchronization and tracking in a digital communication system|
|US6415004 *||Jul 30, 1999||Jul 2, 2002||Mitsubishi Denki Kabushiki Kaisha||Phase detector, timing recovery device using the same, and a demodulator using the timing recovery device|
|US6442217||May 22, 2000||Aug 27, 2002||Sicom, Inc.||Digital communication receiver with digital, IF, I-Q balancer|
|US6452948 *||Jun 10, 1998||Sep 17, 2002||Sicom, Inc.||Method for baud-clock phase synchronization in a TDMA digital communications system and apparatus therefor|
|US6621443||Oct 1, 2002||Sep 16, 2003||Smar Res Corp||System and method for an acquisition of data in a particular manner|
|US6674822 *||Oct 16, 2000||Jan 6, 2004||Koninklijke Philips Electronics N.V.||Searching the optimal sampling instant in a TDMA packet transmission system|
|US6724847 *||Sep 6, 2000||Apr 20, 2004||Motorola, Inc.||Feed-forward symbol synchronizer and methods of operation therefor|
|US6850576 *||Feb 5, 2001||Feb 1, 2005||Mitsubishi Denki Kabushiki Kaisha||Method and apparatus for reproducing timing, and a demodulating apparatus that uses the method and apparatus for reproducing timing|
|US7336732 *||Jul 28, 2004||Feb 26, 2008||L-3 Communications Titan Corporation||Carrier frequency detection for signal acquisition|
|US7675998 *||Apr 22, 2005||Mar 9, 2010||Trident Microsystems (Far East) Ltd.||Method and circuit for determining a clock signal sampling instant for symbols of a modulation method|
|US7844017||Feb 25, 2008||Nov 30, 2010||L-3 Communications Titan Corporation||Carrier frequency detection for signal acquisition|
|US8085881 *||Aug 5, 2005||Dec 27, 2011||British Telecommunications Public Limited Company||High data rate demodulation system|
|US8401108 *||Sep 11, 2008||Mar 19, 2013||L-3 Communications Corp||Modulation and demodulation of band-limited signals using near-Nyquist sampling|
|US9712317 *||Oct 20, 2015||Jul 18, 2017||Avago Technologies General Ip (Singapore) Pte. Ltd.||Carrier synchronization appropriate for ALM NFC data transmission|
|US20010031021 *||Feb 5, 2001||Oct 18, 2001||Mitsubishi Denki Kabushiki Kaisha, 2-3, Marunouchi 2-Chome, Chiyoda-Ku, Tokyo, Japan||Method and apparatus for reproducing timing, and a demodulating apparatus that uses the method and apparatus for reproducing timing|
|US20070286317 *||Aug 5, 2005||Dec 13, 2007||Stentiford Frederick W||High Data Rate Demodulation System|
|US20080112509 *||Apr 22, 2005||May 15, 2008||Christian Bock||Method and circuit for determining a clock signal sampling instant for symbols of a modulation method|
|US20080212717 *||Feb 25, 2008||Sep 4, 2008||John Robert Wiss||Carrier frequency detection for signal acquisition|
|US20090003492 *||Aug 4, 2005||Jan 1, 2009||Michael Robert Fitch||High Data Rate Demodulation System|
|EP0912010B1 *||Sep 26, 1997||Dec 31, 2008||Micronas GmbH||Phase locked loop for a receiver of digitally transmitted signals|
|EP0913963A2 *||Oct 23, 1998||May 6, 1999||Mitsubishi Denki Kabushiki Kaisha||Timing phase synchronization detecting circuit and demodulator|
|EP0913963A3 *||Oct 23, 1998||Jan 8, 2003||Mitsubishi Denki Kabushiki Kaisha||Timing phase synchronization detecting circuit and demodulator|
|EP0924892A2 *||Dec 14, 1998||Jun 23, 1999||NEC Corporation||Circuit for reproducing bit timing and method of reproducing bit timing|
|EP0924892A3 *||Dec 14, 1998||Dec 10, 2003||NEC Corporation||Circuit for reproducing bit timing and method of reproducing bit timing|
|EP1085427A2 *||Jun 27, 2000||Mar 21, 2001||Mitsubishi Denki Kabushiki Kaisha||Embedded RAM based digital signal processor|
|EP1085427A3 *||Jun 27, 2000||Aug 24, 2005||Mitsubishi Denki Kabushiki Kaisha||Embedded RAM based digital signal processor|
|WO2000051282A1 *||Feb 25, 2000||Aug 31, 2000||Aironet Wireless Communications, Inc.||System for clock recovery|
|WO2002100035A2 *||Jun 4, 2002||Dec 12, 2002||Infineon Technologies Ag||Method for digitally processing an analogue data stream and a corresponding circuit arrangement|
|WO2002100035A3 *||Jun 4, 2002||Sep 18, 2003||Infineon Technologies Ag||Method for digitally processing an analogue data stream and a corresponding circuit arrangement|
|U.S. Classification||375/355, 327/141|
|International Classification||H04L7/00, H04L7/02, H03L7/087, H04L7/033, H03L7/091|
|Cooperative Classification||H04L7/0334, H04L7/0083, H04L7/0054, H03L7/091, H03L7/087|
|European Classification||H03L7/087, H04L7/033D, H04L7/00D|
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