|Publication number||US5672543 A|
|Application number||US 08/639,677|
|Publication date||Sep 30, 1997|
|Filing date||Apr 29, 1996|
|Priority date||Apr 29, 1996|
|Publication number||08639677, 639677, US 5672543 A, US 5672543A, US-A-5672543, US5672543 A, US5672543A|
|Inventors||Chaur Rong Chang, Po-Tao Chu, Tzu-Min Peng, Kuang-Hui Chang|
|Original Assignee||Taiwan Semiconductor Manufacturing Company, Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (5), Referenced by (23), Classifications (13), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
(1) Field of the Invention
The invention relates to a method of metallization in the fabrication of integrated circuits, and more particularly, to a method of tungsten metallization preventing peeling of the tungsten or underlying glue layer called the volcano defect in the manufacture of integrated circuits.
(2) Description of the Prior Art
Tungsten-plug metallization is well-known in the art. A conventional tungsten plug process of the prior art is illustrated in FIG. 1. Referring now to FIG. 1, there is shown semiconductor substrate 10. A contact hole has been opened through interlevel dielectric layer 20 to source/drain region 14. A titanium glue layer 24 and titanium nitride barrier layer 26 have been deposited over the surface of the substrate and within the contact hole. A layer of tungsten 28 is deposited which will form a plug within the contact hole. The titanium nitride (TIN) barrier layer 26 can prevent the penetration of WF6 gas during the tungsten deposition step. However, the nucleation step of the tungsten chemical vapor deposition (CVD) process has a WF6 gas rich chamber condition. If the WF6 gas penetrates through the TiN layer, the WF6 gas can react with the titanium molecules to form TiF3 gas. The continuous out-gassing of TiF3 through the deposited tungsten film will create a mountain-shaped opening 30 on top of the tungsten film. This is the so-called volcano defect.
If the deposition of the tungsten film is conducted right after the TiN deposition, the volcano defects are more likely to be observed. Voids or cracks 32, due to compressive stress are formed in the TiN film, especially near the sharp corner of the contact hole. The WF6 can easily pass through these voids to react with the underlying titanium. The titanium might also be exposed to the WF6 due to poor step coverage of the TiN film.
In order to compensate for poor step coverage of the TiN film and the strength of the TiN structure near the sharp corner of the contact hole, a Rapid Thermal Annealing (RTA) treatment is inserted between TiN deposition and tungsten deposition. Because of the instrument hardware configuration limitation, the RTA treatment throughput is too low compared with the other processes and the equipment itself is hard to maintain. The RTA treatment becomes a bottleneck for the whole process flow.
Volcano defects have been observed frequently on the scribe lines, seal rings, and bonding pads rather than on the small contact areas. FIG. 2 illustrates a top view of bonding pads 62. Volcano defects 30 can be seen in the area of the bonding pads. The most reasonable explanation for this phenomenon is the stress-induced deformation of the TIN layer during the tungsten film growing step. As we know, tungsten film exhibits strong tensile stress. During the tungsten CVD process, the stress induced deformations are much more severe in the local areas with lengthy steep corners such as the bonding pads, seal rings, and scribe lines. Within these areas, more voids are generated and thus, more volcano defects are formed.
In order to reduce the possibilities for volcano defects, it is necessary to reduce the stress differences between the tungsten film and the underlying Ti/TiN barrier layer. Volcano defects are more likely to be observed when the stress differences between the tungsten film and the barrier layer is high.
U.S. Pat. No. 5,397,742 to Kim teaches the formation by Rapid Thermal Annealing (RTA) of a titanium silicide layer on top of the TiN layer. U.S. patent application Ser. No. 08/297,501 (TS93-039) to S. H. Hsieh filed on Aug. 29, 1994, now U.S. Pat. No. 5,552,339 teaches forming a furnace amorphous silicon layer over the TiN layer. U.S. Pat. No. 5,332,691 to Kinoshita et al teaches forming a highly amorphous silicon-containing tungsten layer over the TiN layer.
A principal object of the present invention is to provide an effective and very manufacturable method of tungsten plug metallization which prevents the volcano defect.
Another object of the invention is to provide a method of tungsten plug metallization which reduces stress differences between the tungsten film and the underlying barrier layer.
Yet another object is to provide a method of tungsten plug metallization which utilizes a stress buffer layer on top of the TiN barrier layer to prevent the volcano defect.
A still further object of the invention is to provide a method of tungsten plug metallization which reduces stress differences between the tungsten film and the underlying barrier layer by utilizing a stress buffer layer on top of the barrier layer.
In accordance with the objects of this invention a new method of metallization using a tungsten plug is achieved. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer covers the semiconductor device structures wherein a contact opening is made through the insulating layer to the semiconductor substrate. A barrier layer is deposited conformally over the surface of the insulating layer and within the contact opening. A stress buffer layer is deposited overlying the barrier layer wherein the stress buffer layer prevents volcano defects. A tungsten plug is formed within the contact opening to complete the formation of the tungsten plug metallization without volcano defects in the fabrication of an integrated circuit device.
In the accompanying drawings forming a material part of this description, there is shown:
FIG. 1 schematically illustrates in cross-sectional representation a conventional tungsten plug process of the prior art.
FIG. 2 schematically illustrates a top view of the bonding pad area of a prior art integrated circuit device including volcano defects.
FIGS. 3 through 8 schematically illustrate in cross-sectional representation a preferred embodiment of the present invention.
FIG. 9 graphically illustrates stress as a function of temperature.
Referring now more particularly to FIG. 3, there is illustrated a portion of a partially completed integrated circuit. There is shown a semiconductor substrate 10, preferably composed of monocrystalline silicon. Source/drain regions 14 are formed as is understood in the art either before or after formation of gate electrodes (not shown).
An interlevel dielectric layer 20, composed of borophosphosilicate glass (BPSG), borosilicate glass (BSG), or phosphosilicate glass (PSG), or the like, is deposited over the surface of the semiconductor device structures to a thickness of between about 5000 to 15,000 Angstroms. A contact hole 22 is opened through the insulating layer to the source/drain region 14 within the semiconductor substrate, as shown in FIG. 4.
Referring now to FIG. 5, a glue layer is deposited conformally over the surface of the insulating layer 20 and within the contact hole 22. The glue layer preferably is composed of titanium 24 and is deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD) to a thickness of between about 500 to 1000 Angstroms. A titanium nitride barrier layer 26 is deposited conformally over the glue layer 24 by CVD or PVD to a thickness of between about 500 to 1500 Angstroms.
Alternatively, a thick layer of titanium could be deposited over the insulating layer 20. The titanium layer is nitrided to form a titanium nitride layer within the top portion of the titanium layer, resulting in titanium layer 24 and titanium nitride layer 26, as shown in FIG. 5.
Volcano defects are believed to result from stress-induced deformation of the TiN barrier layer, as described hereinabove. All reliable thermal treatments to enhance the integrity of the TiN film change the film stress from compressive to tensile. As discussed above, thermal treatment is undesirable because of low throughput. The key feature of the present invention is the introduction of a stress buffer layer having tensile stress which effectively stops the volcano defects.
Referring now to FIG. 6, a cap stress buffer layer 42 having low resistance is deposited conformally over the surface of the barrier layer 26. The stress buffer layer 42 may be composed of tungsten silicide or any other dielectric material such as titanium silicide, cobalt silicide, or the like, and is deposited by CVD to a thickness of between about 500 to 1500 Angstroms. This stress buffer layer 42 provides enough protection of the underlying Ti/TiN barrier layer to prevent volcano defects. This has been proven experimentally.
Referring now to FIG. 7, tungsten 28 is blanket deposited over the surface of the substrate using WF6 as a precursor in a chemical vapor deposition chamber.
Referring now to FIG. 8, the tungsten is etched back to form the tungsten plug 28 within the contact hole. The second metallization 44, such as an aluminum alloy, is deposited and patterned. A passivation layer 46 completes fabrication of the integrated circuit. Of course, other processes may be performed such as an intermetal dielectric deposition and further metallization, as is well known in the art.
The following Example is given to show the important features of the invention and to aid in the understanding thereof. Variations may be made by one skilled in the art without departing from the spirit and scope of the invention.
FIG. 9 graphically illustrates stress as a function of temperature. "+" represents tensile stress and "-" represents compressive stress (as deposited) in FIG. 9 and in Table 1.
In an experiment, the inventors conformally deposited 400 Angstroms of titanium within a contact hole followed by 1000 Angstroms of titanium nitride. Stress was measured in dynes/cm2 for each wafer after the Ti/TiN layer was deposited. This is shown in the second column of Table 1. Four methods of preparing the barrier layer for tungsten deposition were performed, two trials for each method. The first method was a RTA at 640° C. for 1 minute. The second method was a WSix stress buffer layer of the present invention having a thickness of 500 Angstroms. The third method was furnace annealing at 450° C. and the fourth method was a furnace annealing at 660° C. The stress of the barrier layer was measured after each method was complete. Observations to detect volcano defects were made after the tungsten deposition. The results are shown in the following table.
TABLE 1__________________________________________________________________________ after Ti/TiN (dynes/cm2) Furnace Furnacerun depos. stress RTA Invention (450° C.) (660° C.) Volcano Defects__________________________________________________________________________1 -4.272E9 +1.587E10 --2 -4.514E9 +1.548E10 --3 -4.045E9 +6.745E9 --4 -4.731E9 +6.679E9 --5 -4.338E9 +3.6E9 --6 -4.603E9 -2.145E9 ˜15%7 -4.129E9 +1.422E10 --8 -4.338E9 +1.387E10 --__________________________________________________________________________
It can be seen from Table 1 that the process of the present invention as well as the RTA and high temperature furnace annealing processes result in the absence of volcano defects. The low temperature furnace annealing process shows non-uniformity, as evidenced by the large difference in measured stress between the two runs, and also shows the presence of volcano defects.
Although the RTA and high temperature furnace annealing processes result in the prevention of volcano defects, it is desirable to keep the thermal budget as low as possible. The process of the present invention prevents volcano defects and does not increase the thermal budget.
While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5183782 *||Nov 21, 1991||Feb 2, 1993||Sharp Kabushiki Kaisha||Process for fabricating a semiconductor device including a tungsten silicide adhesive layer|
|US5332691 *||May 11, 1993||Jul 26, 1994||Sharp Kabushiki Kaisha||Method of forming a contact|
|US5397742 *||Apr 15, 1994||Mar 14, 1995||Hyundai Electronics Industries Co., Ltd.||Method for forming tungsten plug for metal wiring|
|US5489552 *||Dec 30, 1994||Feb 6, 1996||At&T Corp.||Multiple layer tungsten deposition process|
|US5552339 *||Aug 29, 1994||Sep 3, 1996||Taiwan Semiconductor Manufacturing Company||Furnace amorphous-SI cap layer to prevent tungsten volcano effect|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US6078492 *||Aug 3, 1998||Jun 20, 2000||United Microelectronics Corp.||Structure of a capacitor in a semiconductor device having a self align contact window which has a slanted sidewall|
|US6091148 *||Sep 10, 1997||Jul 18, 2000||Micron Technology Inc||Electrical connection for a semiconductor structure|
|US6100186 *||Apr 14, 1998||Aug 8, 2000||Micron Technology, Inc.||Method of selectively forming a contact in a contact hole|
|US6136697 *||Jul 27, 1998||Oct 24, 2000||Acer Semiconductor Manufacturing Inc.||Void-free and volcano-free tungsten-plug for ULSI interconnection|
|US6175155 *||Sep 2, 1999||Jan 16, 2001||Micron Technology, Inc.||Selectively formed contact structure|
|US6200895||Feb 10, 1999||Mar 13, 2001||Micron Technology, Inc.||Method of forming an electrical connection|
|US6261949 *||Apr 6, 1999||Jul 17, 2001||Nec Corporation||Method for manufacturing semiconductor device|
|US6316132 *||Sep 2, 1999||Nov 13, 2001||Xilinx, Inc.||Structure and method for preventing barrier failure|
|US6344411 *||Nov 23, 1998||Feb 5, 2002||Nec Corporation||OHMIC contact plug having an improved crack free tin barrier metal in a contact hole and method of forming the same|
|US6352924||Jun 5, 2000||Mar 5, 2002||Taiwan Semiconductor Manufacturing Company||Rework method for wafers that trigger WCVD backside alarm|
|US6569759 *||Feb 13, 2002||May 27, 2003||Nec Electronics Corporation||Semiconductor device having interconnection implemented by refractory metal nitride layer and refractory metal silicide layer and process of fabrication thereof|
|US6638852||Sep 17, 2001||Oct 28, 2003||Xilinx, Inc.||Structure and method for preventing barrier failure|
|US6787913 *||Oct 12, 2001||Sep 7, 2004||Nec Electronics Corporation||Ohmic contact plug having an improved crack free TiN barrier metal in a contact hole and method of forming the same|
|US7071563 *||Sep 28, 2001||Jul 4, 2006||Agere Systems, Inc.||Barrier layer for interconnect structures of a semiconductor wafer and method for depositing the barrier layer|
|US7129169 *||May 12, 2004||Oct 31, 2006||International Business Machines Corporation||Method for controlling voiding and bridging in silicide formation|
|US7417290||Jan 9, 2006||Aug 26, 2008||International Business Machines Corporation||Air break for improved silicide formation with composite caps|
|US7659199||Apr 4, 2008||Feb 9, 2010||International Business Machines Corporation||Air break for improved silicide formation with composite caps|
|US20020020922 *||Oct 12, 2001||Feb 21, 2002||Nec Corporation||Ohmic contact plug having an improved crack free TiN barrier metal in a contact hole and method of forming the same|
|US20050255699 *||May 12, 2004||Nov 17, 2005||International Business Machines Corporation||Method for controlling voiding and bridging in silicide formation|
|US20070161240 *||Jan 9, 2006||Jul 12, 2007||International Business Machines Corporation||Air break for improved silicide formation with composite caps|
|US20080220604 *||Apr 4, 2008||Sep 11, 2008||International Business Machines Corporation||Air break for improved silicide formation with composite caps|
|US20100301436 *||May 24, 2010||Dec 2, 2010||Fujitsu Semiconductor Limited||Semiconductor device and method for making semiconductor device|
|WO2007080165A1 *||Jan 9, 2007||Jul 19, 2007||International Business Machines Corporation||Air break for improved silicide formation with composite caps|
|U.S. Classification||438/653, 438/644, 257/E21.584, 438/654, 438/643, 257/E21.585, 438/937|
|Cooperative Classification||H01L21/76877, H01L21/76843, Y10S438/937|
|European Classification||H01L21/768C4, H01L21/768C3B|
|Apr 29, 1996||AS||Assignment|
Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., T
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHANG, KUANG-HUI;PENG, TZU-MIN;CHU, PO-TAO;AND OTHERS;REEL/FRAME:007975/0828
Effective date: 19960327
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