Publication number | US5724276 A |

Publication type | Grant |

Application number | US 08/664,628 |

Publication date | Mar 3, 1998 |

Filing date | Jun 17, 1996 |

Priority date | Jun 17, 1996 |

Fee status | Paid |

Publication number | 08664628, 664628, US 5724276 A, US 5724276A, US-A-5724276, US5724276 A, US5724276A |

Inventors | Jonathan S. Rose, Trevor J. Bauer |

Original Assignee | Xilinx, Inc. |

Export Citation | BiBTeX, EndNote, RefMan |

Patent Citations (4), Non-Patent Citations (2), Referenced by (127), Classifications (12), Legal Events (5) | |

External Links: USPTO, USPTO Assignment, Espacenet | |

US 5724276 A

Abstract

The present invention is part of a Field Programmable Gate Array logic block which performs arithmetic functions as well as logic functions. The novel structure includes a small amount of extra hardware which can implement the XOR function as well as several other useful functions. With the invention, one-bit adders can be generated using only a single lookup table, a carry multiplexer, and the extra hardware. N-bit adders can be implemented with N lookup tables. Multipliers, adders, counters, loadable synchronous set-reset counters and many other common functions are all more efficiently implemented with the invention.

Claims(3)

1. A field programmable gate array (FPGA) logic block structure comprising:

a first multiplexer having at least two data inputs and at least one control input;

a second multiplexer having at least two data inputs and at least one control input, said second multiplexer providing a first data input to said first multiplexer;

a first lookup table having a plurality of inputs, said first lookup table providing true and complement output signals, one as a second data input to said first multiplexer and one as a first data input to said second multiplexer;

a second lookup table having a plurality of inputs, said second lookup table providing a second data input to said second multiplexer; and

a plurality of lines accessible from a general interconnect structure of an FPGA, one of said lines providing a control input to said first multiplexer, and other of said lines providing said inputs to said first and second lookup tables.

2. An FPGA logic block structure as in claim 1 further comprising:

a carry multiplexer having at least two data inputs and at least one control input, said carry multiplexer receiving as a first data input a carry-in signal from an upstream carry multiplexer and providing a carryout signal to a location external to said logic block; one of said lines providing a second data input to said carry multiplexer, said carry multiplexer receiving as a control input one of said true and complement output signals.

3. An FPGA logic block structure as in claim 2 wherein said location external to said logic block is a downstream multiplexer.

Description

The invention relates to field programmable integrated circuit devices or FPGAs, particularly to logic blocks which make up the FPGAs.

Since the first FPGA was invented in 1984, variations on the basic FPGA have been devised to let the FPGA do specialized functions more efficiently. Special interconnection lines allow adjacent logic blocks to be connected without taking up general interconnection lines. Hardware allowing the carry function to be fast with respect to addition has been placed between adjacent logic blocks. Thus, prior art FPGAs can implement adders and other arithmetic functions at high speed. However, typically, a prior art structure having lookup tables and a carry chain with multiplexers will require two lookup tables to implement one bit of an adder, one pair of lookup tables and one carry multiplexer being used for each digit of the sum. Two 4-input lookup tables are needed because the full adder requires both the sum (the XOR of the two input signals and the carry-in signal from the next lower order bit) and the carry-propagate signal (the XOR of the two input signals alone) for controlling the carry chain. One 4-input lookup table can implement either the sum or the carry-propagate but not both. For other arithmetic functions such as multiply, the number of lookup tables is greater than two per bit.

FIG. 1a shows part of a prior art logic block that includes a carry chain. A typical logic block in FPGA products available from Xilinx, Inc. includes more structures than those shown in FIG. 1a. Such structures are shown at pages 2-9 through 2-13 of the Xilinx 1994 Data Book available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. Such additional structures are also shown by Hsieh et al in FIG. 9 of U.S. Pat. No. 5,267,187 (docket M-1230). As shown in FIG. 1a, the logic block includes two lookup tables LUT F and LUT G, a carry multiplexer CMUX, and a multiplexer F5 for using the two lookup tables to implement one five-input function.

FIG. 1b shows the structure of FIG. 1a configured to implement one bit of an adder. We see in FIG. 1b that the prior art structure of FIG. 1a requires two lookup tables LUT F and LUT G to process one bit of an adder. When the structure of FIG. 1a is configured as in FIG. 1b to implement addition, a carry-in signal from a lower order bit is applied to the 1 input terminal of carry multiplexer CMUX and to an input terminal G1 of lookup table LUT G. The two input signals ai and bi are applied to two input terminals F0 and F1 of lookup table LUT F and to two input terminals G2 and G3 of LUT G. Either of the input signals ai or bi (shown here as ai) is applied to the 0 input terminal of carry-multiplexer CMUX. Lookup table LUT F is configured to generate the XOR function (ai ⊕ bi) of the signals on the F0 and F1 input terminals. Lookup table LUT G is configured to generate the XOR function (ai ⊕ bi ⊕ carry-in) of G1, G2, and G3. The carry-in signal may be routed through general interconnect to carry-in terminal G1, or as shown in FIG. 9 of U.S. Pat. No. 5,267,187 the carry-in signal may be directly routed to and selected by a multiplexer which receives this signal as an input. Thus lookup table LUT F generates the carry propagate signal for controlling multiplexer CMUX. Lookup table LUT G generates the sum.

The present invention adds a small number of additional circuit elements to the prior art structures. The novel circuit allows a logic block to implement an additional XOR function as well as several other useful functions. With the invention, one bit of an adder can be formed using only a single lookup table, a carry multiplexer, and two multiplexers provided as part of the logic block. Multipliers, adders, counters, and loadable synchronous set-reset counters are all conveniently implemented with the invention. Even though the addition of a multiplexer increases the chip area slightly, the total chip resources required to implement many functions are less than when implemented in prior art structures.

FIG. 1a shows a prior art structure for implementing arithmetic functions requiring carry.

FIG. 1b shows the structure of FIG. 1a configured for implementing one bit of an adder.

FIG. 2a shows a structure according to the invention for implementing arithmetic functions requiring carry.

FIG. 2b shows the structure of FIG. 2a configured to implement an adder.

FIG. 3 shows how the inverted input signal to multiplexer FX is derived.

FIGS. 4a and 4b show logic blocks of the invention configured to generate two bits of a multiplier.

FIG. 5 shows a logic block of the invention configured to generate an 8-bit parity sum.

FIG. 6 shows the logic block of the invention configured to generate one bit of a parallel loadable set/reset counter.

FIG. 2a shows one embodiment of the invention. Many portions of FIG. 2a correspond to those in FIG. 1a and are given the same labels. In addition, Multiplexer FX controlled by memory cell M is provided. Multiplexer FX receives the output signal from LUT G and the inverted output signal from LUT F. The output of Multiplexer FX is provided to multiplexer F5. If memory cell M carries a logic 1, the LUT G output signal is provided to multiplexer F5 and multiplexer F5 functions as in FIG. 1a. If memory cell M carries logic 0, then multiplexer F5 provides a choice of the inverted or noninverted output signal from LUT F as controlled by the signal on line BY. Thus the output signal from multiplexer F5 is the XOR function of the BY signal and the LUT F output signal. The inverted output signal from LUT F, which is represented by the bubble at the 0 input of multiplexer FX, is always available because the output signal is buffered through two inverters, not shown in FIG. 2a, and the inverted value is simply taken from the first inverter. FIG. 3 shows the two inverters I1 and I2 placed in series at the output of lookup table LUT F. The output signal from inverter I1 drives the 0 input terminal of multiplexer FX. The output signal from inverter I2 drives the 0 input terminal of multiplexer F5.

A fundamental advantage of the structure of FIG. 2a is that when multiplexers FX and F5 are used as an XOR gate, lookup table LUT G is available for other functions and thus the chip resources required for the arithmetic function are reduced.

Adder

FIG. 2b shows the structure of FIG. 2a implemented as one bit of an adder (the function shown in FIG. 1b). Portions of the structure not used for the adder function are shown in faint lines and portions which implement the adder are shown in heavy lines. In FIG. 2b, the carry-in signal is applied to line BY and thus controls multiplexer F5. Thus the output of LUT F is the half sum ai ⊕ bi and the output of multiplexer F5 is the full sum ai ⊕ bi ⊕ carry-in.

Multiplier

Consider a 4-bit by 4-bit multiplier for calculating a_{3} a_{2} a_{1} a_{0} times b_{3} b_{2} b_{1} b_{0}. The calculation steps are shown in Table I below:

TABLE I______________________________________ a_{3}a_{2}a_{1}a_{0}times b_{3}b_{2}b_{1}b_{0}a_{3}b_{0}a_{2}b_{0}a_{1}b_{0}a_{0}b_{0}+ a_{3}b_{1}a_{2}b_{1}a_{1}b_{1}a_{0}b_{1}0+ a_{3}b_{2}a_{2}b_{2}a_{1}b_{2}a_{0}b_{2}0 0+ a_{3}b_{3}a_{2}b_{3}a_{1}b_{3}a_{0}b_{3}0 0 0r_{7}r_{6}r_{5}r_{4}r_{3}r_{2}r_{1}r_{0}______________________________________

The configuration of FIG. 4a generates the r1 bit of the multiplication shown in Table I: r1=alb0+a0b1. The circuit of FIG. 4a also generates the carry-out signal to be used as carry-in for the next bit. Lookup table LUT F performs the calculation a1b0 ⊕ a0b1. Lookup table LUT G performs the calculation a0b1. This signal is routed through the FPGA general interconnect structure to the BX input terminal, and is used to generate the carry-out signal sent to the next more significant bit. The inventive structure allows the calculation to be done in two lookup tables. By contrast, with the structure of FIG. 1a, the calculation would require an extra lookup table.

The type of equation generated in FIG. 4a is used repeatedly in a multiplier. FIG. 4b shows generation of r_{3}. In order to understand generation of multiplier bit r_{3}, the steps of Table I are shown in three tables, Tables II through IV, which correspond to calculations performed in FIG. 4b.

TABLE II______________________________________ a_{3}b_{0}a_{2}b_{0}a_{1}b_{0}a_{0}b_{0}+ a_{3}b_{1}a_{2}b_{1}a_{1}b_{1}a_{0}b_{1}0 r_{5}- 1 r_{4}- 1 r_{3}- 1 r_{2}- 1 r_{1}- 1 r_{0}- 1______________________________________

TABLE III______________________________________ a_{3}b_{2}a_{2}b_{2}a_{1}b_{2}a_{0}b_{2}0 0+ a_{3}b_{3}a_{2}b_{3}a_{1}b_{3}a_{0}b_{3}0 0 0r_{7}- 2 r_{6}- 2 r_{5}- 2 r_{4}- 2 r_{3}- 2 r_{2}- 2 r_{1}- 2 r_{0}- 2______________________________________

TABLE IV______________________________________ r_{5}- 1 r_{4}- 1 r_{3}- 1 r_{2}- 1 r_{1}- 1 r_{0}- 1r_{7}- 2 r_{6}- 2 r_{5}- 2 r_{4}- 2 r_{3}- 2 r_{2}- 2 r_{1}- 2 r_{0}- 2r_{7}r_{6}r_{5}r_{4}r_{3}r_{2}r_{1}r_{0}______________________________________

Logic block CLB1 makes the calculation shown in Table II. The signals a2, b1, a3, and b0 are applied to terminals F3 through F0 of lookup table LUT F, which is programmed to make the calculation a2b1 ⊕ a3b0. Lookup table LUT G of CLB1 makes the calculation a2b1 and this result is applied through interconnect lines to terminal BX of logic block CLB1. The carry-in terminal of logic block CLB1 receives the carry-out signal COUTr2-1, which is generated in another logic block not shown. Thus logic block CLB1 generates on its F5 output terminal the function r3-1, which can be seen in Table II to be a3b0 ⊕ a2b1, and generates on its carry-out terminal the r3-1 carry-out signal COUTr3-1.

Similarly, logic block CLB2 makes the calculation shown in Table III. The signals a1, b2, a0, and b3 are applied to the F3 through F0 input terminals of lookup table LUTF and lookup table LUT F is programmed to generated the function alb2 ⊕ a0b3. The carry-in signal from r1-1 is always 0, as can be understood from Table III since a0b2 is always added to 0 and thus produces a logical 0 carry-out value. Thus logic block CLB2 generates in its F5 output terminal the function r3-2, which can be seen in Table III to be a1b2 ⊕ a0b3. Logic block CLB2 generates on its carry-out terminal the r3-1 carry-out signal COUTr3-2.

Results from CLB1 and CLB2 are used in CLB3 to generate the final value r3. Lookup table LUT G is not used and is thus available for other functions. The signals r3-1 and r3-2 are applied to terminals F3 and F2 of lookup table LUT F, and lookup table LUT F is programmed to generate the function r3-1 ⊕ r3-2, which is combined in multiplexers M and F5 with carry-in signal COUTr2 to generate the final output function r3=r3-1 ⊕ r3-2⊕COUTr2.

Thus the invention saves one lookup table in generating bit r1 and three lookup tables in generating bit r3. The larger the arithmetic function, the greater the density increase provided by the multiplexer combination of the invention.

Parity Tree

FIG. 5 shows the structure of FIG. 2 configured to implement an 8-bit wide parity tree. A parity sum of eight data bits d0 through d7 is generated by applying the eight data bits to the input terminals shown. General interconnect of the FPGA (not shown) is used to route the output signal from LUT G (the parity sum d0⊕d1⊕d2⊕d3) to terminal BY for controlling multiplexer F5. Multiplexer F5 receives inverted and noninverted parity sums d4⊕d5⊕d6⊕d7. Thus the output signal P of multiplexer F5 is the parity sum of the eight data bits d0⊕d1⊕d2⊕d3⊕d4⊕d5⊕d6⊕d7.

Complex Counter

FIG. 6 shows the structure of FIG. 2 used to implement one bit of a parallel loadable counter with a set/reset signal. Lookup table LUT G is programmed with the truth table G=(G3.G2+G3.G0).G1. This truth table causes G1 to be a reset signal. (The truth table G=(G3.G2+G3.G0)+G1 would cause G1 to serve as a set signal.) The reset signal is applied to terminal G1. If reset is logical 1, then G1 is logical 0 and the output of lookup table LUT G is logical 0 regardless of other input signals. If reset is logical 0 then other signals control the output value.

Typically the set/reset signal is globally controlled and thus resets all bits in the counter.

The Load/Count signal on G3 determines whether the counter will load a new value into the counter or will continue with a count. If Load/Count is logical 0, a new value is loaded from terminal G2 and if Load/Count is logical 1 then the SUM1 value at terminal GO is stored in flip flop 61. For incrementing the register by 1, logical 0 is applied to each line BX for each bit in the counter, and logical 1 is applied to the carry-in terminal of the least significant bit. Each other bit of the counter receives its carry-in signal from the carry-out of the previous bit. When the counter of FIG. 6 is in its counting mode, SUM1 is passed through LUT G to D flip flop 61. When Load/Count is high, the SUM1 value is always one clock tick ahead of the COUNT value it increments. Lookup table LUT F is programmed to act as a feed through for the COUNT signal. This applies the COUNT value to the CMUX control terminal and to the XOR gate formed by multiplexers FX and F5. The Carry-in signal is applied to the control terminal of the F5 multiplexer, performing the XOR function. Thus the SUM1 signal is the sum of the Carry-in and COUNT values.

Without the extra multiplexer FX to complete the XOR function it would not be possible to separately calculate the sum and also provide both the set/reset and the load function within one logic block. Thus many useful benefits result from the addition of multiplexer FX.

In light of the above description, other embodiments of the invention will become obvious to those skilled in the art. For example, if an FPGA designer does not want to offer the function of five input variables, the two multiplexers can be replaced by an XOR gate.

Patent Citations

Cited Patent | Filing date | Publication date | Applicant | Title |
---|---|---|---|---|

US5267187 * | Sep 11, 1992 | Nov 30, 1993 | Xilinx Inc | Logic structure and circuit for fast carry |

US5436574 * | Nov 12, 1993 | Jul 25, 1995 | Altera Corporation | Universal logic module with arithmetic capabilities |

US5481206 * | Sep 20, 1994 | Jan 2, 1996 | Xilinx, Inc. | Circuit for fast carry and logic |

US5481486 * | Dec 13, 1993 | Jan 2, 1996 | Altera Corporation | Look up table implementation of fast carry arithmetic and exclusive-OR operations |

Non-Patent Citations

Reference | ||
---|---|---|

1 | "The Programmable Logic Data Book", 1994, pp. 2-9 through 2-13, available from Xilinx Inc., 2100 Logic Drive, San Jose, CA 95124. | |

2 | * | The Programmable Logic Data Book , 1994, pp. 2 9 through 2 13, available from Xilinx Inc., 2100 Logic Drive, San Jose, CA 95124. |

Referenced by

Citing Patent | Filing date | Publication date | Applicant | Title |
---|---|---|---|---|

US5889411 * | Mar 14, 1997 | Mar 30, 1999 | Xilinx, Inc. | FPGA having logic element carry chains capable of generating wide XOR functions |

US5907248 * | Feb 9, 1998 | May 25, 1999 | Xilinx, Inc. | FPGA interconnect structure with high-speed high fanout capability |

US5920202 * | Apr 4, 1997 | Jul 6, 1999 | Xilinx, Inc. | Configurable logic element with ability to evaluate five and six input functions |

US5942913 * | Mar 20, 1997 | Aug 24, 1999 | Xilinx, Inc. | FPGA repeatable interconnect structure with bidirectional and unidirectional interconnect lines |

US5963050 * | Mar 24, 1997 | Oct 5, 1999 | Xilinx, Inc. | Configurable logic element with fast feedback paths |

US6051992 * | Apr 1, 1999 | Apr 18, 2000 | Xilinx, Inc. | Configurable logic element with ability to evaluate five and six input functions |

US6107827 * | May 13, 1999 | Aug 22, 2000 | Xilinx, Inc. | FPGA CLE with two independent carry chains |

US6118300 * | Nov 24, 1998 | Sep 12, 2000 | Xilinx, Inc. | Method for implementing large multiplexers with FPGA lookup tables |

US6124731 * | Jan 10, 2000 | Sep 26, 2000 | Xilinx, Inc. | Configurable logic element with ability to evaluate wide logic functions |

US6191610 | May 15, 2000 | Feb 20, 2001 | Xilinx, Inc. | Method for implementing large multiplexers with FPGA lookup tables |

US6201410 | Aug 13, 1999 | Mar 13, 2001 | Xilinx, Inc. | Wide logic gate implemented in an FPGA configurable logic element |

US6204689 | May 27, 1999 | Mar 20, 2001 | Xilinx, Inc. | Input/output interconnect circuit for FPGAs |

US6204690 | May 18, 2000 | Mar 20, 2001 | Xilinx, Inc. | FPGA architecture with offset interconnect lines |

US6288570 * | Oct 3, 2000 | Sep 11, 2001 | Xilinx, Inc. | Logic structure and circuit for fast carry |

US6289400 * | Apr 15, 1998 | Sep 11, 2001 | Infineon Technologies Ag | Electrical control device with configurable control modules |

US6292022 | Jan 11, 2001 | Sep 18, 2001 | Xilinx, Inc. | Interconnect structure for a programmable logic device |

US6362650 * | May 18, 2000 | Mar 26, 2002 | Xilinx, Inc. | Method and apparatus for incorporating a multiplier into an FPGA |

US6397241 * | Dec 18, 1998 | May 28, 2002 | Motorola, Inc. | Multiplier cell and method of computing |

US6427156 * | Jan 21, 1997 | Jul 30, 2002 | Xilinx, Inc. | Configurable logic block with AND gate for efficient multiplication in FPGAS |

US6448808 | Aug 15, 2001 | Sep 10, 2002 | Xilinx, Inc. | Interconnect structure for a programmable logic device |

US6466052 * | May 15, 2001 | Oct 15, 2002 | Xilinx, Inc. | Implementing wide multiplexers in an FPGA using a horizontal chain structure |

US6505337 | Dec 19, 2000 | Jan 7, 2003 | Xilinx, Inc. | Method for implementing large multiplexers with FPGA lookup tables |

US6516332 * | Sep 2, 1997 | Feb 4, 2003 | Siemens Plc | Floating point number data processing means |

US6573749 | Jan 8, 2002 | Jun 3, 2003 | Xilinx, Inc. | Method and apparatus for incorporating a multiplier into an FPGA |

US6671709 | Mar 25, 2002 | Dec 30, 2003 | Motorola, Inc. | Multiplier cell and method of computing |

US6708191 | Jul 9, 2002 | Mar 16, 2004 | Xilinx, Inc. | Configurable logic block with and gate for efficient multiplication in FPGAS |

US6724810 | Nov 17, 2000 | Apr 20, 2004 | Xilinx, Inc. | Method and apparatus for de-spreading spread spectrum signals |

US6798240 | Jan 24, 2003 | Sep 28, 2004 | Altera Corporation | Logic circuitry with shared lookup table |

US6847228 * | Nov 19, 2002 | Jan 25, 2005 | Xilinx, Inc. | Carry logic design having simplified timing modeling for a field programmable gate array |

US6888373 | Feb 11, 2003 | May 3, 2005 | Altera Corporation | Fracturable incomplete look up table for area efficient logic elements |

US6943580 | Feb 10, 2003 | Sep 13, 2005 | Altera Corporation | Fracturable lookup table and logic element |

US6961741 * | Feb 14, 2002 | Nov 1, 2005 | Stmicroelectronics Ltd. | Look-up table apparatus to perform two-bit arithmetic operation including carry generation |

US7030650 | Nov 10, 2004 | Apr 18, 2006 | Altera Corporation | Fracturable incomplete look up table area efficient logic elements |

US7061268 | Mar 15, 2004 | Jun 13, 2006 | Altera Corporation | Initializing a carry chain in a programmable logic device |

US7167021 | Nov 24, 2003 | Jan 23, 2007 | Altera Corporation | Logic device logic modules having improved arithmetic circuitry |

US7185035 | Oct 23, 2003 | Feb 27, 2007 | Altera Corporation | Arithmetic structures for programmable logic devices |

US7205791 | Mar 12, 2004 | Apr 17, 2007 | Altera Corporation | Bypass-able carry chain in a programmable logic device |

US7251672 * | May 15, 2002 | Jul 31, 2007 | Nxp B.V. | Reconfigurable logic device |

US7312632 | May 24, 2007 | Dec 25, 2007 | Altera Corporation | Fracturable lookup table and logic element |

US7317330 | Jul 14, 2004 | Jan 8, 2008 | Altera Corporation | Logic circuitry with shared lookup table |

US7323902 | Jul 25, 2005 | Jan 29, 2008 | Altera Corporation | Fracturable lookup table and logic element |

US7424506 * | Mar 31, 2001 | Sep 9, 2008 | Durham Logistics Llc | Architecture and related methods for efficiently performing complex arithmetic |

US7467175 | Dec 21, 2004 | Dec 16, 2008 | Xilinx, Inc. | Programmable logic device with pipelined DSP slices |

US7467177 | Dec 21, 2004 | Dec 16, 2008 | Xilinx, Inc. | Mathematical circuit with dynamic rounding |

US7472155 | Dec 21, 2004 | Dec 30, 2008 | Xilinx, Inc. | Programmable logic device with cascading DSP slices |

US7475105 * | Jun 15, 2005 | Jan 6, 2009 | Stmicroelectronics Pvt. Ltd. | One bit full adder with sum and carry outputs capable of independent functionalities |

US7480690 | Dec 21, 2004 | Jan 20, 2009 | Xilinx, Inc. | Arithmetic circuit with multiplexed addend inputs |

US7558812 * | Nov 26, 2003 | Jul 7, 2009 | Altera Corporation | Structures for LUT-based arithmetic in PLDs |

US7565388 | Nov 21, 2003 | Jul 21, 2009 | Altera Corporation | Logic cell supporting addition of three binary words |

US7567997 | Dec 21, 2004 | Jul 28, 2009 | Xilinx, Inc. | Applications of cascading DSP slices |

US7617269 * | Aug 3, 2005 | Nov 10, 2009 | Stmicroelectronics Pvt. Ltd. | Logic entity with two outputs for efficient adder and other macro implementations |

US7663400 | Dec 21, 2007 | Feb 16, 2010 | Actel Corporation | Flexible carry scheme for field programmable gate arrays |

US7671625 | Mar 5, 2008 | Mar 2, 2010 | Altera Corporation | Omnibus logic element |

US7772879 | Apr 11, 2008 | Aug 10, 2010 | Actel Corporation | Logic module including versatile adder for FPGA |

US7800401 | Aug 20, 2007 | Sep 21, 2010 | Altera Corporation | Fracturable lookup table and logic element |

US7840627 | May 12, 2006 | Nov 23, 2010 | Xilinx, Inc. | Digital signal processing circuit having input register blocks |

US7840630 | May 12, 2006 | Nov 23, 2010 | Xilinx, Inc. | Arithmetic logic unit circuit |

US7844653 | May 12, 2006 | Nov 30, 2010 | Xilinx, Inc. | Digital signal processing circuit having a pre-adder circuit |

US7849119 | May 12, 2006 | Dec 7, 2010 | Xilinx, Inc. | Digital signal processing circuit having a pattern detector circuit |

US7853632 | May 12, 2006 | Dec 14, 2010 | Xilinx, Inc. | Architectural floorplan for a digital signal processing circuit |

US7853634 | May 12, 2006 | Dec 14, 2010 | Xilinx, Inc. | Digital signal processing circuit having a SIMD circuit |

US7853636 | May 12, 2006 | Dec 14, 2010 | Xilinx, Inc. | Digital signal processing circuit having a pattern detector circuit for convergent rounding |

US7860915 | May 12, 2006 | Dec 28, 2010 | Xilinx, Inc. | Digital signal processing circuit having a pattern circuit for determining termination conditions |

US7865542 | May 12, 2006 | Jan 4, 2011 | Xilinx, Inc. | Digital signal processing block having a wide multiplexer |

US7870182 | May 12, 2006 | Jan 11, 2011 | Xilinx Inc. | Digital signal processing circuit having an adder circuit with carry-outs |

US7872497 | Dec 23, 2009 | Jan 18, 2011 | Actel Corporation | Flexible carry scheme for field programmable gate arrays |

US7880499 * | Jun 27, 2007 | Feb 1, 2011 | Achronix Semiconductor Corporation | Reconfigurable logic fabrics for integrated circuits and systems and methods for configuring reconfigurable logic fabrics |

US7882165 | Apr 21, 2006 | Feb 1, 2011 | Xilinx, Inc. | Digital signal processing element having an arithmetic logic unit |

US7900078 | Sep 14, 2009 | Mar 1, 2011 | Achronix Semiconductor Corporation | Asynchronous conversion circuitry apparatus, systems, and methods |

US7911230 | Apr 16, 2009 | Mar 22, 2011 | Altera Corporation | Omnibus logic element for packing or fracturing |

US8078899 | Feb 8, 2011 | Dec 13, 2011 | Achronix Semiconductor Corporation | Asynchronous conversion circuitry apparatus, systems, and methods |

US8085064 | Jun 25, 2010 | Dec 27, 2011 | Actel Corporation | Logic module including versatile adder for FPGA |

US8099540 * | Oct 11, 2006 | Jan 17, 2012 | Fujitsu Semiconductor Limited | Reconfigurable circuit |

US8125242 | Jan 17, 2011 | Feb 28, 2012 | Achronix Semiconductor Corporation | Reconfigurable logic fabrics for integrated circuits and systems and methods for configuring reconfigurable logic fabrics |

US8217678 | Jul 12, 2010 | Jul 10, 2012 | Altera Corporation | Fracturable lookup table and logic element |

US8237465 * | Mar 17, 2011 | Aug 7, 2012 | Altera Corporation | Omnibus logic element for packing or fracturing |

US8244791 | Jan 30, 2008 | Aug 14, 2012 | Actel Corporation | Fast carry lookahead circuits |

US8300635 | Sep 10, 2009 | Oct 30, 2012 | Achronix Semiconductor Corporation | Programmable crossbar structures in asynchronous systems |

US8352532 * | Aug 20, 2009 | Jan 8, 2013 | Xilinx, Inc. | Circuit structure for multiplying numbers using look-up tables and adders |

US8479133 | Apr 6, 2009 | Jul 2, 2013 | Xilinx, Inc. | Method of and circuit for implementing a filter in an integrated circuit |

US8495122 | Dec 21, 2004 | Jul 23, 2013 | Xilinx, Inc. | Programmable device with dynamic DSP architecture |

US8543635 | Jan 27, 2009 | Sep 24, 2013 | Xilinx, Inc. | Digital signal processing block with preadder stage |

US8575959 | Jan 19, 2012 | Nov 5, 2013 | Achronix Semiconductor Corporation | Reconfigurable logic fabrics for integrated circuits and systems and methods for configuring reconfigurable logic fabrics |

US8593174 | Jun 29, 2012 | Nov 26, 2013 | Altera Corporation | Omnibus logic element for packing or fracturing |

US8788550 | Jun 12, 2009 | Jul 22, 2014 | Altera Corporation | Structures for LUT-based arithmetic in PLDs |

US8878567 | Oct 24, 2013 | Nov 4, 2014 | Altera Corporation | Omnibus logic element |

US8949759 | Nov 4, 2013 | Feb 3, 2015 | Achronix Semiconductor Corporation | |

US9496875 | Sep 30, 2014 | Nov 15, 2016 | Altera Corporation | Omnibus logic element |

US20020116426 * | Feb 14, 2002 | Aug 22, 2002 | Stmicroelectronics Ltd. | Look-up table apparatus to perform two-bit arithmetic operation including carry generation |

US20020169812 * | Mar 31, 2001 | Nov 14, 2002 | Orchard John T. | Architecture and related methods for efficiently performing complex arithmetic |

US20040145942 * | May 15, 2002 | Jul 29, 2004 | Katarzyna Leijten-Nowak | Reconfigurable logic device |

US20040155676 * | Feb 11, 2003 | Aug 12, 2004 | Sinan Kaptanoglu | Fracturable incomplete look up table for area efficient logic elements |

US20050030062 * | Jul 14, 2004 | Feb 10, 2005 | Bruce Pedersen | Logic circuitry with shared lookup table |

US20050144210 * | Dec 21, 2004 | Jun 30, 2005 | Xilinx, Inc. | Programmable logic device with dynamic DSP architecture |

US20050144211 * | Dec 21, 2004 | Jun 30, 2005 | Xilinx, Inc. | Programmable logic device with pipelined DSP slices |

US20050144212 * | Dec 21, 2004 | Jun 30, 2005 | Xilinx, Inc. | Programmable logic device with cascading DSP slices |

US20050144213 * | Dec 21, 2004 | Jun 30, 2005 | Xilinx, Inc. | Mathematical circuit with dynamic rounding |

US20050144215 * | Dec 21, 2004 | Jun 30, 2005 | Xilinx, Inc. | Applications of cascading DSP slices |

US20050144216 * | Dec 21, 2004 | Jun 30, 2005 | Xilinx, Inc. | Arithmetic circuit with multiplexed addend inputs |

US20050289211 * | Jun 15, 2005 | Dec 29, 2005 | Stmicroelectronics Pvt.Ltd. | One bit full adder with sum and carry outputs capable of independent functionalities |

US20060017460 * | Jul 25, 2005 | Jan 26, 2006 | Altera Corporation | Fracturable lookup table and logic element |

US20060059222 * | Aug 3, 2005 | Mar 16, 2006 | Stmicroelectronics Pvt. Ltd. | Logic entity with two outputs for efficient adder and other macro implementations |

US20060190516 * | Apr 21, 2006 | Aug 24, 2006 | Xilinx, Inc. | Digital signal processing element having an arithmetic logic unit |

US20060195496 * | May 12, 2006 | Aug 31, 2006 | Xilinx, Inc. | Digital signal processing circuit having a pattern detector circuit |

US20060212499 * | May 12, 2006 | Sep 21, 2006 | Xilinx, Inc. | Digital signal processing block having a wide multiplexer |

US20060230092 * | May 12, 2006 | Oct 12, 2006 | Xilinx, Inc. | Architectural floorplan for a digital signal processing circuit |

US20060230093 * | May 12, 2006 | Oct 12, 2006 | Xilinx, Inc. | Digital signal processing circuit having a pattern detector circuit for convergent rounding |

US20060230094 * | May 12, 2006 | Oct 12, 2006 | Xilinx, Inc. | Digital signal processing circuit having input register blocks |

US20060230095 * | May 12, 2006 | Oct 12, 2006 | Xilinx, Inc. | Digital signal processing circuit having a pre-adder circuit |

US20060230096 * | May 12, 2006 | Oct 12, 2006 | Xilinx, Inc. | Digital signal processing circuit having an adder circuit with carry-outs |

US20060288069 * | May 12, 2006 | Dec 21, 2006 | Xilinx, Inc. | Digital signal processing circuit having a SIMD circuit |

US20060288070 * | May 12, 2006 | Dec 21, 2006 | Xilinx, Inc. | Digital signal processing circuit having a pattern circuit for determining termination conditions |

US20070222477 * | May 24, 2007 | Sep 27, 2007 | Altera Corporation | Fracturable lookup table and logic element |

US20070230336 * | Oct 11, 2006 | Oct 4, 2007 | Fujitsu Limited | Reconfigurable circuit |

US20100013517 * | Jun 27, 2007 | Jan 21, 2010 | Rajit Manohar | |

US20100100864 * | Dec 23, 2009 | Apr 22, 2010 | Actel Corporation | Flexible carry scheme for field programmable gate arrays |

US20100191786 * | Jan 27, 2009 | Jul 29, 2010 | Xilinx, Inc. | Digital signal processing block with preadder stage |

US20100192118 * | Apr 6, 2009 | Jul 29, 2010 | Xilinx, Inc. | Method of and circuit for implementing a filter in an integrated circuit |

US20100271068 * | Jun 25, 2010 | Oct 28, 2010 | Actel Corporation | Logic module including versatile adder for fpga |

US20110058570 * | Sep 10, 2009 | Mar 10, 2011 | Virantha Ekanayake | Programmable crossbar structures in asynchronous systems |

US20110062987 * | Sep 14, 2009 | Mar 17, 2011 | Rajit Manohar | Asynchronous conversion circuitry apparatus, systems, and methods |

US20110130171 * | Feb 8, 2011 | Jun 2, 2011 | Achronix Semiconductor Corporation | Asynchronous conversion circuitry apparatus, systems, and methods |

US20110169524 * | Jan 17, 2011 | Jul 14, 2011 | Achronix Semiconductor Corporation. | |

CN1540865B | Feb 9, 2004 | May 12, 2010 | 阿尔特拉公司 | Logic element and manufacturing method thereof, programmable logic device and data processing system |

EP2550593A2 * | Mar 22, 2011 | Jan 30, 2013 | Altera Corporation | Look up table structure supporting quaternary adders |

EP2550593A4 * | Mar 22, 2011 | Mar 5, 2014 | Altera Corp | Look up table structure supporting quaternary adders |

WO2009100564A1 * | Jan 30, 2008 | Aug 20, 2009 | Agate Logic (Beijing), Inc. | An integrated circuit with improved logic cells |

Classifications

U.S. Classification | 708/235, 708/700 |

International Classification | G06F7/575, G06F7/50, G06F7/505 |

Cooperative Classification | G06F2207/4812, G06F7/503, G06F7/575, G06F7/5057 |

European Classification | G06F7/575, G06F7/503, G06F7/505T |

Legal Events

Date | Code | Event | Description |
---|---|---|---|

Jun 17, 1996 | AS | Assignment | Owner name: XILINX, INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ROSE, JONATHAN S.;BAUER, TREVOR J.;REEL/FRAME:008037/0499 Effective date: 19960614 |

Aug 16, 2001 | FPAY | Fee payment | Year of fee payment: 4 |

Sep 12, 2005 | SULP | Surcharge for late payment | Year of fee payment: 7 |

Sep 12, 2005 | FPAY | Fee payment | Year of fee payment: 8 |

Aug 18, 2009 | FPAY | Fee payment | Year of fee payment: 12 |

Rotate