|Publication number||US5724538 A|
|Application number||US 08/607,622|
|Publication date||Mar 3, 1998|
|Filing date||Feb 27, 1996|
|Priority date||Apr 8, 1993|
|Also published as||DE4410060A1, DE4410060B4|
|Publication number||08607622, 607622, US 5724538 A, US 5724538A, US-A-5724538, US5724538 A, US5724538A|
|Inventors||Dale C. Morris, Jerome C. Huck, William R. Bryg|
|Original Assignee||Hewlett-Packard Company|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (5), Referenced by (64), Classifications (7), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This is a continuation of application Ser. No. 08/044,854 filed on Apr. 8, 1993, now abandoned.
The present invention relates to the design of computer systems incorporating virtual memory and more particularly to computers that utilize translation lookaside buffers (TLBs) in the translation of virtual addresses to physical addresses.
Conventional computer systems use a technique called virtual memory which simulates more memory than actually exists and allows the computer to run several programs concurrently regardless of their size. Concurrent user programs access main memory addresses via virtual addresses assigned by the operating system. The mapping of the virtual addresses to the main memory or the physical addresses is a process known as virtual address translation. Virtual memory translation can be accomplished by any number of techniques so that the processor can access the desired information in the main memory.
The virtual address and physical address spaces are typically divided into equal size blocks of memory called pages and a page table provides the translation between virtual addresses and physical addresses. Page tables can be organized in a number of structures. "Forward-mapped" tables are most easily accessed using the virtual page number as a pointer to the table entry containing the translation. "Reverse-mapped" tables are most easily accessed using the physical page number as a pointer to the table entry Containing the translation. Since there are many more possible virtual page numbers than physical page numbers, forward-mapped tables can be very large and sparse, but fairly easily searched given the virtual page number. A reverse-mapped table contains one entry for each page of physical memory. Since there are a limited number of physical pages, compared to virtual pages, reverse-mapped tables tend to be more efficient storage structures, but more difficult to access given only the virtual page number.
Each page table entry typically contains the virtual address and/or the physical address, and protection and status information concerning the page. Status typically includes information about the type of accesses the page has undergone. For example, a dirty bit indicates there has been a modification to data in the page. Because the page tables are usually large, they are stored in the main memory. Therefore each regular memory access can actually require two accesses, one to obtain the translation and a second to access the physical memory location.
Many computer systems that support virtual address translation use a translation lookaside buffer (TLB). The TLB is a small, fast, associative memory which is usually situated on or in close proximity to the processor unit and stores recently used pairs of virtual and physical addresses. The TLB contains a subset of the translations in the page table and can be accessed much more quickly. When the processing unit needs information from main memory, it sends the virtual address to the TLB. The TLB accepts the virtual address page number and returns a physical page number. The physical page number is combined with low-order address information to access the desired byte or word in main memory.
In most cases the TLB cannot contain the entire page table so that procedures need to be implemented to update the TLB. When a virtual page is accessed, the translation for which is not in the TLB, the page table is accessed to determine the translation of this virtual page number to a physical page number and this information is entered in the TLB. Access to the page table can take twenty times longer than access to the TLB and therefore program execution speed is optimized by keeping the translations being utilized in the TLB.
Most computer systems today use some sort of mass storage, typically a disk, to augment the physical random access (RAM) memory in the computer. This augmentation of main memory enables larger programs to be implemented than if only main memory were available. In addition, disk memory is considerably less expensive than RAM but is also hundreds of times slower. Depending on the length of a program and on the competition with other programs for the main memory, part of a program may reside in main memory and part may reside in the disk memory at any particular point in time. The parts of a program that need to be accessed immediately are brought into main memory while the parts not currently used are left in the disk memory.
As an example, if a single program is two mega-bytes long and used with a computer having one mega-byte of main memory, then there will be two mega-bytes of virtual addresses used by the program. Since the main memory can only hold one mega-byte of information, the remaining one mega-byte of program information would be stored in the disk memory system. So at any one time half of the virtual address can and cannot be mapped to program information in main memory as half of the program fills the available physical memory. The access to the information in main memory occurs normally. That is, the TLB is looked to first to see if it has the translation and if not then the TLB is updated from information in the page table and then the TLB is again referenced to get the translation information.
If access to the information that is not in the main memory occurs, then the TLB is looked to first for the translation which will not be there. Then the page table is referenced to get the translation information to update the TLB. However the page table only has the translations for information in the main memory and therefore will not have the required translation information. This condition is called a page fault. In response to a page fault, the virtual page that is referenced is assigned a physical page and this information is inserted into a page directory. If all physical pages have already been associated with other virtual pages, then a page fault handler needs to select which of the physical pages to reassign to the virtual address page currently being referenced. There are many algorithms for such a choice such as first-in-first-out and least-recently-used algorithms. The page fault handler is typically implemented in software while the TLB update process can be handled either by hardware or software as is well known in the industry.
FIG. 1 illustrates the process described above. In step 112 a virtual address is presented to the TLB. If the translation for that virtual address is in the TLB (TLB hit), then the associated physical address is derived from the TLB and is utilized to access physical memory (step 114). If the translation for that virtual address is not in the TLB (TLB miss), then the translation for that virtual address is looked up in the page directory/table (step 116). If the translation is in the page directory, then this information is inserted in the TLB (step 118) and the virtual address is again presented (step 112). This time there will be a TLB hit so that the resulting physical address is used to access physical memory.
If the virtual address is in a page of virtual addresses for which no page of physical addresses is associated, then there will be no entry for this page in the page directory and a page fault will occur. In this situation, a software page fault handler (step 120) will assign a physical page to the virtual page and update the page table. Then the virtual address is again presented to the TLB and the TLB does not yet have the translation so there will be a TLB miss and the TLB will be updated from the page directory. Then the virtual address is again presented to the TLB and this time a TLB hit is assured so that the resulting physical address is used to access physical memory.
FIG. 2 illustrates a simplified method of accessing an entry in a translation lookaside buffer (TLB) in response to the presentation of a virtual address. For illustration purposes, the illustrated TLB has only one entry whereas a TLB would normally have many more entries. The virtual address is loaded into a register 201. This virtual address is composed of two parts a virtual page number 203 and a physical offset 205. The physical offset 205 is normally the lower 12 bits (bits 11-0) of the address which specify a particular byte within a page. The remaining bits in the register indicate the virtual page number.
The term "page offset" is a term often used in the industry and is synonymous with the term "physical offset" used in describing the present invention. Other bits are often used in uniquely specifying a translation to a physical page number. Such bits include "address space identifier" bits, for example. However, for the purposes of the present invention, all such bits will be considered part of the virtual page number.
For the example illustrated, the virtual page number becomes the virtual tag which supplies one input for the TLB comparator 207. A TLB 209 has two linked parts, a TLB tag 211 and an associated physical page number 213. The TLB tag 211 supplies the second input to the TLB comparator 207 and the comparator compares the TLB tag to the virtual tag. If the tags match, then the comparator indicates a TLB hit and the physical page number 213 is combined with the physical offset 205 to provide the physical (real) memory address. If the tags do not match, then there has been a TLB miss and the TLB miss process described in association with FIG. 1 is employed to update the TLB.
FIG. 3 illustrates the process of retrieving the physical page information given the virtual page number as would be required to update the TLB after a TLB miss. As described above, the virtual to physical mappings are maintained in a page table. For translating a given virtual address to a physical address, one approach is to perform a many-to-one function (hash) on the virtual address to form an index into the page table. This gives a pointer to a linked list of entries. These entries are then searched for a match. To determine a match, the virtual page number is compared to an entry in the page table (virtual tag). If the two are equal, that page table entry provides the physical address translation.
In the example illustrated, a hash function 301 is performed on the virtual page number 203 to form an index. This index is an offset into the page table 303. As shown, the index is 0, that is, the index points to the first entry 305 in the page table. Each entry in the page table consists of multiple parts but typically contains at least a virtual tag 307, a physical page 309 and a pointer 311. If the virtual page number 203 equals the virtual tag 307, then physical page 309 gives the physical (real) memory page address desired. If the virtual tag does not match, then the pointer 311 points to a chain of entries in memory which contain virtual to physical translation information. The additional information contained in the chain is needed as more than one virtual page number can hash to the same page table entry.
As shown, pointer 311 points to a chain segment 313. This chain segment contains the same type of information as the page table. As before, the virtual page number 203 is compared to the next virtual tag 315 to see if there is a match. If a match occurs then the associated physical page 317 gives the address of the physical memory page desired. If a match does not occur, then the pointer 319 is examined to locate the next chain segment, if any. If the pointer 319 does not point to another chain segment, as shown, then a page fault has occurred. A page fault software program is then used, as described in association with FIG. 1, to update the page table.
The above described method works well for systems where the virtual TAG is less than the basic datapath size of the computer or in systems having only one central processing unit (CPU). However if the virtual TAG is larger than the datapath size, then two compares are required to test if the virtual TAG and the virtual page number are the same. This additional compare step reduces the speed of the computer system. In addition, in systems utilizing multiple CPUs, great care must be taken to insure that one CPU does not update the same page table entry that another CPU is testing. Otherwise it is possible for a first CPU to modify a page table entry while a second CPU is performing the second compare step on the same page table entry. This is an unacceptable result and therefore additional hardware would be required to insure conflicts do not occur.
What is needed in the industry is a method and apparatus that allows for virtual tags which are larger than the basic datapath of the computer system without requiring multiple compare steps when testing an entry in the page table.
The present invention provides a method and apparatus for utilizing virtual tags larger than the basic computer datapath without requiring multiple compare operations instead of storing the entire tag in the page table entries, multiple comparisons are avoided by storing a reduced tag. The reduced tag is no larger than the basic datapath size, so only a single compare operation is needed. The reduced tag is formed from the system virtual address by removing some of the bits thereby forming a smaller tag. To maintain uniqueness of the page table entries, the bits removed from the virtual address are used to form an index into the page table.
In a second preferred embodiment, the bits not used to form the reduced tag are combined with other bits from the virtual address to form a hashed index. This hashed index provides for an even distribution of entries in the page table.
In a third preferred embodiment, a hashed tag is formed from the virtual page number bits and the index bits. This hashed tag is no bigger than the basic data width of the computer and is stored in the page table in place of the reduced tag. An index into the page table is designed to maintain the uniqueness of the page table entries.
FIG. 1 illustrates a prior art procedure for responding to virtual addresses that are presented during execution of a program.
FIG. 2 illustrates a prior art method of accessing an entry in a translation lookaside buffer.
FIG. 3 illustrates a prior art method of retrieving physical page information to update a TLB after a TLB miss.
FIG. 4 illustrates a first preferred embodiment of the present invention where index bits are combined with a hashed tag to provide access to the page table.
FIG. 5 illustrates a second preferred embodiment of the present invention where hashed index bits are combined with a hashed tag to provide access to the page table.
FIG. 6 illustrates a third preferred embodiment of the present invention where hashed tags are stored in the page table.
FIG. 7 illustrates an alternate page table format.
A basic feature of the present invention is the splitting up of the virtual page number 203 into two parts. A first part which becomes the reduced tag and a second part which is used as an index. The reduced tag is formed by limiting the bits used for the tag to no more than the width of the basic computer data path. For example, if the computer system has a data width of 32 bits, then the reduced tag would contain no more than 32 bits. Any bits that are not used to form the reduced tag are then used to form a remainder index.
FIG. 4 illustrates a preferred implementation of the present invention for retrieving the physical page information after a TLB miss. As illustrated, the virtual page number 203 is split into two parts; a reduced tag 401 and a remainder index 403. The reduced tag 401 consists of no more bits than the basic data width of the computer. Bits not used to form the reduced tag form the remainder index 403. So if the virtual page number 203 was 36-bits in length, then the reduced tag 401 would be 32-bits long and the remainder index 403 would be 4-bits in length assuming a 32-bit computer data width.
A hash function 405 is performed on the reduced tag 401 to produce a tag index 407. The tag index 407 is combined with the remainder index 403, for example by concatenation, to form a page table index 409. As shown, the page table index is 1 and points to the second entry 411 of the page table 413. Each entry in the page table consists of multiple parts as was previously described in association with FIG. 3. If the reduced tag 401 equals the reduced tag 415, then physical page 417 gives the physical (real) memory page address desired. If the tags 401 and 415 do not match, then the pointer 419 is examined to find the next link in the chain, if any, as was previously described.
This method and apparatus requires the page table to have a minimum number of indices. In this example, since the remainder index 403 is 4-bits in size, the page table must have at least 16 entries. However since page tables are typically much greater in size than this, this constraint does not pose a problem.
FIG. 5 illustrates a second preferred implementation of the present invention. As before, the virtual page number 203 is split into a reduced tag 401 and a remainder index 403. The reduced tag 401 is as wide as the basic data width of the computer. Bits not used to form the reduced tag form the remainder index 403. In the example shown the remainder index is 4-bits long and the reduced tag 401 is 32-bits long.
The 32-bits of the reduced tag 401 are processed by a hash function 405 to produce a tag index 407. A second hash function 501 is performed on the remainder index 403 and "n" bits 503 from the virtual tag 401 where "n" can be 0 to the maximum number of bits in the reduced tag. The output 505 of the second hash function 501 is combined with the tag index 407, for example by concatenation, to form a page table index 507.
By using a second hash function 501, a more even distribution of page table indexes is possible than if only the remainder index 403 bits were used. Ideally the distribution would be such that the first index into the page table would result in a hit. Due to page table size constraints however, a search length into the table of 1.1 is more typical and allows for a reasonable page table size.
The organization and function of the page table 509 is essentially as described in association with FIGS. 3 and 4. However the size of the page table is determined by the number of bits in the output 505 of the second hash function. At a minimum, the output 505 will consist of the number of bits in the remainder index 403. In the minimum case where the remainder index is four bits long and "n"=0, the page table will have 16 entries and will function as described in association with FIG. 4. If "n">0 then the output 505 will be greater than 4-bits and the page table will have 2m entry spaces where m is the number of bits in the output 505. There is not necessarily a direct relationship between "n" and "m" as the second hash function can take any number of bits from the reduced tag and produce one or more additional bits to combine with the remainder index 403 bits. The more bits in the output 505, the more evenly distributed are the pages in the page table.
The "n" bits from the reduced tag can be software configurable such that the number of bits, and the particular bits used, can be selected by software. This allows for the smart configuration of the computer system which is desirable if the virtual address 203 is much larger than the datapath size and therefore the constraints on the page table size becomes a problem.
FIG. 6 illustrates an additional embodiment of the present invention. The operation of the page table lookup process is essentially the same as described in association with FIG. 4 with the following exceptions.
The page table 413 contains "hash tags" 601 and 603 instead of the reduced tags of FIG. 4. These hash tags are formed by taking the index bits 403 and the virtual page number bits 401 and performing a hash function on the bits with the result being no larger than the basic data width of the computer. This hash result is then stored in the page table (601 & 603) in place of the reduced tags described before.
In operation, a page table index 409 is formed as previously discussed. Concurrent with the page table index formation, a hash result 605 is formed by performing a hash function 607 on the index bits 403 and the virtual page number bits 401. This hash function is the same as that used to generate all the hash tags which were stored in the page table. The page table index points to an entry 411 in the page table 413 and the hashed tag 603 is compared 609 to the hash result 605. If the tag 603 and the result 605 match then physical page 417 gives the physical memory page address desired. If there is no match, then the pointer 419 is examined to find the next link in the chain, if any.
This method and apparatus of generating a page table tag is particularly advantageous when the computer operating system can assure that the high order bits in the virtual page number are zeros. For example, if the entire virtual address space is not needed, then some bits can always be zero. This method and apparatus also permits a reduction in the size of the IDX index which improves the efficiency of the page table as the page table minimum size is reduced.
FIG. 7 illustrates one of many possible alternate page table organizations which are useful without departing from the scope of the present invention. In this example, one entry 701 in a page table is shown. This entry has three sets (703, 705 and 707) of reduced tags and physical page entries. The operation of this page table is essentially the same as described in association with FIG. 4 except that three reduced tags (709, 711 and 713) are compared to the virtual page number 401 before the pointer 715 is examined to find the next link, if any.
The above preferred embodiments described all have the advantage of allowing large virtual addresses to be used while eliminating the need for multiple compare steps. Therefore computers implementing the present invention will enjoy the advantages of a large address space without the performance penalties and problems associated with prior art designs. This is a particularly important advancement for high performance computer systems employing multiple CPU each with access to a common physical memory.
Other embodiments of the invention will be apparent to the skilled in the art from a consideration of this specification or practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the invention being indicated by the following claims.
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|U.S. Classification||711/206, 711/207, 711/E12.06|
|International Classification||G06F12/08, G06F12/10|
|Jan 16, 2001||AS||Assignment|
|Aug 31, 2001||FPAY||Fee payment|
Year of fee payment: 4
|Sep 6, 2005||FPAY||Fee payment|
Year of fee payment: 8
|Sep 3, 2009||FPAY||Fee payment|
Year of fee payment: 12
|Sep 22, 2011||AS||Assignment|
Owner name: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P., TEXAS
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Effective date: 20030131