|Publication number||US5734275 A|
|Application number||US 08/683,685|
|Publication date||Mar 31, 1998|
|Filing date||Jul 18, 1996|
|Priority date||Jul 18, 1996|
|Publication number||08683685, 683685, US 5734275 A, US 5734275A, US-A-5734275, US5734275 A, US5734275A|
|Inventors||Benjamin Howard Ashmore, Jr.|
|Original Assignee||Advanced Micro Devices, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (8), Referenced by (11), Classifications (8), Legal Events (9)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
This invention relates to any device having a programmable bit line and more particularly to a sense amplifier for sensing the status of the bit line. The bit line can be programmed within, for example, a programmable logic device (PLD).
2. Description of the Relevant Art
A PLD is a general purpose combinational or sequential digital component whose ultimate function is determined by the designer. There are generally three classes of PLDs denoted as either a programmable gate array (PGA), a programmable logic array (PLA) and a programmable array logic (PAL).
A PGA comprises a matrix of cells spaced from one another by an interconnect network. Each cell can include one or more circuit devices, the function of which is defined by a metallization layer applied at the final stage of manufacture. Absent the programmable metallization layer, a PGA can be stockpiled to await a customer-defined program. The lower density cell layout and higher resistance interconnect is offset by the short design turnaround (i.e., program/functionality completion) time afforded by a PGA.
Unlike PGA, a PAL and PLA achieve programmability not at the metallization layer but mostly in the field. A PLA and PAL is generally programmed at the user site by selectively applying electrical "program" current and/or voltage to the PLA or PAL. The end user can thereby purchase the PLA or PAL and program (or reprogram) the device many times depending upon the desired application.
For sake of brevity, description of a conventional PLD is provided herein in reference to a PLA or PAL. It is understood, however, that the idea of a programmable array having a programmable bit-line output remains consistent for all PLDs regardless of whether the PLD is a PLA, a PAL or a PGA. Further, it is understood that the bit-line voltage state must be sensed in order to determine its programmed output. Each of the aforementioned PLDs must therefore need a sense amplifier which operates not only to sense a bit line state but to do so at high speeds with minimal power consumption.
A PLA and a PAL comprise an array of AND and OR logic gates that can be organized from dedicated logic functions by selectively opening or otherwise altering the interconnections between the gates. Alterations can be accomplished by blowing fusible links or reducing the conductivity of the interconnections by selectively applying a programmable voltage and/or current.
In a PLA or PAL, alterations are performed on the array--the AND array and/or the OR array. A PLA comprises both an AND array and an OR array. A typical PLA device 10 is shown in FIG. 1. Sense amplifiers 12 and 14 are coupled at the output of respective AND and OR arrays 16 and 18. Sense amplifier 12 not only senses but also amplifies the voltage value upon bit lines (BL) 18 which extend from AND array 16. The amplified signal is then applied to word lines (WL) 20 of OR array 18. The OR array, and specifically the bit lines 22 of OR array 18, is responsive to the logic value of word lines 20.
The programmable interconnections of AND array 16 and OR array 18 include not only fuses but also programmable transistors, such as floating-gate MOSFETs and RAM cells. Upon receiving a programmable voltage on their word lines, AND array 16 or OR array 18 respond by making certain interconnections (i.e., programming the array). The word lines associated with AND array 16 are labeled as reference numeral 24. Using a floating-gate MOSFET example, word lines are coupled to the floating-gate of the MOSFET, and bit lines are connected to the drain terminal of the MOSFET. The source terminal is typically connected to a ground supply.
While a PLA includes both AND and OR arrays, a PAL includes only an AND array. The OR array of a PAL is not needed since the sharing of AND outputs ("products") between outputs is not used. A PAL is therefore no longer universal since a fixed allocation of products to OR gate must be chosen.
Regardless of whether the structure includes both an AND array and an OR array, or only an AND array, the structure can replicate any combinational logic using a sum of products (SOP) output. Accordingly, SOP output is shown as reference numeral 26 in FIG. 1. The SOP output can, if desired, be extended by adding clocked flip-flops within a sequential circuit 28. The sequential circuit receives SOP output 26 to create a general-purpose sequencer. A sequencer such as that shown in FIG. 1 allows direct implementation of a synchronous finite state machine with both Moore-type or Mealy-type outputs. The transitions between states in the behavioral specification in the state machine map directly into the product terms of the sequencer. Output from sequential circuit 28, denoted as reference numeral 30, can be fed back either to AND array 16 or OR array 18 depending upon the level of programmability needed.
FIG. 2 illustrates in further detail AND array 16, sense amplifier 12, OR array 18 and sense amplifier 14. AND array 16 receives a series of word line (WL) inputs, both true and complement word line values. Word lines extend as rows across AND array 16 and intersect bit lines (BLs) which extend as columns. A cell 32 is formed at the intersection between word lines and bit lines.
During operation, a high value upon word lines will cause a corresponding cell 32 to form a low resistive path between a ground supply and a corresponding bit lines. Thus, a bit line will go to a low logic value if a single cell 32 along that bit line column is conducting. Conversely, a bit line will transition to a high logic value if all the cells 32 along the bit line are non-conducting. A "programmed" cell 32, according to the present example, is one which will conduct if its associated word line voltage value is high. The operation of cells 34 within OR array 18 can operate in the same fashion as cells 32 within AND array 16.
The difference between high and low logic values on associated bit lines is generally quite small. There is a need to discern that difference and to amplify that difference to a voltage value recognizable to combinational or sequential logic. That need is filled by sense amplifiers 12 and 14 coupled between bit lines and logic devices 36 and 38, respectively. AND array 16 and sense amplifier 12 thereby comprise the combination of cells 32 arranged within a matrix, the output of which is sensed and amplified as input to a series of AND gates 36. Likewise, OR array 18 and sense amplifier 14 form the combination of cells 34 having an output which is sensed and amplified as input to a series of AND gates 38. As defined henceforth, a conducting cell is one which presents a low logic value on its associated bit line. The low logic value is one which is distinguished from a high logic value by the corresponding sense amplifiers 12 or 14.
Referring to FIG. 3, a detailed schematic of an interconnection between a programmable cell and a sense amplifier is illustrated. In the example shown, programmable cells 32a/34a and 32b/34b comprise two programmable read-only memory (PROM) cells useable in either art AND array or an OR array. Cells associated with a single bit line are connected in parallel between that bit line and a ground supply 40. A true and complement word line is forwarded to the cells to activate either a conductive or non-conductive path between the interconnected bit line and ground supply 40. A BIAS transistor 42 includes a source/drain path connected between the bit line and sense amplifier 12/14. The source/drain path is controlled by a BIAS voltage applied to the gate terminal of transistor 42. Typically, BIAS voltage applied to BIAS transistor 42 is constant, and is selected to ensure a constant current source into sense amplifier 12/14. Coupled to the output of sense amplifier 12/14 is typically a buffer 44, the output of which is fed into logic gates. The logic gates can comprise either a series of AND gates or a series of OR gates, depending on whether the cell at issue is within an AND array or an OR array.
Sense amplifiers coupled to the output of AND or OR arrays are fairly well known. A description of a PLD having the aforesaid architecture is provided in reference to U.S. Pat. No. 5,475,321 (herein incorporated by reference). AND and OR arrays associated with modern PLDs are quite large. Specifically, there can be hundreds if not thousands of connections to each bit line. Those connections attribute parasitic capacitance to the bit line which can lessen the responsiveness of the sense amplifier output to transitions of the cells. For example, if most of the cells associated with a bit line are conducting, the associated bit line cannot quickly transition to a high logic value when all of those cells transition to a non-conducting state. Likewise, when the cells are all non-conducting, it may take some time before the associated bit line can transition to a low state if only a few cells become conducting. Thus, the bit line is slew rate sensitive, and has a transition delay proportional to the loading factor of numerous cells coupled thereto. These problems are generally described in reference to U.S. Pat. No. 5,410,268 (herein incorporated by reference).
It is important to maintain large matrices of cells while at the same time minimizing the transition delay associated with those large matrices. It would be desirable for the sense amplifier to sense slight changes in bit line voltages thereby enhancing the speed of the sense operation. However, sensing must be performed with minimal account given to improper transitions or noise upon the bit line. Even in worst case situations where numerous cells are transitioning from a conductive to a non-conductive state, the resulting noise level must not deleteriously effect the true bit line value. More specifically, noise under the worst case scenarios must not cause improper transitions of the sense amplifier. It is therefore desirable that a sense amplifier be designed which is not unduly susceptible to situations where numerous transitions cause imputed noise on the bit line. Given minimal effect of bit line noise on the sense amplifier, the sense amplifier must nonetheless be able to read small, actual (non-noise) voltage fluctuations in the bit line signal. Still further, the desired sense amplifier must not itself impute noise onto the power supply or ground supply conductors attached thereto. An improved sense amplifier is therefore needed which can sense small voltage differences on the bit line at a relatively high rate, can consume minimal power, and can place minimal noise on the power and ground supply conductors.
The problems outlined above are in large part solved by an improved sense amplifier of the present invention. The sense amplifier utilizes a cascode arrangement of transistors connected to each bit line forwarded from a programmable array of cells. The cells are those found in any PLD: either a PGA, a PLA or a PAL. The cascode-connected transistors include a source/drain path through which current from a current source transistor forwards current from a power supply to a current sink transistor. The amount of current being forwarded is dependent upon the size of transistors which form the current supply and current sink. A current sinking, single BIAS N transistor is coupled between the cascode-connected transistors and a ground supply. A pair of current sourcing, parallel-coupled BIAS P transistors are coupled between a power supply and the cascode-connected transistors. The single BIAS N transistor receives a BIAS voltage sufficient to sink current through the cascode transistors from the pair of BIAS P transistors coupled to the power supply. Thus, the pair of BIAS P transistors are configured to receive a BIAS voltage sufficient to source a current equal to the current which the single BIAS N transistor sinks.
The cascode-coupled transistors comprise an amplifying transistor having a gate connected to receive a bit line. The amplifying transistor includes a source/drain path coupled between the parallel-coupled pair of BIAS P transistors and the single BIAS N transistor. Thus, the source/drain path of the amplifying transistor does not connect directly to a ground supply as in conventional designs. Instead, the source/drain path couples to a virtual ground which is regulated to the ground supply by the single BIAS N transistor. The purpose in having a single BIAS N transistor coupled between the ground supply and the bit line ground is to prevent collapse of the bit line and to ensure fast sense operation thereof.
In addition to an amplifying transistor, the cascode-connected transistors also include a pull-up transistor having a gate terminal connected to the source/drain path of the amplifying transistor, and further having a source/drain path connected between the bit line and the sense amplifier output. The amplifying transistor serves to amplify the sense amplifier output relative to the bit line, whereas the pull-up transistor attempts to drive the bit line high when one or more cells connected to the bit line are conducting. When cells are conducting, the bit line is driven low by the direct source/drain path within each cell, causing the amplifying transistor source/drain path to be of large resistive value. The gate terminal of the pull-up transistor is therefore drawn to a high voltage value as a result of a BIAS P transistors pulling the pull-up transistor gate high. An active high on the pull-up transistor gate somewhat counteracts the pull-down effect of conductive cells, and thereby prevents collapse of the bit line toward ground supply. As such, the improved cascode and BIAS P transistor arrangement hereof helps ensure the bit line logic values are approximately near the threshold value of the amplifying transistor. Any slight modification (except for noise) on the bit line voltage will be quickly sensed by the amplifying transistor, the result of which is placed on the sense amplifier output.
According to one embodiment, a diode-configured transistor is coupled between the amplifying transistor source/drain path and the pull-up transistor source/drain path. The diode-coupled transistor is configured having the gate and drain terminals mutually connected to the source/drain path of the amplifying transistor. The source terminal of the diode-coupled transistor is connected to the source/drain path of the pull-up transistor. The diode-coupled transistor serves to channel current from one of the pair of BIAS P transistors to the pull-up transistor source/drain path during times when cells on the bit line are conductive. The diode-coupled transistor is therefore referred to as a "current channeling transistor" which provides current from the pair of BIAS P transistors to the ground supply during times when the cells are conductive. That current substantially equals the current forwarded through the amplifying transistor source/drain path during times when the cells are non-conductive. The current channeling transistor helps ensure against collapse of the bit line to ground when the cells are conducting.
According to another embodiment, an additional current source is provided from the power supply to the source/drain path of the amplifying transistor. The additional current supply is sourced into the amplifying transistor source/drain path which equals the current normally sourced by one of the pair of BIAS P transistors. Utilizing a current channeling transistor causes decoupling of current from one of the pair of BIAS P transistors such that the current must be replicated by current from the additional current source. While the current channeling transistor ensures fairly uniform current from the pair of BIAS P transistors through the pull-up transistors during low bit line conditions, the additional current source (in addition to one of the pair of BIAS transistors) replicates that current through the amplifying transistor during high bit line conditions. Thus, the combination of current steering and additional current sourcing advantageously provides uniform current between the power and ground supplies regardless of the bit line voltage state. Accordingly, current channeling and additional current sourcing maintains substantially uniform power consumption with minimal noise imputed upon the power supplies regardless of the condition being sensed.
According to yet another embodiment, a clipping diode is coupled between the bit line and the virtual ground conductor. The clipping diode comprises a mutually coupled drain and gate terminal of a transistor connected to the bit line, wherein the source of that transistor is connected to a virtual ground conductor. The virtual ground conductor is separated from the ground supply by a single BIAS N transistor, and more specifically a source/drain path of that transistor. Single BIAS N transistor is an n-channel transistor, whereas the pair of BIAS P transistors are p-channel transistors. The clipping diode is used to remove over-voltage noise spikes from the bit line which exceed the threshold of the diode. Noise spikes often occur when a large number of conductive cells transition from a conductive state to a non-conductive state. If a single cell remains conductive, then the bit line must remain low; however, transitioning of a large number of cells to a non-conducting state inadvertently causes a temporary voltage rise on the bit line. Unless that voltage rise is clipped (removed) by the clipping diode, the bit line-imputed noise will translate to a false high voltage read by the sense amplifier. The clipping diode also serves to maintain the bit line voltage near an optimal voltage sense range. By preventing bit line voltage rise above a predetermined amount, the clipping diode maintains the bit line voltage near an amount which ensures fast recovery (and therefore fast subsequent sense times) from large voltage spikes on the bit line.
According to still another embodiment, a pull-down transistor is coupled between the virtual ground (bit line ground) and the ground supply. The pull-down transistor includes a gate terminal connected to the output of a sense amplifier. During times when the sense amplifier output is high (denoting a high bit line) it is necessary to ensure sufficient sinking current from the active amplifying transistor. More specifically, whenever the bit line is high, or above the threshold of the amplifying transistor, the amplifying transistor turns on, and the source of that transistor sinks current from at least one of the pair of BIAS P transistors, and possibly from the additional current supply. There may be a significant amount of current needed to be drawn away from the BIAS transistors by the source of the amplifying transistor, that result being achieved by adding another sinking transistor (pull-down transistor) to the amplifying transistor source-coupled virtual ground. The added ground afforded by the pull-down transistor allows significant amounts of current to be drawn to the amplifying transistor only during times when the bit line is high. If the bit line transitions low, then not only will the amplifying transistor turn off but so will the pull-down transistor. Hard coupling the ground supply to the virtual ground in the later instance is not needed. Accordingly, the pull-down transistor is selectively coupled to the virtual ground depending upon the voltage state of the sense amplifier output.
Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which:
FIG. 1 is a block diagram of a PLD, and more specifically a PLA having an AND array and an OR array;
FIG. 2 is a logic diagram of AND/OR array cells with sense amplified output according to the block diagram of FIG. 1;
FIG. 3 is a circuit schematic of AND/OR array cells coupled to a sense amplifier according to a conventional design;
FIG. 4 is a circuit schematic of a sense amplifier according to one embodiment of the present invention; and
FIG. 5 is a circuit schematic of a sense amplifier according to various alternative embodiments of the present invention.
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.
Turning now to FIG. 4, a circuit schematic of one embodiment of a sense amplifier is shown according to the present invention. Sense amplifier 50 comprises a cascode arrangement of a pull-up transistor 52 and an amplifying transistor 54. Transistors 52 and 54 are preferably n-channel MOS transistors. The gate terminal of pull-up transistor 52 is connected to the source/drain path (specifically, the drain terminal) of amplifying transistor 54. The source/drain path (specifically, the source terminal) of transistor 52 is connected to the bit line as well as the gate terminal of transistor 54. Accordingly, the mutual connections between transistors 52 and 54 comprise a cascode connection coupled between an output of sense amplifier 50 (OUT) and the bit line (BL).
The virtual ground is driven to a ground supply 56 in accordance with a BIAS N voltage applied to an BIAS N transistor 56. BIAS N transistor 56 sinks current through amplifying transistor 54 during times in which a bit line voltage exceeds a turn-on threshold of transistor 54. BIAS N voltage is selected to draw a specified amount of current in accordance with the geometry of BIAS N transistor 56, and more specifically a geometry of BIAS P transistor pairs 58a and 58b as well as BIAS P voltage applied thereto. If bit line goes low (less than the threshold of amplifying transistor 54), node 60 will be drawn to a high voltage value which causes turn-on of pull-up transistor 52. However, if cells coupled to the bit line remain conducting, pull-up transistor will not pull up the bit line to a threshold above the turn on of amplifying transistor 54. Instead, pull-up transistor 52 merely prevents collapse of bit line voltage to the ground supply. Pull-up transistor 52 thereby maintains bit line voltage approximately near the threshold of amplifying transistor 54 in readiness for bit line transition to a high level. The bit line transitions to a high level whenever the cells are no longer conducting, and pull-up transistor 52 moves the bit line voltage above the threshold of amplifying transistor 54. Once transistor is turned on (i.e., placed in the linear or saturation region), a drop in the voltage at node 60 occurs and pull-up transistor 52 turns off. In the instance in which bit line is low, pull-up transistor 52 is active and sense amplifier output (OUT) is also low. However, in instances where bit line is high, then pull-up transistor 52 is inactive and the sense amplifier output is high. Accordingly, output (OUT) follows the bit line (BL) logic state, yet at an amplified voltage level.
An important aspect of sense amplifier 50 is BIAS N transistor 56 as well as the direct connection of amplifying transistor 54 to transistor 56. Instead of connecting amplifier transistor 54 directly to a ground supply, as in conventional designs, amplifying transistor 54 is connected to a virtual ground (BL GND). The virtual ground is regulated by BIAS N voltage applied to BIAS N transistor 56. BIAS N voltage is chosen to sink sufficient current through amplifying transistor 54 during times in which the bit line is high and transistors 58a and 58b are sourcing current through amplifying transistor 54. The gain of BIAS N transistor 56 is specifically chosen to be greater than the gain of BIAS P transistor 58a but less than the cumulative gain of transistors 58a and 58b. Proper sizings of those transistors to achieve the desired gain helps ensure that any active memory element (conductive cell) can initiate a sense condition by pulling the bit line low, or any inactive memory elements can terminate a sense condition by pulling the bit line high. These advantages are provided by careful attention to BIAS voltages (BIAS N and BIAS P) as well as the sizings of transistors 56, 58a and 58b. The input BIAS levels BIAS P and BIAS N are chosen such that p-channel and n-channel devices, respectively, of identical gain will source and supply, respectively, identical currents. Careful attention to the sizing ratios, and gain provided by those ratios, is necessary to ensure proper operation of the bit line approximately near the threshold of transistor 54. Proper sizings and gain of the BIAS transistors thereby enhances the speed by which sense amplifier 50 operates.
Turning now to FIG. 5, various embodiments are provided to the base sense amplifier 50 shown in FIG. 4. The embodiments are provided either in the alternative to one another, or cumulative of each other. Each embodiment is shown in FIG. 5 encircled by a phantom line, and will be discussed henceforth in regard to their unique features.
FIG. 5 illustrates sense amplifier 50 having cascode transistors 52 and 54 as well as BIAS transistors 56, 58a and 58b, similar to those shown in FIG. 4. In addition to the base arrangement of FIG. 4, a current channeling transistor 62 shown in FIG. 5 may be added according to one embodiment. Transistor 62 is essentially configured as a diode having the gate and drain terminals of transistor 62 coupled together to node 60. The source of transistor 62 is connected to the output terminal of sense amplifier 50.
Current channeling transistor 62 performs an important function in that it channels current sent from transistor 58b through transistor 52, and eventually through the conducting transistors of various cells connected to the bit line. Thus, during times when the bit line is low, node 60 is drawn to a high voltage level via transistor 58b, and current flows through current channeling transistor 62. When the bit line is low, a substantial majority of current will be sourced from transistor 58b and transistor 58a. Conversely, when the bit line is high, transistor 54 will turn on and node 60 will drop. A lowering of node 60 will reverse BIAS the diode of current channeling transistor 62 causing the entirety of current flowing through transistor 54 to arise from transistor 58b. Current channeling transistor 62 helps reduce negative voltage swings upon the bit line.
To further aid in maintaining constant current, particularly during times when the bit line is high, an additional current source 64 is provided according to another embodiment. Additional current source 64 preferably provides the current which transistor 58a would normally provide, absent transistor 62. However, since transistor 62 blocks passage of current from transistor 58a during a low voltage at node 60, all current through transistor 54 arises from transistor 58b and, if provided, additional current source 64. Current source 64 comprises a series-connected pair of p-channel and n-channel transistors 66 and 68, respectively. Transistors 66 and 68 are sized to compensate for the loss of current from transistor 58a only during times when node 60 is low. If node 60 is high, then current through transistor 52 will arise from transistors 58a and 58b. Additional current source 64 thereby equalizes the current through amplifying transistor 54 to that of the current through pull-up transistor 52, and thereby draws substantially equal current from the power supply to the ground supply regardless of the bit line voltage state. If not for current channeling transistor 62 connected as a diode, additional current source 64 would not be needed. However, the advantages of the current channeling transistor is needed, and is enhanced by additional current source 64. The combination of transistor 62 and source 64 help ensure, regardless of the bit line state, a constant current through either transistor 52 or (if the bit line is low) transistor 54 (if the bit line is high). A constant current through transistors 52 and 52, regardless of the bit line state, helps ensure a constant draw of current from the power supply and thereby lessens the imputed noise upon that supply. Further, a constant current draw from the power supply substantially eliminates power consumption spikes regardless of the bit line state or transitions of the bit line.
According to yet another embodiment, a clipping transistor 70 is provided. Clipping transistor 70 is configured as a diode, wherein the gate and drain terminals are connected together to the bit line, and the source terminal is connected to the virtual ground. Clipping transistor 70 serves to clip any rising voltage upon the bit line. If the rising voltage of transistor 54 exceeds the forward bias threshold of the diode-coupled transistor 70, then transistor 54 becomes active and the rising voltage is clipped to a pre-defined level. Clipping transistor 70 thereby serves to perform the clipping operation during times when a false rise (resulting from noise) is placed upon the bit line. A false rise generally occurs in large PLDs which have numerous cells within an array. If numerous cells connected to a bit line are in a conductive state, the bit line will be drawn substantially close to ground. However, pull-up transistor 52 helps ensure that the bit line does not collapse fully to ground. Pull-up transistor thereby serves to maintain the bit line near the threshold voltage of transistor 54 so that when the bit line goes high, transistor 54 output quickly transitions high.
Clipping transistor 70 helps reduce the bit line recovery time from overvoltage conditions, whereas the current channeling transistor 62 helps reduce bit line recoery time from undervoltage conditions. Thus, the combination of transistors 62 and 70 ensures a narrow range of voltages upon the bit line, resulting in high speed sensing thereof.
The bit line can be adversely affected if, for example, numerous cells are conducting and all but one cell transitions to a non-conducting state. As many cells become non-conducting, pull-up transistor 54 temporarily drives the bit line high. The pull-up transistor is sized so that significant drive is provided, so that a temporary rise in the bit line voltage occurs during this transitional moment. The aforesaid bit-line-rise problem occurs due to the needed drive strength of pull-up transistor 52. To partially overcome this problem, clipping transistor 70 is presented. In addition, the cascode arrangement of transistors 52 and 54 assures that node 60 fluctuates significantly more than the bit line. Fluctuation margin maintained by the cascode arrangement helps prevent inadvertent transitions of pull-up transistor 52. Thus, small transitions upon transistor 54 gate will not necessarily equate to turn-off conditions at node 60 relative to pull-up transistor 52. Thus, the cascode-configured transistors, in conjunction with clipping transistor 70, is less sensitive to bit-line-rise noise common in large PLDs.
According to another embodiment, an additional pull-down transistor 72 is provided. Pull-down transistor is coupled in parallel with BIAS N transistor 56. Pull-down transistor 72 is active only during when the output (OUT) of the sense amplifier is high. Thus, like BIAS N transistor 56, pull-down transistor 72 is an n-channel transistor.
Pull-down transistor 52 is operably coupled to draw current from the virtual ground only when the sense amplifier output is high. Current is purposefully not drawn from the virtual ground when the output is low. Whenever the bit line transitions high, transistor 54 will turn on and the sense amplifier output will transition high. If the bit line is high, then a need arises for securely coupling the virtual ground to the ground supply. This need is fulfilled by providing an additional pull-down transistor 72 coupled in parallel to BIAS N transistor 56. The additional pull-down ensures the virtual ground is substantially near ground supply and that sufficient current can be drawn through transistor 54. The pull-down transistor 72 (or additional sink transistor) is active only when there is a need to couple a virtual ground near the ground supply. This occurs only when the sense amplifier output is high. When the sense amplifier output is low (i.e., as a result of the bit line being low), then a coupling of the virtual ground to the ground supply is not needed. This is evidenced by the sense amplifier output being low, thereby rendering transistor 72 off.
It will be appreciated to those skilled in the art having the benefit of this disclosure that this invention is believed to be capable of use with any PLD. Furthermore, it is also to be understood that the form of the invention shown and described is to be taken as exemplary, presently preferred embodiments of a sense amplifier embodied upon a PLD. Various modifications and changes may be made without departing from the spirit and scope of the invention as set forth in the claims. It is intended that the following claims be interpreted to embrace all such modifications and changes.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4124899 *||May 23, 1977||Nov 7, 1978||Monolithic Memories, Inc.||Programmable array logic circuit|
|US4899070 *||Jul 13, 1988||Feb 6, 1990||Altera Corporation||Bit line sense amplifier for programmable logic devices|
|US4918341 *||Sep 23, 1988||Apr 17, 1990||Actel Corporaton||High speed static single-ended sense amplifier|
|US5410268 *||Sep 8, 1993||Apr 25, 1995||Advanced Micro Devices, Inc.||Latching zero-power sense amplifier with cascode|
|US5426385 *||Jun 7, 1994||Jun 20, 1995||National Science Council||Double positive feedback loop precharge CMOS single-ended sense amplifier|
|US5475321 *||Jul 6, 1994||Dec 12, 1995||Kabushiki Kaisha Toshiba||Programmable logic device having input transition detector circuit|
|US5592427 *||Jun 6, 1995||Jan 7, 1997||Fujitsu Limited||Semiconductor memory having a sense amplifier with load transistors having different load characteristics|
|US5610540 *||Apr 1, 1996||Mar 11, 1997||Siemens Aktiengesellschaft||Low power sensor amplifier for gain memory cells|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US6809550||Sep 20, 2002||Oct 26, 2004||Atmel Corporation||High speed zero DC power programmable logic device (PLD) architecture|
|US7116594 *||Sep 3, 2004||Oct 3, 2006||International Business Machines Corporation||Sense amplifier circuits and high speed latch circuits using gated diodes|
|US7242629 *||Jul 24, 2006||Jul 10, 2007||International Business Machines Corporation||High speed latch circuits using gated diodes|
|US7542363 *||Mar 18, 2005||Jun 2, 2009||Renesas Technology Corp.||Semiconductor memory device enhancing reliability in data reading|
|US7885132||May 7, 2009||Feb 8, 2011||Renesas Electronics Corporation||Semiconductor memory device enhancing reliability in data reading|
|US8654600||Mar 1, 2011||Feb 18, 2014||Lattice Semiconductor Corporation||Low-voltage current sense amplifier|
|US20050213387 *||Mar 18, 2005||Sep 29, 2005||Renesas Technology Corp.||Semiconductor memory device enhancing reliability in data reading|
|US20060050581 *||Sep 3, 2004||Mar 9, 2006||International Business Machines Corporation||Sense amplifier circuits and high speed latch circuits using gated diodes|
|US20060119382 *||Dec 7, 2004||Jun 8, 2006||Shumarayev Sergey Y||Apparatus and methods for adjusting performance characteristics of programmable logic devices|
|US20090213667 *||May 7, 2009||Aug 27, 2009||Renesas Technology Corporation||Semiconductor memory device enhancing reliability in data reading|
|EP1670140A2 *||Dec 2, 2005||Jun 14, 2006||Altera Corporation||Apparatus and method for adjusting performance characteristics of programmable logic devices|
|U.S. Classification||327/51, 327/50|
|International Classification||G11C7/06, G11C7/12|
|Cooperative Classification||G11C7/12, G11C7/067|
|European Classification||G11C7/12, G11C7/06S|
|Nov 21, 1996||AS||Assignment|
Owner name: ADVANCED MICRO DEVICES, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ASHMORE, BENJAMIN HOWARD JR.;REEL/FRAME:008258/0518
Effective date: 19961112
|Jan 6, 1998||AS||Assignment|
Owner name: VANTIS CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ADVANCED MICRO DEVICES, INC.;REEL/FRAME:009472/0719
Effective date: 19971219
|May 14, 1998||AS||Assignment|
Owner name: VANTIS CORPORATION, CALIFORNIA
Free format text: PATENT ASSIGNMENT AGREEMENT;ASSIGNOR:ADVANCED MICRO DEVICES, INC.;REEL/FRAME:009178/0222
Effective date: 19971219
|Jul 14, 1998||CC||Certificate of correction|
|Aug 29, 2001||FPAY||Fee payment|
Year of fee payment: 4
|Jun 6, 2002||AS||Assignment|
Owner name: LATTICE SEMICONDUCTOR CORPORATION, OREGON
Free format text: MERGER;ASSIGNOR:VANTIS CORPORATION;REEL/FRAME:012937/0738
Effective date: 20020211
|Sep 2, 2005||FPAY||Fee payment|
Year of fee payment: 8
|Aug 21, 2009||FPAY||Fee payment|
Year of fee payment: 12
|Mar 17, 2015||AS||Assignment|
Owner name: JEFFERIES FINANCE LLC, NEW YORK
Free format text: SECURITY INTEREST;ASSIGNORS:LATTICE SEMICONDUCTOR CORPORATION;SIBEAM, INC.;SILICON IMAGE, INC.;AND OTHERS;REEL/FRAME:035220/0048
Effective date: 20150310