Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS5745060 A
Publication typeGrant
Application numberUS 08/600,313
Publication dateApr 28, 1998
Filing dateFeb 12, 1996
Priority dateFeb 12, 1996
Fee statusPaid
Publication number08600313, 600313, US 5745060 A, US 5745060A, US-A-5745060, US5745060 A, US5745060A
InventorsDamien McCartney, John O'Dowd
Original AssigneeAnalog Devices, Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Gain calibration circuitry for an analog to digital converter
US 5745060 A
Abstract
A method, and apparatus, for calibrating a delta sigma modulator. The delta sigma modulator includes an integrating amplifier circuit with an integrating capacitor for producing an output indicative of an amount of charge held on the integration capacitor. During the calibration mode, a feedback signal sampling section samples a feedback signal and transfers packets of charge corresponding to such sampled feedback signal to the integrating capacitor in each modulator cycle and an input signal section samples a calibration signal and transfers packets of charge corresponding to a portion of the calibration signal to the integrating capacitor in each modulator cycle. With such an arrangement, some charge is transferred to the integration capacitor in each modulator cycle thus reducing idle-tones.
Images(9)
Previous page
Next page
Claims(13)
What is claimed is:
1. A delta sigma modulator, comprising:
a feedback signal sampling section for sampling a feedback signal and transferring charge packets corresponding to such sampled feedback signal to a summing node;
an input signal sampling section for sampling a calibration voltage and transferring charge packets corresponding to a fractional portion of the calibration voltage to the summing node.
2. A delta sigma modulator, comprising:
an integrating amplifier circuit, having an integrating capacitor, for producing an output indicative of an amount of charge held on the integration capacitor;
a feedback sampling section for, during a calibration mode, sampling a feedback signal and for transferring charge packets corresponding to such sampled voltage to the integrating capacitor;
an input sampling section for, during the calibration mode, sampling a calibration voltage and transferring charge packets corresponding to a fractional portion of the calibration voltage to the integrating capacitor.
3. A method for calibrating a delta sigma modulator, such modulator having an integrating amplifier circuit with an integrating capacitor for producing an output indicative of an amount of charge held on the integration capacitor, such method comprising the steps of:
sampling a feedback signal and transferring packets of charge corresponding to such sampled feedback signal to the integrating capacitor; and,
sampling a calibration signal and transferring packets of charge corresponding to a fractional portion of the calibration signal to the integrating capacitor.
4. A delta sigma modulator, comprising:
a feedback signal sampling section for sampling a feedback signal and transferring charge packets corresponding to such sampled feedback signal to a summing node;
an input signal sampling section for sampling a calibration voltage and transferring charge packets corresponding to a fractional portion of the calibration voltage to the summing node over periods of time, T, where the total charge transferred over each period of time, T, corresponds to the calibration voltage.
5. A delta sigma modulator, comprising:
an integrating amplifier circuit, having an integrating capacitor, for producing an output indicative of an amount of charge held on the integration capacitor;
a feedback sampling section for, during a calibration mode, sampling a feedback signal and for transferring charge corresponding to such sampled voltage to the integrating capacitor;
an input sampling section for, during the calibration mode, sampling a calibration voltage each modulator cycle and transferring charge corresponding to a fractional portion of the calibration voltage to the summing node over periods of time, T, where the total charge transferred over each period of time, T, corresponds to the calibration voltage.
6. A method for calibrating a delta sigma modulator, such modulator having an integrating amplifier circuit with an integrating capacitor for producing an output indicative of an amount of charge held on the integration capacitor, such method comprising the steps of:
sampling a feedback signal and transferring packets of charge corresponding to such sampled feedback signal to the integrating capacitor; and,
sampling a calibration signal and transferring packets of charge corresponding to a fractional portion of the calibration signal to the integrating capacitor over periods of time, T, where the total charge transferred over each period of time, T, corresponds to the calibration voltage.
7. A delta sigma modulator, comprising:
a feedback signal sampling section for sampling a feedback signal and transferring charge packets corresponding to such sampled feedback signal to a summing node each modulator cycle;
an input signal sampling section having a plurality of capacitors for, during a calibration mode, sampling a calibration voltage with a fractional portion of the plurality of capacitors and transferring charge packets representative of the sampled calibration voltage to the summing node, and for sampling an input voltage, AIN, during a normal operating mode with the plurality of capacitors and transferring change representative of the input voltage to the summing node.
8. A delta sigma modulator, comprising:
a feedback signal sampling section for sampling a feedback signal and transferring charge packets corresponding to such sampled feedback signal to a summing node each modulator cycle;
an input signal sampling section having a plurality of capacitors for, during a calibration mode, sampling a calibration voltage with a portion of the plurality of capacitors and transferring charge packets representative of the sampled calibration voltage to the summing node, and for sampling an input voltage, AIN, during a normal operating mode with the plurality of capacitors and transferring change representative of the input voltage to the summing node; and,
wherein the calibration voltage is sampled by a different one of the plurality of capacitors over a corresponding different portion of a period of time, T, the plurality of capacitors sampling the calibration voltage over the period of time T.
9. An delta sigma modulator, comprising:
a feedback signal sampling section for sampling a feedback signal and transferring charge packets corresponding to such sampled feedback signal to a summing node in each modulator cycle;
an input signal sampling section for sampling a calibration voltage and transferring charge packets corresponding to a fractional portion of the calibration voltage to the summing node in each modulator cycle.
10. A method for calibrating a delta sigma modulator, such modulator having an integrating amplifier circuit with an integrating capacitor for producing an output indicative of an amount of charge held on the integration capacitor, such method comprising the steps of:
sampling a feedback signal and transferring packets of charge corresponding to such sampled feedback signal to the integrating capacitor in each modulator cycle; and,
sampling a calibration signal and transferring packets of charge corresponding to a fractional portion of the calibration signal to the integrating capacitor in each modulator cycle.
11. A delta sigma modulator, comprising:
a feedback signal sampling section for sampling a feedback signal and transferring charge packets corresponding to such sampled feedback signal to a summing node;
an input signal sampling section having a plurality of, N, capacitors for, during a normal mode, simultaneously sampling an input voltage with the plurality of, N, capacitors producing N charge packets and transferring the N charge packets to the summing node and, during a calibration mode, simultaneously sampling a calibration voltage with a subset, n, of the N plurality of capacitors, where n is less than N, producing n charge packets and transferring the n charge packets to the summing node.
12. The delta sigma modulator recited in claim 11 wherein n=1.
13. The delta sigma modulator recited in claim 11 wherein during each of the samplings of the calibration voltage, the subset of capacitors includes a different one, or ones, of the N capacitors, and wherein each of the N capacitors is included in at least one of the samplings of the calibration voltage.
Description
BACKGROUND OF THE INVENTION

This invention relates generally to analog to digital converters and more particularly to calibration circuits and methods adapted for use in over-sampled analog to digital converters.

As is known in the art, analog to digital converters (ADCs) are widely used in converting an analog signal into a corresponding digital signal. During the analog to digital conversion process, however, different types of errors may arise in the ADC. One such error is commonly referred to as the ADC gain error. More particularly, an ADC converts an analog input signal into a series of an N bit binary coded digital words. A reference voltage, VREF, is fed to the ADC. The value of the reference voltage, VREF, establishes the range of input voltage, VIN (i.e., the analog signal being converted). In an ideal (i.e., error free) N-bit ADC, an incremental change, Δ= VREF /2N ! in the input voltage, VIN, will result in the least significant bit (LSB) of the digital word changing by 1 for a unipolar input voltage range. With a bipolar input voltage range, an incremental change Δ'= VREF /2N-1 ! in the input voltage, VIN, will result in the least significant bit (LSB) of the digital word changing by 1.

However, in real ADCs, active device mismatch and other manufacturing imperfections give rise to gain and offset errors. An offset error is evident if, for a zero input voltage, the ADC produces a non-zero digital word for a unipolar range and a code different from 2N-1 for a bipolar range (assuming offset binary coding). Generally, a full-scale error is evident if, with an input voltage equal to VREF, the ADC does not produce a digital word 2N (for both unipolar and bipolar ranges). Thus, the full-scale error is made up of the offset error and a gain, or span, error. Therefore, the gain error is the full-scale error less the offset error and is sometimes expressed as a percentage of the full-scale range of the ADC. Because of such errors, the input voltage that produces an output code of 2N may be greater, or less, than the expected full scale voltage, VFS, by an amount related to the error.

As is also known in the art, various techniques have been developed to calibrate out (i.e., correct for) these offset and gain errors. One technique is with analog circuitry, such as variable resistors in an operational amplifier network. The ADC input is offset and scaled by the network in order that the input signal is pre-conditioned with voltages to result in the ADC producing a zero digital word with a zero input voltage and a digital word 2N with an input voltage equal to VFS.

Another technique is through digital calibration. Here, the calibration sequence involves first applying a zero input to the ADC. Any resulting non-zero digital word is stored as an offset error in an offset register. Next, a calibration voltage VCAL, here VFS, is applied and the digital word produced is stored. The stored digital word is then offset corrected by subtracting from it the contents of the offset register. Now the resulting digital word corresponds to either 2N or 2N-1 output codes depending on whether it is a unipolar or bipolar range. A gain factor may be calculated as the number that when used to multiply the offset corrected conversion result will result in the desired output code. The gain factor is stored in a gain register so that, during normal operation, the results are first offset corrected by subtraction of the offset register and then gain corrected by multiplication by the gain register to produce an error free output code.

As is also known in the art, one type of ADC is an over-sampling ADC where multiple input samples are used to form a single digital word sample of the input signal. One such over-sampling ADC is a delta sigma ADC. One such delta sigma ADC is described in U.S. Pat. No. 5,134,401 issued Jul. 28, 1992 entitled "Delta Sigma Modulator Having Programmable Gain/Attenuation", inventors Damien McCartney and David R. Welland, assigned to the same assignee as the present invention, the contents thereof being incorporated herein by reference. Such modulator is included as modulator 9 in the ADC 10 shown in FIG. 1.

Thus, referring to FIG. 1, modulator 9 includes an input 11 fed by an analog input signal and an input 13 fed by a reference voltage, VREF, as shown. The modulator 9 includes an input signal sampling circuit 12, a feedback signal sampling circuit 14, an integrating amplifier 16 having an integration capacitor CINTGR, a filter 18, a comparator 20, a buffer 22 and a programmable control unit 24 all arranged as shown and described in the above reference U.S. Pat. No. 5,134,401. Thus, the input signal sampling circuit 12 includes four switches S1, S2, S3, S4, and an input capacitor, CIN, arranged as shown, and controlled by binary signals on lines AN, AN, I1R and I2R, respectively as shown. (It is noted that the signal on line AN is the complement of the signal on line AN). Likewise the feedback sampling circuit 14 includes four switches S5, S6, S7, S8, and a reference capacitor, CRF, as shown controlled by binary signals on lines RF, RF, R1R, R2R, respectively, as shown. (It is noted that the signal on line RF is the complement of the signal on line RF). The control signals on lines AN, AN, I1R, I2R, RF, RF, R1R, and R2R are produced by the programmable control unit 24 as described in the above reference U.S. Pat. No. 5,134,401 and such signals are shown for lines RF, AN, I1R, and I2R, in FIGS. 2A, 2B, 2C and 2D, respectively.

In normal operation, the signal on line RF is the basic clock signal for modulator 9 clock, as shown in FIG. 2A. The input voltage of the analog signal AIN is sampled and a charge corresponding to the voltage of the sampled signal is stored on capacitor CIN when switches S1 and S3 are closed (in response to a pulse, logic 1, on lines AN and I1R) and switches S2 and S4 are open (in response to a logic 0 on complementary signal line AN and line I2R). The stored charge is then transferred to input summing node 19 of the integrator 16 when switches S2 and S4 are closed (in response to a pulse, logic 1, on line AN and line I2R) and switches S1 and S3 are open (in response to a logic 0 on lines AN and I1R). The rate at which the samples taken by the input sampler are transferred to the summing node 19 (i.e., the rate that pulses are produced on line I2R) is the rate at which pulses are produced on line AN (and hence on complementary signal line AN). The feedback sampler 14 may add either positive charge or negative charge at input summing node 19 as described in the above referenced U.S. Patent in order to produce a net zero charge at the summing node 19.

The gain of the modulator 9 may be selected in accordance with the ratio of the rate charge stored on capacitor CIN is transferred to the summing node 19 (i.e., the rate of the pulses on line I2R) to the rate charge stored on the capacitor CRF is transferred to the summing node 19, (i.e., the modulator clock rate, that is, the rate of the pulses on line RF). Thus, in FIGS. 2A through 2D the pulses trains on lines RF, AN, I1R and I2R, are shown, respectively, for normal operation of modulator 10 (FIG. 1) with a gain of K, here one. (In FIGS. 4A through 4D, the pulses trains on lines RF, AN, I1R and I2R, are shown, respectively, for normal operation of modulator 10 (FIG. 1) with a gain of 2K, here two). It should also be noted that the falling edges of the signals on lines I1R and I2R occur before the corresponding falling edges of the signals on lines RF and AN, as described in the above referenced U.S. Patent, for making the charge-injection associated with switch opening signal independent. In a given phase of the signal on line RF, the modulator 9 output determines whether the signal on line R1R is active or whether the signal on line R2R is active. This is how a feedback corresponding to VREF or to -VREF is achieved, where VREF is the magnitude of the feedback signal produced by modulator 9. The signals on lines R1R and R2R are omitted in the interest of clarity.

Typically, such over-sampling ADCs do not use the full range of the modulator 9. By appropriately scaling the input capacitor, CIN, and the reference capacitor, CREF, the density of ones at the output of the modulator can be limited to 10% to 90%, for example, for the full range of analog input voltage. This avoids excess noise that arises if there is an output sequence having either a large number of ones or a large number of zeros.

A voltage VCAL is available for calibration; i.e., typically, but not always, the available reference voltage, VREF. The gain calibration is performed by connecting the calibration voltage VCAL to the ADC input 11 (FIG. 1). In some cases the full scale range, may be very much less than the calibration voltage, VCAL, for example if the ADC is incorporating amplification. In such case, the value of the input capacitor, CIN, would be considerably greater than the value of CREF. As discussed above and in the above referenced U.S. Pat. No. 5,134,401, the sampling rate at which the capacitor CIN stores charge may be greater (by a factor R) than the rate at which the reference capacitor, CREF stores charge. That is, in some applications, the full scale range may be VCAL /G, where G is the factor by which the full scale input is less than the calibration voltage VCAL. One technique suggested to generate a suitable voltage is to attenuate VCAL by a factor of G; however, because any practical attenuator will itself introduce gain error the use of most resistor or switched-capacitor attenuators are not adequate.

Another technique suggested to obtain an attenuation, G, of the calibration voltage, VCAL, is to sub-sample such calibration voltage. That is, the calibration voltage VCAL is applied to the analog input and sampled with the input capacitor CIN once every G samples; the other G-1 samples being zero samples. However, with such technique, if G is greater than R, the sampling rate by CIN of VCAL will be less than that by CREF of VREF. This may mean that the input signal is only sampled every 2 or more modulation cycles with zero samples in the intervening cycles. While such technique is adequate in many applications, in some applications driving the delta sigma ADC with such a periodic signal may give rise to excess noise that will often appear at low frequencies and which are sometimes called "idle tones". This results in noisy or unrepeatable gain calibration which may not be satisfactory.

More particularly, if a gain calibration were to be performed with an attenuation factor of four (i.e., G=4), first AIN is set equal to VCAL. Attenuation of the input AIN is achieved by removing three pulses on line AN, for every four pulses on line RF, as shown in FIGS. 3A through 3D, where the pulses on line RF are shown in FIG. 3A and the pulses on line AN are shown in FIG. 3B. Thus, instead of transferring a charge of VCAL CIN during each of the pulses on line RF, or here a total charge, QT =4VCAL CIN, for each four RF pulses, a calibration charge, QCAL =QT /4=VCAL CIN is transferred once for each set of four RF pulses. To put it still another way, to obtain an attenuation factor G, during each period, T, a calibration charge QVCAL =VCAL CIN is transferred once every (G) RF pulses. It should be noted that the signals on lines I1R and I2R (FIGS. 3C and 3D, respectively) are unaltered from those shown in FIGS. 2C and 2D in order to maintain the same level of charge injection as in the normal operation, thereby having the same offset.

For a calibration mode where a sampling ratio R=2 and an attenuation factor, G=8, are provided, reference is made to FIGS. 5A through 5D, where FIGS. 5A through 5D show the signals on lines RF, AN, I1R and I2R, respectively. Here, while three pulses on line AN are removed for every four pulses on line RF, the rate of pulses on line I2R is twice that of the pulses on line RF. Therefore, in the general case, for a gain R (where R is the ratio of the pulse rate on line I2R to the pulse rate on line RF), to obtain an attenuation factor G, during each period, T, a calibration charge QCAL =VCAL CIN is transferred once every (G/R) RF pulses.

In should be noted from FIGS. 3A-3D and FIGS. 5A-5D, that output charge is sampled only during the modulator cycles in which line AN is pulsed (i.e., "active") with the consequential idle-tone problems discussed above.

SUMMARY OF THE INVENTION

In accordance with the present invention a method for calibrating a delta sigma modulator is provided. The delta sigma modulator includes an integrating amplifier circuit with an integrating capacitor for producing an output indicative of an amount of charge held on the integration capacitor. During the calibration mode, a feedback signal sampling section samples a feedback signal and transfers packets of charge corresponding to such sampled feedback signal to the integrating capacitor, and an input signal section samples a calibration signal and transfers packets of charge corresponding to a portion of the calibration signal to the integrating capacitor.

In accordance with one feature of the invention, a delta sigma modulator includes an integrating amplifier circuit with an integrating capacitor for producing an output indicative of an amount of charge held on the integration capacitor. A feedback signal sampling section samples a feedback signal and transfers packets of charge corresponding to such sampled feedback signal to the integrating capacitor. An input signal sampling section is adapted for coupling to an input signal during a normal operating mode and transferring packets of charge AIN CIN to the integrating capacitor, where CIN is the capacitance between an input of the sampling section and the integrating capacitor. During a calibration mode, the input signal sampling section is adapted for coupling a calibration voltage, VCAL. In the calibration mode, the capacitance between the input and the integrating capacitance is reduced by a factor, G, and portions of the charge VCAL CIN are transferred to the integrating capacitor.

With such an arrangement, some charge is transferred to the integration capacitor during the calibration more often thereby reducing idle-tones.

BRIEF DESCRIPTION OF THE DRAWING

Other features of the invention, as well as the invention itself will be more readily understood with reference to the following detailed description taken together with the accompanying drawings, in which:

FIG. 1 is a schematic block diagram of a delta sigma ADC according to the prior art;

FIGS. 2A-2D are timing diagrams of control signals used by the ADC of FIG. 1 during normal operation to provide such ADC with a sampling ratio R=1;

FIGS. 3A-3D are timing diagrams of control signals used by the ADC of FIG. 1 during a calibration mode to attenuate a calibration signal fed thereto by a factor, G, of four and to provide such ADC with a sampling ratio R=1;

FIGS. 4A-4D are timing diagrams of control signals used by the ADC of FIG. 1 during normal operation to provide such ADC with a sampling ratio R=2;

FIGS. 5A-5D are timing diagrams of control signals used by the ADC of FIG. 1 during a calibration mode to attenuate a calibration signal fed thereto by a factor, G, of eight and to provide such ADC with a sampling ratio R=2;

FIG. 6 is a delta sigma ADC according to the invention;

FIGS. 7A-7D are timing diagrams of control signals used by the ADC of FIG. 6 during a calibration mode and a normal operating mode;

FIG. 8 is a delta sigma ADC according to an alternative embodiment of the invention;

FIGS. 9A-9G are timing diagrams of control signals used by the ADC of FIG. 8 during a calibration mode to attenuate a calibration signal fed thereto by a factor, G, of four and to provide such ADC with a sampling ratio R=1;

FIGS. 10A-10G are timing diagrams of control signals used by the ADC of FIG. 8 during normal operation to provide such ADC with a sampling ratio R=1;

FIGS. 11A-11G are timing diagrams of control signals used by the ADC of FIG. 8 during a calibration mode and a subsequent normal operation mode to attenuate a calibration signal fed thereto by a factor, G, of four and to provide such ADC with a sampling ratio R=1;

FIGS. 12A-12G are timing diagrams of control signals used by the ADC of FIG. 8 during a calibration mode to attenuate a calibration signal fed thereto by a factor, G, of eight and to provide such ADC with a sampling ratio R=1;

FIGS. 13A-13G are timing diagrams used by the ADC of FIG. 8 during normal operation to provide such ADC with a sampling ratio R=2;

FIGS. 14A-14G are timing diagrams of control signals used by the ADC of FIG. 8 during a calibration mode to attenuate a calibration signal fed thereto by a factor, G, of eight and to provide such ADC with a sampling ratio R=2; and,

FIG. 15 is an input sampling circuit adapted for use in a delta sigma ADC according to an alternative embodiment of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to FIG. 6, a delta sigma ADC 50 is shown to include a modulator 52 and a digital filter 54. The digital filter 54 is of any conventional type used to process the binary stream of data produced by the modulator 52 and converting them into a sequence of multi-bit digital words. The modulator 52 includes an input signal sampler 62, a feedback signal sampler 64, an integrating amplifier 66 having an integration capacitor CINTGR, a filter 68, for example, a second integrator in the case of a second order modulator, a comparator 70, and a programmable control unit 74 all arranged as shown. The feedback signal sampling circuit 64, like the feedback signal sampler 14 in FIG. 1, includes four switches S5, S6, S7, S8, and a reference capacitor, CRF, as shown controlled by binary signals on lines RF, RF, R1R, R2R,respectively, as shown. (As noted above in connection with FIG. 1, the signal on line RF is the complement of the signal on line RF). The controlsignals on lines RF, RF, R1R, and R2R are produced by the programmable control unit 74 as described in the above reference U.S. Patent 5,134,401 and such signal are shown for line RF in FIG. 7A.

The input signal sampling circuit 62 includes a plurality of, here two, capacitors CIN /4 and 3CIN /4 and four switches S1, S2, S3, and S4, arranged as shown. The capacitance of capacitor CIN /4 is CIN /4; the capacitance of capacitor 3CIN /4 is 3CIN /4. The switches S1 and S2 are controlled by binary signals on lines AN and AN, respectively, as shown. (It is noted that the signal on line AN is the complement of the signal online AN).

In normal operation, the pulses on line RF provides the basic modulator 52 clock, as shown in FIG. 7A. The pulses on lines AN, I1R and I2R are shown in FIGS. 7B through 7D, respectively. It is first noted that the rate of pulses on line RF is equal to the rate of pulses on line I1R, therefore the modulator 52 has a sampling ratio, R, of one.

The input voltage of the analog signal AIN is fed to terminal 11 through switch S.sub.(C/N)1. Also, capacitors CIN /4 and 3CIN /4are connected in parallel by switch S.sub.(C/N)2 to, during the normal operating mode, provide a total capacitance, CT =CIN, between nodes 51, 53, as shown. Thus, the total charge stored by the two capacitors, CIN /4 and 3CIN /4 is the same as that stored in input signal switching section 12 (FIG. 1) in response to the pulses described above in connection with FIGS. 2A-2D. Thus, the modulator 52 operates as input signal switching section 12 (FIGS. 1, 2A-2D) and withoutany attenuation of the input signal AIN.

Charge corresponding to AIN is stored on the two capacitors CIN /4, 3CIN /4 when switches S1 and S3 are closed and switches S2 and S4 are open. The stored charge is transferred to input summing node 59 of the integrator 66 when switches S1 and S3 areopen and switches S2 and S4 are closed. The feedback sampler 64 may add either positive charge or negative charge at input summing node 119 as described in the above referenced U.S. Patent in order to produce anet zero charge at the summing node 59.

During the calibration mode, a calibration signal, a voltage VCAL, here VREF, is fed to terminal 11 through switch S.sub.(C/N)1 and capacitor 3CIN /4 is decoupled from node 51 by switch S.sub.(C/N)2. Thus, a capacitor CIN /4 having one-fourth the capacitance of CIN is coupled across nodes 51 and 53. It follow then that for each four RF pulses, (such four pulses being produced in a time duration, T) instead of transferring one calibration charge QCAL =VCAL CIN =4VFS CIN, a charge VCAL CIN /4=QCAL /4=VFS CIN will be transferred for each four RF pulses. More particularly, and referring back to FIGS. 3A-3D, an attenuation factor G of 4 is achieved with modulator 9 (FIG. 1) by transferring charge, QCAL to the summing node 59 during the period, T; here, however, withmodulator 52 (FIG. 6), charge QCAL /4 is transferred to the summing node 59 at the same rate as the pulses on line RF (i.e., the modulator clock rate). It is noted, however, that after each series of four successive modulator clock pulses on line RF, the same amount of charge, i.e. QCAL, is transferred to summing node 59 (FIG. 6) as was transferred to summing node 19 (FIG. 1). Here, however, because some charge, QCAL /4 is transferred to the summing node 59 at the modulator clock rate, idle-tones have been reduced.

To put it another way, during the calibration mode, the feedback signal sampling section 54 samples a feedback signal, VREF and transfers packets of charge corresponding to such sampled feedback signal to the integrating capacitor CINTGR in each modulator cycle corresponding tothe rate pulses are produced on line RF and an input signal sampling section 52 samples a calibration signal, VCAL, here VREF, and transfers packets of charge corresponding to a portion, here one fourth, of the calibration signal to the integrating capacitor CINTGR in eachmodulator cycle. With such an arrangement, some charge is transferred to the integration capacitor in each modulator cycle thereby reducing idle-tones.

In the more general case, an input signal sampling section 62 is adapted for coupling to an input signal, AIN, during a normal operating mode and transferring packets of charge AIN CIN, to the integrating capacitor, where CIN is the capacitance between an input of the sampling section and the integrating capacitor, CINTGR. During a calibration mode, the input signal sampling section 11 is adapted for coupling a calibration voltage, VCAL, here VREF. In the calibration mode, the capacitance between the input and the integrating capacitance, CINTGR, is reduced by a factor, G, and portions of a charge VCAL CIN are transferred to the integrating capacitor.

Referring now to FIG. 8, a delta sigma ADC 100 is shown to include a modulator 102 and a digital filter 104. The digital filter 104 is of any conventional type used to process the binary stream of data produced by the modulator 102 and converting them into a sequence of multi-bit digitalwords. The modulator 102 includes an input signal sampler 112, a feedback signal sampler 114, an integrating amplifier 116 having an integration capacitor CINTGR, a filter 118, for example, a second integrator in the case of a second order modulator, a comparator 120, and a programmablecontrol unit 124 all arranged as shown. The feedback signal sampling circuit 114, like the feedback signal sampler 14 in FIG. 1, includes four switches S5, S6, S7, S8, and a reference capacitor, CRF, as shown controlled by binary signals on lines RF, RF, R1R, R2R,respectively, as shown. (As noted above in connection with FIG. 1, the signal on line RF is the complement of the signal on line RF). The controlsignals on lines RF, RF, R1R, and R2R are produced by the programmable control unit 124 as described in the above reference U.S. Pat. No. 5,134,401 and the signal for line RF is shown in FIG. 9A.

The input signal sampling circuit 112 includes a plurality of, here four, input signal sub-sampling circuits 1121, 1122, 1123 and 1124, as shown. Each one of the sub-sampling circuits 1121, 1122, 1123 and 1124 is identical in construction and includes two switches S1 and S2, and an input capacitor, CIN /4, arranged as shown. The binary control signals for switches S1, and S2 of sub-sampling circuit 1121 are controlled by binary signals on lines AN0 and AN0, respectively. (It is noted that the signal on line AN0 is the complement of the signal on line AN0). The binary control signals for switches S1 and S2 of sub-sampling circuit 1122 are controlled by binary signals on lines AN1 and AN1, respectively, as shown. (It is noted that the signal on line AN1 is the complement of the signal on line AN1). The binary control signals for switches S1 and S2 of sub-sampling circuit 1123 are controlled by binary signals on lines AN2 and AN2, respectively as shown. (It is noted that the signal on line AN2 is the complement of the signal on line AN2). The binary control signals for switches S1 and S2 of sub-sampling circuit 1124 are controlled by binary signals on lines AN3 and AN3, respectively, as shown. (It is noted that the signal online AN3 is the complement of the signal on line AN3).

In normal operation, the pulses on line RF provides the basic modulator 102clock, as shown in FIG. 10A. The input voltage of the analog signal AIN is fed to terminal 11 of input signal sampling circuit 112 and sampled by each one of the switches S1 in sub-sampling circuits 1121 -1124 in response to pulses on lines AN0-AN3, shown in FIGS. 10B through 10E, respectively. It is noted that each one of the capacitors CIN /4 has a capacitance one fourth the capacitance of capacitor CIN in FIG. 1. Thus, because all of the switches S1 -S4 areclosed at the same time, the total capacitance between the input 11 and theintegrating capacitor CINTGR is CIN and the charge stored by the four capacitors in the input signal switching circuit 112 is the same as that stored in input signal switching section 12 (FIG. 1) in response to the pulses described above in connection with FIGS. 2A-2D. That is, because the binary signals on lines AN0-AN3 are in phase with each other during the normal operating mode, and as shown in FIGS. 10A-10G and in phase with the binary signal on line I1R (the signal on line I2R being delayed by one half modulator period), the modulator 102 operates as inputsignal switching section 12 (FIGS. 1, 2A-2D) and without any attenuation ofthe input signal AIN.

Charge corresponding to the sampled voltage is stored on all four capacitors CIN /4 and is transferred to input summing node 119 of theintegrator 116 when switches S1 and S3 are open and switches S2 and S4 are closed. The rate at which the samples taken by theinput sampler are transferred to the summing node 119 (i.e., the rate that pulses are produced on line I2R) is the rate at which pulses are produced on lines AN0-AN3. The feedback sampler 114 may add either positive charge or negative charge at input summing node 119 as described in the above referenced U.S. Patent in order to produce a net zero charge at the summing node 119.

During the calibration mode, a calibration signal, here a voltage VCAL, here VREF, is fed to terminal 11. Further, the pulses on lines AN0-AN3 produced by programmable control 124 are shown in FIGS. 9B-9E. (It is noted that the pulses on lines RF, I1R and I2R do not changebetween the normal mode and the calibration mode when the same gain, here unity gain, is used). More particularly, and referring back to FIGS. 3A-3D, an attenuation factor G of 4 is achieved with modulator 9 (FIG. 1) by transferring charge, QCAL =VCAL CIN to the summing node 19 once every four pulses on line RF; i.e, during the period of time, T. Here, with modulator 102 (FIG. 8), charge QCAL /4 is transferred to the summing node 119 at the same rate as the pulses on line RF (i.e., the modulator clock rate). The amount of charge transferred during each modulator 102 clock pulse on line RF is one-fourth, (i.e., QCAL /4) the amount of charge transferred during each one of the set of four RF pulses used in the modulator 9 (FIG. 1). It is noted, however, that after each series of four successive modulator clock pulses on line RF, the sameamount of charge, i.e. QCAL, is transferred to summing node 119 (FIG. 7) as was transferred to summing node 19 (FIG. 1). Here, however, because some charge is transferred to the summing node 119 at the modulator clock rate, idle-tones have been reduced.

To put it another way, during the calibration mode, the feedback signal sampling section 114 samples a feedback signal, VREF and transfers packets of charge corresponding to such sampled feedback signal to the integrating capacitor CINTGR in each modulator cycle corresponding tothe rate pulses are produced on line RF and an input signal sampling section 112 samples a calibration signal, VCAL, here VREF, and transfers packets of charge corresponding to a portion, here one fourth, of the calibration signal to the integrating capacitor CINTGR in each modulator cycle. With such an arrangement, some charge is transferred to the integration capacitor in each modulator cycle thereby reducing idle-tones.

Referring now to FIGS. 11A-11G, timing diagrams of timing signal on lines RF, AN0, AN1, AN2 AN3, I1R and I2R, respectively, are shown during both aninitial calibration mode and a subsequent normal operating mode for the modulator 102 in FIG. 8. It is first noted that here during the calibration mode switches S1 of sub-sampling sections 1122, 1123, 1124 remain open while switch S1 of sub-sampling section 1121 operates at the same rate pulses are produced on line RF. Thus, during the calibration mode, modulator 102 operates with such switching operation as the modulator 52, FIG. 6. During the normal operating mode, switches S1 of all the sub-sampling sections 1121, 1122, 1123, 1124 operate together thereby increasing the capacitance between input 11 and summing node 119 from CIN /4 to CIN.

Referring now to FIGS. 12A-12G, timing diagrams of control signals on linesRF, AN0, AN1, AN2 AN3, I1R and I2R, respectively, are shown during a calibration mode to attenuate a calibration signal fed thereto by a factor, G, of eight and to provide ADC 100 with a sampling ratio R=1. It is noted that in this arrangement, while calibration charge is not produced at the same rate as the rate pulses are produced on line RF, there will still be some reduction in "idle tones". In any event, the input signal sampling section 112 is adapted for coupling to an input signal during a normal operating mode and transferring packets of charge AIN CIN, to the integrating capacitor, where CIN is the capacitance between an input of the sampling section the integrating capacitor. During a calibration mode, the input signal sampling section 112 is adapted for coupling a calibration voltage, VCAL, here VREF. In the calibration mode, the capacitance between the input and the integrating capacitance is reduced by a factor, G/2, and portions of the charge VCAL CIN are transferred to the integrating capacitor.

FIGS. 13A-13G are timing diagrams of control signals on lines RF, AN0, AN1,AN2 AN3, IlR and I2R, respectively, and used by the ADC 100 during normal operation to provide such ADC with a sampling ratio R=2. FIGS. 14A-14G aretiming diagrams of control signals on lines RF, ANO, AN1, AN2, AN3, I1R andI2R, respectively, and used by the ADC 100 during a calibration mode to attenuate a calibration signal fed thereto by a factor, G, of eight and toprovide such ADC 100 with a sampling ratio R=2.

Referring now to FIG. 15, an input signal section adapted for use with a bipolar input signal AIN is shown. Equivalent elements as those shownin FIG. 8 are designated by the same numerical designation. It is noted that a differential calibration voltage, VCAL, here VREF, is connected to terminals 11, 11' during the calibration mode. It is also noted that a differential reference voltage, VREF, is connected to terminals 18-18' during both the calibration mode and the normal operatingmode. It is further noted that the outputs of switches S7 and S8 are connected to a summing node 119' which is fed to the non-inverting input (+) of integrating amplifier 116', as shown.

Other embodiments are within the spirit and scope of the appended claims.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US4399426 *May 4, 1981Aug 16, 1983Tan Khen SangOn board self-calibration of analog-to-digital and digital-to-analog converters
US4943807 *Apr 13, 1988Jul 24, 1990Crystal SemiconductorDigitally calibrated delta-sigma analog-to-digital converter
US5134401 *Mar 12, 1991Jul 28, 1992Analog Device, Inc.Delta sigma modulator having programmable gain/attenuation
US5159341 *Mar 12, 1991Oct 27, 1992Analog Devices, Inc.Two phase sampling for a delta sigma modulator
US5363102 *Mar 26, 1993Nov 8, 1994Analog Devices, Inc.Offset-insensitive switched-capacitor gain stage
US5510789 *Mar 28, 1995Apr 23, 1996Analog Devices, IncorporatedAlgorithmic A/D converter with digitally calibrated output
Non-Patent Citations
Reference
1 *Analog Devices, 3V/5, CMOS, 500 A, Signal Conditioning ADC, AD7714, Oct. 1994.
2Analog Devices, 3V/5, CMOS, 500 μA, Signal Conditioning ADC, AD7714, Oct. 1994.
3 *Analog Devices, Lc 2 MOS, Signal Conditioning ADC, AD7710, Jul. 1995.
4Analog Devices, Lc2 MOS, Signal Conditioning ADC, AD7710, Jul. 1995.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US5955978 *Sep 8, 1997Sep 21, 1999Lsi Logic CorporationA/D converter with auto-zeroed latching comparator and method
US6040793 *Mar 18, 1998Mar 21, 2000Analog Devices, Inc.Switched-capacitor sigma-delta analog-to-digital converter with input voltage overload protection
US6111529 *Sep 30, 1998Aug 29, 2000Cirrus Logic, Inc.Accurate gain calibration of analog to digital converters
US6140950 *Aug 17, 1998Oct 31, 2000Linear Technology CorporationDelta-sigma modulator with improved full-scale accuracy
US6204787 *Mar 31, 1999Mar 20, 2001Cirrus Logic, Inc.Circuits and methods for gain ranging in an analog modulator and systems using the same
US6298133Mar 4, 1998Oct 2, 2001Silicon Laboratories, Inc.Telephone line interface architecture using ringer inputs for caller ID data
US6307891Mar 4, 1998Oct 23, 2001Silicon Laboratories, Inc.Method and apparatus for freezing a communication link during a disruptive event
US6359983Mar 4, 1998Mar 19, 2002Silicon Laboratories, Inc.Digital isolation system with data scrambling
US6384760May 30, 2001May 7, 2002Agilent Technologies, Inc.Analog-to-digital converter
US6388449Mar 27, 2001May 14, 2002Motorola, Inc.Circuit and method for auto-calibration of an active load
US6389134Mar 4, 1998May 14, 2002Silicon Laboratories, Inc.Call progress monitor circuitry and method for a communication system
US6430229Apr 22, 1997Aug 6, 2002Silicon Laboratories Inc.Capacitive isolation system with digital communication and power transfer
US6433713May 31, 2001Aug 13, 2002Agilent Technologies, Inc.Calibration of analog-to-digital converters
US6442213 *Mar 4, 1998Aug 27, 2002Silicon Laboratories Inc.Digital isolation system with hybrid circuit in ADC calibration loop
US6480602Mar 4, 1998Nov 12, 2002Silicon Laboratories, Inc.Ring-detect interface circuitry and method for a communication system
US6504864Jun 16, 1998Jan 7, 2003Silicon Laboratories Inc.Digital access arrangement circuitry and method for connecting to phone lines having a second order DC holding circuit
US6509852 *Oct 19, 2001Jan 21, 2003Texas Instruments IncorporatedApparatus and method for gain calibration technique for analog-to-digital converter
US6587560Mar 4, 1998Jul 1, 2003Silicon Laboratories Inc.Low voltage circuits powered by the phone line
US6816100Mar 10, 2000Nov 9, 2004The Regents Of The University Of CaliforniaAnalog-to-digital converters with common-mode rejection dynamic element matching, including as used in delta-sigma modulators
US6833803Sep 11, 2001Dec 21, 2004Radian Research, Inc.Methods and apparatus for analog-to-digital conversion
US7046178 *Mar 26, 2004May 16, 2006Infineon Technologies AgMethod and device for the calibration of a weighted network
US7142142 *Feb 25, 2004Nov 28, 2006Nelicor Puritan Bennett, Inc.Multi-bit ADC with sigma-delta modulation
US7162029May 29, 2003Jan 9, 2007Cirrus Logic, Inc.Gain or input volume controller and method utilizing a modified R2R ladder network
US7202805Feb 10, 2006Apr 10, 2007Analog Devices, Inc.Amplifier gain calibration system and method
US7414557 *Dec 15, 2006Aug 19, 2008Telefonaktiebolaget Lm Ericsson (Publ)Method and apparatus for feedback signal generation in sigma-delta analog-to-digital converters
US7492296 *Sep 28, 2007Feb 17, 2009Cirrus Logic, Inc.Discrete-time programmable-gain analog-to-digital converter (ADC) input circuit with input signal and common-mode current nulling
US7649480 *Dec 4, 2007Jan 19, 2010Wolfson Microelectronics PlcCalibration circuit and associated method
US7952501 *Sep 19, 2007May 31, 2011Sung Wan KimDemodulator capable of compensating offset voltage of RF signal and method thereof
US7994954Nov 17, 2009Aug 9, 2011Wolfson Microelectronics PlcCalibration circuit and associated method
US8319673 *Aug 23, 2010Nov 27, 2012Linear Technology CorporationA/D converter with compressed full-scale range
US8466821 *Jan 7, 2011Jun 18, 2013Panasonic CorporationDelta sigma ADC
US8497793 *Mar 12, 2012Jul 30, 2013Via Telecom, Inc.Analog-to-digital converter with delta-sigma modulation and modulation unit thereof
US20110285569 *Aug 23, 2010Nov 24, 2011Linear Technology CorporationA/D Converter with Compressed Full-Scale Range
US20120001782 *Jan 7, 2011Jan 5, 2012Panasonic CorporationDelta Sigma ADC
CN1909380BJul 17, 2006Dec 1, 2010三洋电机株式会社Switch control circuit, delta-sigma modulation circuit, delta-sigma modulation type AD convertor
EP1332558A1 *Sep 11, 2001Aug 6, 2003Radian Research, Inc.Method and apparatus for analog-to-digital conversion
Classifications
U.S. Classification341/120, 341/172, 341/143
International ClassificationH03M3/02
Cooperative ClassificationH03M3/38, H03M3/43, H03M3/456
European ClassificationH03M3/30
Legal Events
DateCodeEventDescription
Oct 28, 2009FPAYFee payment
Year of fee payment: 12
Oct 27, 2005FPAYFee payment
Year of fee payment: 8
Nov 20, 2001REMIMaintenance fee reminder mailed
Oct 25, 2001FPAYFee payment
Year of fee payment: 4
May 6, 1996ASAssignment
Owner name: ANALOG DEVICES, INC., MASSACHUSETTS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MCCARTNEY, DAMIEN;O DOWD, JOHN;REEL/FRAME:007974/0005
Effective date: 19960429