Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS5766804 A
Publication typeGrant
Application numberUS 08/702,057
Publication dateJun 16, 1998
Filing dateAug 23, 1996
Priority dateJul 18, 1994
Fee statusPaid
Also published asCN1115876A, EP0698916A2, EP0698916A3, EP1786024A1, US5573890, US5702848, US5766806
Publication number08702057, 702057, US 5766804 A, US 5766804A, US-A-5766804, US5766804 A, US5766804A
InventorsChristopher A. Spence
Original AssigneeAdvanced Micro Devices, Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method of optical lithography using phase shift masking
US 5766804 A
Abstract
A method of performing poly level lithography in manufacturing an integrated circuit using a phase shift mask in a step and repeat optical tool where the phase assignment for said phase shift mask is determined by a technique which determines, without assignment conflict, the Intersection of the gate pattern with the active gate pattern and which divides the Intersection into categories of stacks where a slightly different phase assignment rules is employed for the different stacks.
Images(12)
Previous page
Next page
Claims(20)
What is claimed is:
1. A method of forming a mask for a gate level of an integrated circuit, said method comprising the steps of:
providing a mask substrate;
forming a gate level pattern on the mask substrate;
identifying regions of the mask substrate which correspond to active regions of the integrated circuit and identifying one or more portions of the gate level pattern which overlap with the active regions of the integrated circuit; and
forming phase shift regions of different phases on opposite sides of at least one identified portion so as to cause light transmitted through the opposite sides to destructively interfere with each other.
2. A method as recited in claim 1, wherein the step of forming includes etching a portion of the mask substrate to alter the phase of the light transmitted therethrough by 180.
3. A method as recited in claim 1, wherein the step of forming includes depositing an additional layer of the mask substrate to alter the phase of the light transmitted therethrough by 180.
4. A method as recited in claim 1, wherein the step of forming includes forming phase shift regions of opposite phases on the opposite sides.
5. A method as recited in claim 1, wherein the step of forming includes forming phase shift regions having phases differing by 180 on the opposite sides.
6. A method as recited in claim 1, further comprising the steps of:
comparing widths of the identified portions with a minimum width; and
maintaining an equal-valued phase shift on both sides of the identified portions whose widths are larger than the minimum width.
7. A method as recited in claim 6, wherein the step of forming includes the steps of:
for each identified region corresponding to the active regions of the integrated circuit and intersected by the gate level pattern, determining a contiguous piece of the identified region; and
if the contiguous piece of the identified region has a length greater than 2Wi +Wc, dividing the contiguous piece into two separate phase shift regions with a separation distance of at least Wc.
8. A method as recited in claim 7, wherein the step of forming further includes the steps of:
determining distances between each pair of identified portions; and
if any of the distances is less than 2Wi +Wc, maintaining one continuous phase shift region between any such pair of identified portions.
9. A method as recited in claim 8, further comprising the step of verifying that a phase shift difference of the phase shift regions on either side of each identified portion whose width is less than or equal to the minimum width is 180.
10. A method as recited in claim 5, wherein the step of forming includes maintaining a phase of x on one side of said at least one identified portion and altering a phase on an opposite side of said at least one identified portion to be x+180.
11. A method as recited in claim 10, further comprising the steps of:
identifying regions, other than said one or more identified portions, which cause light transmitted through opposite sides thereof to destructively interfere with each other; and
forming a transition phase shift region adjacent to each of the identified regions, the transition phase shift region including two or more additional phase shift regions.
12. A mask for producing a gate level pattern on a substrate of an integrated circuit, comprising:
a light-transmissive mask substrate;
an opaque gate level pattern formed on the mask substrate;
phase shift regions of different phases formed on opposite sides of those portions of the opaque gate level pattern which overlap with active regions of the integrated circuit, but not on opposite sides of those portions of the opaque gate level pattern which do not overlap with active regions of the integrated circuit.
13. A mask as recited in claim 12, wherein some phase shift regions include etched portions which alter the phase of the light transmitted therethrough by 180.
14. A mask as recited in claim 12, wherein some phase shift regions include thicker portions which alter the phase of the light transmitted therethrough by 180.
15. A mask as recited in claim 12, wherein the phase shift regions on opposite sides of the overlapping portions are out of phase with each other by 180.
16. A mask as recited in claim 15, one side of the overlapping portions has a phase of x and the opposite side of the overlapping portions has a phase of x+180.
17. A mask as recited in claim 16, further comprising transition phase shift regions formed adjacent to regions, other than the overlapping portions, which cause light transmitted through opposite sides thereof to destructively interfere with each other, the transition phase shift region including two or more additional phase regions.
18. A mask as recited in claim 17, wherein the phases of the additional phase regions increase linearly.
19. A mask as recited in claim 17, wherein the phases of the additional phase regions increase stepwise.
20. A mask as recited in claim 12, wherein the identified portions whose widths are larger than a minimum width have phase shift regions with a phase of x on either side thereof.
Description

This application is a continuation, of application Ser. No. 08/276,734, filed Jul. 18, 1994, now U.S. Pat. No. 5,573,890.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a field of integrated circuit manufacture using phase shift masking in the optical lithographic patterning process.

2. Background of the Invention

Optical lithography has been the technique of choice employed for forming circuit patterns in integrated circuits. Typically, ultraviolet light is directed through a mask. A mask is similar in function to a "negative" which is used in ordinary photography. However, the typical mask has only fully light transmissive and fully non-transmissive regions as opposed to an ordinary negative which has various "gray" levels. In the same manner as one makes a print from a negative in ordinary photography, the pattern on the mask can be transferred to a semiconductor wafer which has been coated with a photoresist layer. An optical lens system provides focusing of the mask patterns onto the surface of the photoresist layer. The exposed photoresist layer is developed, i.e. exposed/non-exposed regions are chemically removed. The resulting photoresist pattern is then used as a mask for etching underlying regions on the wafer.

In recent years, demands to increase the number of transistors on a wafer have required decreasing the size of the features but this has introduced diffraction effects which have made it difficult to further decrease the feature size. Prior to the work of Levenson, et. al., as reported in "Improving Resolution in Photolithography with a Phase Shifting Mask," IEEE Transactions on Electron Devices, VOL., ED-29, Nov. 12, Dec. 1982, pp. 1828-1836, it was generally thought that optical lithography would not support the increased density patterning requirements for feature sizes under 0.5 microns. At this feature size, the best resolution has demanded a maximum obtainable numerical aperture (NA) of the lens systems. However, the depth of field of the lens system is inversely proportional to the NA, and since the surface of the integrated circuit could not be optically flat, good focus could not be obtained when good resolution was obtained and it appeared that the utility of optical lithography had reached its limit. However, the Levenson paper introduced a new phase shifting concept to the art of mask making which has made use of the concepts of destructive interference to overcome the diffraction effects.

Ordinary photolithography, with diffraction effects, is illustrated in FIGS. 7(a) to 1(d). As the apertures P1 and P2 become closer, N becomes smaller, and as seen in FIG. 1 (b), the light amplitude rays which pass through P1 and P2 start to overlap due to diffraction effects. These overlapping portions result in light intensity at the wafer, FIG. 1(d), which impinges on the photoresist layer. Accordingly, due to diffraction, the intensity of the wafer no longer has a sharp contrast resolution in the region between P1 and P2.

As illustrated by FIG. 2(a) to 2(e), it is possible to make use of the fact that light passing through the masking substrate material, FIG. 2(a), 51, (and FIG. 2(b), 51') exhibits a wave characteristic such that the phase of the amplitude of the light exiting from the mask material is a function of the distance the light ray travels in the substrate material, i.e., thickness t1 and t2. By making the thickness t2 such that (n-1) (t2) is exactly equal to 1/2 λ, where λ is the wavelength of the light in the mask material, and n= refractive index of the added or subtracted natural material, then the amplitude of the light existing from aperture P2 is in opposite phase from the light exiting aperture P1. This is illustrated in FIG. 2(c) showing the effects of diffraction and use of interference cancellation. The photoresist material is responsive to the intensity of the light at the wafer. Since the opposite phases of light cancel where they overlap and since intensity is proportional to the square of the resultant amplitude, as seen in FIG. 2(d), contrast resolution is returned to the pattern.

FIG. 2(a) and FIG. 2(b) illustrate two different techniques for obtaining the interference phase shifting. In FIG. 2(a), the light traverses through a longer distance via deposited layer 52. In FIG. 2(b), the light in region P2 transverses through a shorter distance by virtue of an etched groove 52' in the wafer 51'.

Phase shifting masks are now well known and there are many varieties which have been employed, as more fully set out in the article by B. J. Lin, "Phase-Shifting Masks Gain an Edge," Circuits and Devices, March 1993, pp. 28-35. The configuration of FIG. 2(a) and FIG. 2(c) have been called alternating phase shift masking (APSM). Several researchers have compared the various phase shifting techniques and have shown that the APSM approach is the only known method proven capable of achieving resolution 0.25 microns and below, with depth of field as large as 0.34 microns with an I line stepper. Alternating PSM can be implemented in dark and light field mask versions. If the dark field strategy is employed for alternating PSM, a negative tone photoresist must be employed and if the light field version is employed, a positive photoresist must be chosen. The positive resist portion which is exposed to UV is removed during development and vice versa for negative resist.

As illustrated in FIG. 2(e), the process for making and using binary masks have been highly computerized. The designer of complex integrated circuits now works at a computer terminal and specifies a circuit design on a computer which requires compliance with certain predetermined design rules, 80. The initial design is validated using a design rule checker software 88. Accordingly, when the functional design is completed, a computer aided design tool program 81 automatically creates a digital bit map or vector file called a PG Tape 82 which represents the data in a standard and known data format for manufacturing the mask to accomplish the design. These digital files are then used to control automatic processes for manufacturing the masks, typically resulting in a magnified, eg. 5, physical reticle, 83, containing the mask pattern for each layer of the integrated circuit. The mask is then typically installed in a wafer stepper (a step and repeat optical tool) 84, which automatically carries out the lithographic exposure repeatedly on the wafer 87 by exposing the photoresist layer 85 at a physical location and moving the wafer, i.e. stepping, and repeating the same exposure at an adjoining location.

To date, due to various difficulties, alternating phase shifting masks have not generally been able to be designed automatically by the mask creation programs. This has required mask designers to expend time consuming and tedious manual analysis and has greatly increased the expense of producing PSM.

The problem with alternating PSM is that the dark field/negative resist strategy does not perform well for non-dense line patterns and the light field/positive resist strategy creates unwanted opaque lines corresponding to the 0/180 transitions in the mask.

Accordingly, in order to employ alternating PSM for isolated patterns, it is necessary to solve the problems with the light field/positive resist strategy and to develop a method for automatically creating compensation or trim masks for eliminating the effect of unwanted opaque lines which form along 0/180 transitions.

SUMMARY OF THE INVENTION

It is an object of this invention to provide a method for improving the patterning of integrated circuits using light field photolithography with positive photoresists.

It is a still further object of the invention to simplify the design of phase shift masking for the gate level patterning of an integrated circuit which compensates for 0/180 transition effects.

It is yet a still further object to provide a method to define a phase shift mask for the gate level patterning which provides phase shift elements to improve the dimensional control of the gate level pattern only in the integrated circuit region where the gate pattern overlays the active area pattern of the integrated circuit.

It is a still further object to provide a PSM method which enables maximally reduced gate patterns in the integrated circuit region where the gate pattern overlays the active area pattern of the integrated circuit.

It is a still further object to manufacture integrated circuits having better critical dimension control of the gate level pattern using the improved PSM methods of this invention.

It is a still further object to provide a process which automatically analyzes an IC logic circuit design and provides a digital file according to an accepted standard for manufacturing an alternating PSM for logic circuits.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1(a) to 1(d) are schematic representations of diffraction effects using a prior art ordinary binary transmission mask in photolithography.

FIGS. 2(a) to 2(d) are schematic representations of diffraction effects and the use of prior art phase shift masking (PSM) to compensate for the effects of diffraction.

FIG. 2(e) illustrative of the mask production and IC photolithographic production process.

FIG. 3 is illustrative of a sample IC design showing the active areas (N and P) pattern and an overlay of the pattern of a gate level.

FIG. 4 is illustrative of the area of the Intersection of the active area and gate level including the designation of 0 degree and 180 degree phase shift regions according to this invention.

FIG. 5 is a redrawing of FIG. 4 illustrative of only the 180 degree phase shift regions of the sample design of FIG. 3.

FIG. 6 is a version of a resulting PSM of the invention for the example of FIG. 3 showing gate contact opaque chrome lines and the transition compensation regions surrounding the 180 degree regions.

FIG. 7 is a version of alternative PSM for the example of FIG. 3 showing gate contact opaque chrome lines and the 180 degree regions without surrounding transition compensation regions.

FIG. 8 is a version of trim mask for use following exposure by the mask of FIG. 7 to avoid lines caused by 0/180 transition.

FIGS. 9(a) to 9(c) are cross sections illustrative of the alignment of a trim mask transparent aperture center line with the abutting line of the 0/180 regions of the non-transition compensated mask of FIG. 8.

FIG. 10 is a flow diagram for the procedure to manufacture an alternating PSM with compensating transition regions and reduced gate lengths and to perform photolithography using said alternating light field PSM and positive photoresist.

FIGS. 11(a) and 11(b) illustrates the standard gate metal design and the reduced gate design respectively.

FIGS. 12(a) to 12(d) is illustrative of several configurations of transition compensation region shifter embodiments.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

It is generally believed by those skilled in PSM lithography that a mask employing a light field cannot be automatically designed by a computer for integrated circuit application in the design of alternating PSM layouts. Light field designs use opaque regions on the PSM mask to correspond to the location and shape of the conductive lines, typically doped low resistivity polysilicon, or tungsten silicide or the equivalent, to be formed on the resulting wafer and positive photoresist must be employed in combination with the light field mask. This light field design with PSM has a very significant advantage for logic gate layout in that it provides improved resolution in connection with isolated gates. However, it also has the disadvantage that dark lines form along every abutting 0/180 region. To date, light field alternating PSM have needed to be designed by examining manually each PSM design and by either inserting a compensating phase shift transition region separating each 0 region from each 180 region or by manually designing a trim mask to be used in conjunction with a PSM which has no phase shift compensating regions.

To simplify and provide an automatic solution to the alternating PSM problem, I propose an approach for designing a light field alternating PSM which appears to work reliably for logic circuits and for reliably shrinking gate size for logic circuits. The underlying premise of my approach is to apply the alternating phase shifts only to those regions of the gate level PSM mask where the gate lines provided by a standard gate level pattern design would overlay the regions in which active semiconductor (N and P) are to be formed. In Boolean algebra, where X is a first function and Y is a second function, the common overlay region is called the intersection and is designated Z=S∩Y. (This is also called the "AND" function.) Hereinafter, the overlay region is designated the "Intersection."

With reference to FIG. 3, there is shown, for purposes of illustration, a computer generated printout, in scale, of the aerial view of the layout of "doped" active regions, 30-38 of a circuit to be formed in the integrated circuit semiconductor wafer. Also shown in FIG. 3 overlaid on the active region layout, are computer generated solid black lines, representing the gate pattern, 40-49, called poly lines, which have been printed to the same scale as the active area and in this aerial view of FIG. 3 are positioned exactly as they would be positioned with respect to the active area on the target circuit. Assuming that the width dimensions of the poly lines of this design needs to be so narrow that optical diffraction effects would degrade the image of the mask if constructed by ordinary binary photolithography, then application of my invention method is needed to automatically make a alternating light field PSM and integrated circuits with such mask.

FIG. 4 contains hash marked areas 50 which represent the computer generated Intersection of the poly gate lines 40-49 of FIG. 3 and the semiconductor wafer active area regions 30-38 of FIG. 3. There are many ways to establish the Intersection plot. One approach is to have a computer perform the logical AND function, i.e. XY, pixel by pixel, where X is the active area spatial representation of FIG. 3 and Y is the gate level spatial pattern of FIG. 3. FIG. 4 also includes the outline region of the active area of FIG. 3. Next, the computer is employed to apply a scheme for automatically assigning zero degree and 180 degree regions on opposite sides of the Intersection. It is seen in FIG. 4 that the computer analyzes and then assigns a zero degree and a 180 degree region on opposite sides of each Intersection long dimension. There are constraints on the program for allocating phase selection for a given area: (1) every Intersection longer dimension must have a 0 and 180 border section; and (2) the 180 degree region and the zero degree region on each side of an Intersection along the longer dimension should have a minimum width Wi and have an area around it which can be used as a compensation region. The compensation region should have width Wc. If the area between two Intersections is less than (2Wi +Wc) then the area between the Intersections needs to be merged into a single phase 0 or 180 region.

FIG. 4 is redrawn in FIG. 5 except that the outline of zero degree areas has been deleted so that the FIG. 5 labels only the π regions. The remaining region is assumed to be zero phase. However, as noted earlier, it is recalled that one of the problems Wi th light field designs is that, unless compensated, a dark line is formed on the wafer which corresponds to the line where the 180 region abuts a 0 region. Accordingly, in FIG. 6, a region called the transition region 51 is shown formed between every 180 region and its adjoining zero degree region. The only portion of the periphery of the 180 degree region which are not interfaced by a transition region 51 is where the 180 region abuts the intersection regions 50. FIG. 6 also includes opaque line regions 40-49 which are overlaid on the compensated 180 degree regions, so that FIG. 6 is the aerial representation of one embodiment of the final computer generated light field alternating PSM for a single exposure to produce the gate level poly pattern depicted in FIG. 3. In a single exposure step, assuming a positive resist is employed on a wafer, if a PSM is manufactured according to FIG. 6 design, the gate layered circuit of FIG. 3 aerial view will be able to be produced.

Alternatively, a two step exposure method can also accomplish the gate level poly patterns depicted in FIG. 3. FIG. 7 is identical to FIG. 6 but without any compensating transition region surrounding each 180 degree region. As noted, when exposing in a first step the positive photoresist on the wafer with a light field PSM of the form of FIG. 7, dark lines will be imaged along the line where 180 regions abut 0 regions. These unwanted dark lines can then be removed by a second exposure of the wafer through the "trim" mask of FIG. 8, provided no development is carried until completion of both exposure steps. The trim mask is transmissive along every 0/180 degree region abutting line so that the second exposure of the positive photoresist results in exposure and hence removal of the dark lines during resist development. FIG. 9 is further explanatory of one embodiment of the alignment and construction of a trim mask. FIG. 9(a) is a cross section of a deposited 180 degree phase shift region 100 which has an abutting transition line 110 between the 180 degree region and the zero degree region, 102. In FIG. 9(b) an etched shifter 105 is illustrated and the transition 110' between the zero and 180 degree region is also shown. A trim mask 107 for the shifter masks of FIG. 9(a) and 9(b) is shown in FIG. 9(c). The trim mask 107 is aligned so that the center 111 of the transmission region 112 is aligned with the transition 110 or 110'. The UV light which transmits through the trim mask falls on the positive photoresist and exposes that region so that it will be removed during development of the resist. (It is noted that it is understood by those skilled in the art that following resist development, the non-exposed photoresist remains in place over the top of the region to be retained. Since the photoresist is over the top of a polysilicon or metal layer, after the resist is removed and the wafer is etched, the remaining resist protects the lines beneath it so that the uncovered poly (metal) on the wafer surface is removed, leaving the desired gate contact pattern.)

With reference to FIG. 11(a) and FIGS. 12(a)-12(d), a compensation transition region 51 configuration embodiment is depicted. The transition region 51 can be constructed of step regions, preferably two or more step regions, such as 120 degrees (71) and 60 degree (70) interposed between the π region and the zero degree region. A single π/2 step region may also work in some instances. Physically, these stepped phase transition regions should have a minimum width 0.2 λ/NA, where λ is exposure wavelengths and NA is numerical aperture of the stepper and can be configured according to FIG. 12(a) for a deposited shifter or 12(b) for an etched shifter. Alternatively, the transition region can also have more steps or be a graded transition according to 12(c) or 12(d) for deposited or etched PSM respectively.

FIG. 11(b) discloses a further embodiment of the PSM gate level design method. I have determined that it is possible to employ the dark natural line formed at the Intersection which coincides with the abutting of the 180/0 degree regions to create the narrowest possible gate. For example, using a stepper with a numerical aperture of 0.5, a partial coherence factor 0.5 for the light source, and an exposure wavelength of 365 nm, and an alternating PSM, this minimum gate was 0.2 microns. As shown in FIG. 11(b), as another alternative, I provide a very narrow opaque line, 75 on the mask as shown which would overlay the 0/180 degree natural dark abutting transition. This narrow opaque line is very slightly narrower than the natural width of 0.2 microns, such as 0.18 microns or whatever increment is required to provide reliability in manufacturing yield.

This narrow opaque line is desirable for three reasons: 1) by concealing the phase edge it reduces the displacement of the wafer image caused by misalignment of the phase shift layer to the opaque layer on the mask; 2) it reduces line width error at the abutting 180/0 transition caused by misalignments of phase layers where a multiple phase step method is used; and 3) the opaque line, typically chromium, provides a more robust mask to etching than the photoresist, providing a steeper etched profile.

The natural line width for a stepper is defined as 0.25*λ/NA; where λ is the excitation wavelength and NA is numerical apeture.

The procedure described above is more fully illustrated in the flow diagram of FIG. 10. Specifically, block 120 depicts the AND operation to determine the Intersection of the active area pattern and poly gate contact pattern. Next, in block 121, all gates which are narrower than the minimum width achievable without phase shift masking are identified. Block 122, depicts a subclassification step which identifies groupings of Minimum width gates which are contiguous and where the gate to gate spacing is too close for transition regions, i.e. less than 2Wi +Wc. These groupings are called "stacks". Gates which are not in a stack are classified as isolated gates 126. Next, the "stacks" identified in block 122 are further subclassified into branch, 123, odd 124, or even 125 stacks.

The odd stacks are groups in which an odd number of minimum gate intersectors occur on a common active area bordered by a spacing on both sides which is large enough for a transition region. In block 130, these odd stack regions are to be phase shifted by applying 180 phase shift to the left most region and then progressively alternating the phase from 180 to 0 and 0 to 180 for regions between gates progressively from left to right.

In block 125, the even stack regions are groups where an even number of intersections occur on a common active area bordered by a spacing large enough for a transition region. The strategy here is to apply 0 phase shift to the left most region and progressively alternating the phase from 0 to 180 to 0 for regions between gates progressively from left to right.

For isolated regions 126, one side of the gate is to provided with a transition compensation region, i.e. graduated or steps of phases to eliminate the formation of an unwanted line.

Branch regions are regions in which parts of a single active region is bordered by more than two minimum gates. This contrasts to the odd and even stack where each part of a single active region is bordered by only two Intersections, i.e. two minimum gates. The shift strategy for such branch stack regions is to select one phase, either 180 or 0, for the central region having more than two Intersections, and then working outward in all directions, alternating phase as one crosses each gate.

In block 132, the data for each type of stack and for isolated gates is reassembled and then verified by the Design Rule Checker 133 to confirm and verify that all minimum gates have 180 or 0 phase one side and not on the other side of each long dimension.

In block 134, the transition regions are generated for every location where 180/0 regions abut such as at the short side of a gate and at the edge of a stack. Alternatively, as depicted earlier, the transitions could be replaced by a separate trim mask for which the data is now generated.

Finally, the output data called GDS2 is created for the mask generation. The FRACT software module of the Dracula program supplied by Cadence Design System will create GDS2 in the MEBES standard file format for an e-beam mask writer. For phase shifting type masks, data for more than one layer are output to create the poly reticle and the FRACT module will create the tape output containing all the layers required to create the phase shift mask and the trim mask if this alternative is elected.

The positive photoresist used in this invention are available commercially under numerous tradenames. The invention is not limited to these currently used resists.

The reticles typically are made from amorphous silicon dioxide, i.e. synthetic quartz, and the opaque material is typically chrome. Any opaque material could theoretically be used in place of chrome for this invention and the invention is not dependent on the specific material employed.

The figures of this document depict embodiments of this invention and are not intended to limit the scope of the invention. The scope of claims shall be construed in accordance with the claims. With this in view,

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US5302477 *Aug 21, 1992Apr 12, 1994Intel CorporationPlurality of rim phase-shifted opening patterns in closely spaced array
US5308722 *Sep 24, 1992May 3, 1994Advanced Micro DevicesVoting technique for the manufacture of defect-free printing phase shift lithography
US5308741 *Jul 31, 1992May 3, 1994Motorola, Inc.Radiation; semiconductors
US5328807 *Jun 7, 1991Jul 12, 1994Hitichi, Ltd.Photoresists films, radiation transparent plates, phase shift, and patterns
US5352550 *Apr 23, 1993Oct 4, 1994Hitachi, Ltd.Mask for manufacturing semiconductor devices and method of manufacture thereof
Non-Patent Citations
Reference
1 *A. Moniwa et al., Algorithm For Phase Shifting Mask Design With Priority On Shifter Placement, Jpn. J. Appl. Phys., vol. 32 (Jul. 1993) Pt. 1, No. 12B, pp. 5871 5879.
2A. Moniwa et al., Algorithm For Phase-Shifting Mask Design With Priority On Shifter Placement, Jpn. J. Appl. Phys., vol. 32 (Jul. 1993) Pt. 1, No. 12B, pp. 5871-5879.
3 *H. Jinbo et al., 0.2 m or Less i Line Lithography By Phase Shifting Mask Technology, 1990 International Electron Devices Meeting Technical Digest, Dec. 9 12, 1990, pp. 004 007.
4H. Jinbo et al., 0.2 μm or Less i-Line Lithography By Phase-Shifting-Mask Technology, 1990 International Electron Devices Meeting Technical Digest, Dec. 9-12, 1990, pp. 004-007.
5 *K. Ooi et al., Computer Aided Design Software For Designing Phase Shifting Masks, Jpn. J. Appl. Phys., vol. 32 (1993), Pt. 1, No. 12B, Dec. 1993, pp. 5887 5891.
6K. Ooi et al., Computer Aided Design Software For Designing Phase-Shifting Masks, Jpn. J. Appl. Phys., vol. 32 (1993), Pt. 1, No. 12B, Dec. 1993, pp. 5887-5891.
7 *T. Waas et al., Automatic Generation of Phase Shift Mask Layouts, Microelectronic Engineering 23 (Mar. 1994) pp. 139 142, Elsevier Science B.V.
8T. Waas et al., Automatic Generation of Phase Shift Mask Layouts, Microelectronic Engineering 23 (Mar. 1994) pp. 139-142, Elsevier Science B.V.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US5923566 *Mar 25, 1997Jul 13, 1999International Business Machines CorporationPhase shifted design verification routine
US6057063 *Apr 14, 1997May 2, 2000International Business Machines CorporationPhase shifted mask design system, phase shifted mask and VLSI circuit devices manufactured therewith
US6210841Sep 7, 1999Apr 3, 2001Taiwan Semiconductor Manufacturing CompanyApproach to increase the resolution of dense line/space patterns for 0.18 micron and below design rules using attenuating phase shifting masks
US6420074Dec 7, 2000Jul 16, 2002Numerial Technologies, Inc.Shrinking integrated circuit designs using a two mask process: a phase shift mask and a single phase structure mask; prevention of erasure of phase shifting regions and the creation of undesirable artifact regions; minimization
US6436590Apr 20, 2001Aug 20, 2002Numerical Technologies, Inc.Phase shifting circuit manufacture method and apparatus
US6503666Sep 26, 2000Jan 7, 2003Numerical Technologies, Inc.Phase shift masking for complex patterns
US6523165Jul 13, 2001Feb 18, 2003Numerical Technologies, Inc.Alternating phase shift mask design conflict resolution
US6524752Sep 26, 2000Feb 25, 2003Numerical Technologies, Inc.Integrated circuits, photolithography
US6528232Oct 31, 2000Mar 4, 2003Nec CorporationChemically amplified photoresist composition using the novel sulfonium salt compound as the photoacid generator
US6534224Jan 30, 2001Mar 18, 2003Advanced Micro Devices, Inc.Phase shift mask and system and method for making the same
US6539521Sep 29, 2000Mar 25, 2003Numerical Technologies, Inc.Dissection of corners in a fabrication layout for correcting proximity effects
US6541165Sep 26, 2000Apr 1, 2003Numerical Technologies, Inc.Automatic mapping the phase shifting regions for implementation of such features, resolving phase conflicts, applying subresolution; miniaturization; high-density integrated circuits; opaque and complementary binary phases
US6551750Mar 16, 2001Apr 22, 2003Numerical Technologies, Inc.Self-aligned fabrication technique for tri-tone attenuated phase-shifting masks
US6553560May 31, 2001Apr 22, 2003Numerical Technologies, Inc.Alleviating line end shortening in transistor endcaps by extending phase shifters
US6566019Apr 25, 2001May 20, 2003Numerical Technologies, Inc.Semiconductors; process control of masks
US6566023May 24, 2002May 20, 2003Numerical Technology, Inc.Phase shifting circuit manufacture method and apparatus
US6569583Jun 6, 2001May 27, 2003Numerical Technologies, Inc.Using a computer program; for an optical lithography process for manufacturing an integrated circuit
US6584610Mar 29, 2001Jun 24, 2003Numerical Technologies, Inc.Incrementally resolved phase-shift conflicts in layouts for phase-shifted features
US6593038Jun 6, 2001Jul 15, 2003Numerical Technologies, Inc.Method and apparatus for reducing color conflicts during trim generation for phase shifters
US6605481Mar 8, 2002Aug 12, 2003Numerical Technologies, Inc.Facilitating an adjustable level of phase shifting during an optical lithography process for manufacturing an integrated circuit
US6610449Aug 20, 2002Aug 26, 2003Numerical Technologies, Inc.Mapping the phase shifting regions for implementation of such features, resolving phase conflicts and applying sub-resolution assist features within phase shift regions and optical proximity correction features to phase shift regions
US6622288Mar 29, 2001Sep 16, 2003Numerical Technologies, Inc.Conflict sensitive compaction for resolving phase-shift conflicts in layouts for phase-shifted features
US6635393Mar 23, 2001Oct 21, 2003Numerical Technologies, Inc.Blank for alternating PSM photomask with charge dissipation layer
US6653026Dec 20, 2000Nov 25, 2003Numerical Technologies, Inc.Photolithography; integrated circuits; semiconductors
US6664009Jul 27, 2001Dec 16, 2003Numerical Technologies, Inc.Method and apparatus for allowing phase conflicts in phase shifting mask and chromeless phase edges
US6681379Nov 15, 2001Jan 20, 2004Numerical Technologies, Inc.Phase shifting design and layout for static random access memory
US6684382Aug 31, 2001Jan 27, 2004Numerical Technologies, Inc.Microloading effect correction
US6698007Oct 9, 2001Feb 24, 2004Numerical Technologies, Inc.Method and apparatus for resolving coloring conflicts between phase shifters
US6699800 *Mar 28, 2002Mar 2, 2004Nanya Technology CorporationPattern design method for lithography C/H process
US6704921Apr 3, 2002Mar 9, 2004Numerical Technologies, Inc.Automated flow in PSM phase assignment
US6721938Feb 25, 2002Apr 13, 2004Numerical Technologies, Inc.Optical proximity correction for phase shifting photolithographic masks
US6728946Oct 31, 2000Apr 27, 2004Franklin M. SchellenbergMethod and apparatus for creating photolithographic masks
US6733929Feb 6, 2002May 11, 2004Numerical Technologies, Inc.Phase shift masking for complex patterns with proximity adjustments
US6735752Sep 10, 2001May 11, 2004Numerical Technologies, Inc.Modifying a hierarchical representation of a circuit to process features created by interactions between cells
US6738958Sep 10, 2001May 18, 2004Numerical Technologies, Inc.Modifying a hierarchical representation of a circuit to process composite gates
US6777141Sep 16, 2002Aug 17, 2004Numerical Technologies, Inc.Includes identifying a pattern, and automatically mapping the phase shifting regions for implementation of such features.
US6785879Jun 11, 2002Aug 31, 2004Numerical Technologies, Inc.Model-based data conversion
US6787271Feb 28, 2002Sep 7, 2004Numerical Technologies, Inc.Design and layout of phase shifting photolithographic masks
US6811935Sep 5, 2002Nov 2, 2004Numerical Technologies, Inc.Includes identifying features for which phase shifting can be applied, automatically mapping the phase shifting regions for implementation of such features, resolving phase conflicts, applying sub-resolution assist features
US6818385Jan 13, 2003Nov 16, 2004Numerical Technologies, Inc.Phase shifting circuit manufacture method and apparatus
US6821689Sep 16, 2002Nov 23, 2004Numerical TechnologiesUsing second exposure to assist a PSM exposure in printing a tight space adjacent to large feature
US6852471Oct 5, 2001Feb 8, 2005Numerical Technologies, Inc.Exposure control for phase shifting photolithographic masks
US6859918Dec 6, 2002Feb 22, 2005Numerical TechnologiesAlleviating line end shortening by extending phase shifters
US6866971Nov 14, 2002Mar 15, 2005Synopsys, Inc.Full phase shifting mask in damascene process
US6901575Dec 5, 2001May 31, 2005Numerical Technologies, Inc.Resolving phase-shift conflicts in layouts using weighted links between phase shifters
US6978436Jun 7, 2002Dec 20, 2005Synopsys, Inc.Design data format and hierarchy management for phase processing
US6981240Jan 10, 2003Dec 27, 2005Synopsys, Inc.Cutting patterns for full phase shifting masks
US7028285Jun 7, 2002Apr 11, 2006Synopsys, Inc.Standard cell design incorporating phase information
US7083879Aug 17, 2001Aug 1, 2006Synopsys, Inc.Phase conflict resolution for photolithographic masks
US7122281Nov 14, 2002Oct 17, 2006Synopsys, Inc.Defining critical edge portions of the features with a full phase shifting mask (FPSM) includes a first set of cuts between adjacent phase shifters to resolve phase conflicts; a computer software
US7132203Apr 6, 2004Nov 7, 2006Synopsys, Inc.Masking for layers of integrated circuits; automatic detection phase shift zones patterns; controlling; mdel for fitting between exposure pattern and targets; photolithography
US7135255Mar 31, 2003Nov 14, 2006International Business Machines CorporationLayout impact reduction with angled phase shapes
US7165234May 12, 2004Jan 16, 2007Synopsys, Inc.shifters on a phase shifting mask can be assigned their corresponding phase through the use of a simulation engine of the type normally used for model-based optical proximity correction
US7169515Apr 29, 2004Jan 30, 2007Synopsys, Inc.A data processing system containing a machine readable data storage medium with instructions for laying out a photolithographic mask, coupled to a processor; integrated circuits; electromagnetic waveform computer program for assigning phase shifting regions
US7174531Mar 26, 2004Feb 6, 2007Schellenberg Franklin MCreating photolithographic masks
US7178128Oct 15, 2002Feb 13, 2007Synopsys Inc.Alternating phase shift mask design conflict resolution
US7216331Nov 3, 2004May 8, 2007Synopsys, Inc.Resolving phase-shift conflicts in layouts using weighted links between phase shifters
US7236916Sep 9, 2003Jun 26, 2007Synopsys, Inc.Structure and method of correcting proximity effects in a tri-tone attenuated phase-shifting mask
US7281226Feb 27, 2003Oct 9, 2007Synopsys, Inc.Incrementally resolved phase-shift conflicts in layouts for phase-shifted features
US7348108Sep 10, 2004Mar 25, 2008Synopsys, Inc.Design and layout of phase shifting photolithographic masks
US7422841May 7, 2004Sep 9, 2008Synopsys, Inc.Exposure control for phase shifting photolithographic masks
US7435513Sep 10, 2004Oct 14, 2008Synopsys, Inc.Reducing phase conflicts in complex designs
US7500217Mar 17, 2005Mar 3, 2009Synopsys, Inc.Handling of flat data for phase processing including growing shapes within bins to identify clusters
US7534531Jan 13, 2005May 19, 2009Synopsys, Inc.Full phase shifting mask in damascene process
US7585595Aug 17, 2004Sep 8, 2009Synopsys, Inc.Automatic mapping the phase shifting regions by photolithographic masking, resolving phase conflicts, applying subresolution; miniaturization; high-density integrated circuits; opaque and complementary binary phases
US7622336Dec 27, 2006Nov 24, 2009Semiconductor Energy Laboratory Co., Ltd.Manufacturing method of semiconductor device
US7629109Apr 7, 2008Dec 8, 2009Synopsys, Inc.Exposure control for phase shifting photolithographic masks
US7659042Jul 31, 2008Feb 9, 2010Synopsys, Inc.photomasks; photoresists; for hard-to-etch metal layers such as copper; integrated circuits; improved resolution
US7827518Jun 20, 2007Nov 2, 2010Synopsys, Inc.Incrementally resolved phase-shift conflicts in layouts for phase-shifted features
Classifications
U.S. Classification430/5, 430/322
International ClassificationG03F1/00, H01L21/027, G03F7/20, G03F9/00
Cooperative ClassificationG03F1/34, G03F1/26, G03F7/70283, G03F7/70433
European ClassificationG03F1/34, G03F7/70J2, G03F7/70F14, G03F1/26
Legal Events
DateCodeEventDescription
Nov 20, 2009FPAYFee payment
Year of fee payment: 12
Jun 2, 2009ASAssignment
Owner name: AMD TECHNOLOGIES HOLDINGS, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ADVANCED MICRO DEVICES, INC.;REEL/FRAME:022764/0488
Effective date: 20090302
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AMD TECHNOLOGIES HOLDINGS, INC.;REEL/FRAME:022764/0544
Nov 23, 2005FPAYFee payment
Year of fee payment: 8
Sep 28, 2001FPAYFee payment
Year of fee payment: 4