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Publication numberUS5777509 A
Publication typeGrant
Application numberUS 08/668,657
Publication dateJul 7, 1998
Filing dateJun 25, 1996
Priority dateJun 25, 1996
Fee statusPaid
Also published asDE69709925D1, DE69709925T2, EP0907916A1, EP0907916B1, WO1997050026A1
Publication number08668657, 668657, US 5777509 A, US 5777509A, US-A-5777509, US5777509 A, US5777509A
InventorsFrank Gasparik
Original AssigneeSymbios Logic Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Apparatus and method for generating a current with a positive temperature coefficient
US 5777509 A
Abstract
A bias current generator includes a first circuit component having a first voltage developed across a pair of terminals thereof, the first voltage decreasing as an operating temperature of the first circuit component increases. The bias current generator further includes a second circuit component having a second voltage developed across a pair of terminals thereof, the second voltage decreasing as an operating temperature of the second circuit component increases. In addition, the bias current generator includes an impedance element connected to the first circuit component and the second component, the impedance element (1) having an impedance which increases as an operating temperature of the impedance element increases, and (2) having a first current flowing therethrough, wherein a decrease in the first voltage causes a corresponding increase in the first current, and a decrease in the second voltage causes a corresponding increase in the first current. Moreover, the bias current generator includes a mirroring circuit for generating a second current which mirrors the first current flowing through the impedance element. A method for generating a bias current that counteracts the effects temperature has upon electron and hole mobility is also disclosed.
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Claims(20)
What is claimed is:
1. A bias current generator, comprising:
a first circuit component having a first voltage developed across a pair of terminals thereof, said first voltage decreasing as an operating temperature of said first circuit component increases;
a second circuit component having a second voltage developed across a pair of terminals thereof, said second voltage decreasing as an operating temperature of said second circuit component increases;
an impedance element connected to said first circuit component and said second circuit component, said impedance element (1) having an impedance which increases as an operating temperature of said impedance element increases, and (2) having a first current flowing therethrough, wherein a decrease in said first voltage causes a corresponding increase in said first current, and a decrease in said second voltage causes a corresponding increase in said first current; and
a mirroring circuit generating a second current which mirrors the first current flowing through said impedance element.
2. The bias current generator of claim 1, wherein said first circuit component, said second circuit component and said impedance element is interposed between a first reference potential and a second reference potential.
3. The bias current generator of claim 1, wherein said impedance element is interposed between said first circuit component and said second circuit component.
4. The bias current generator of claim 3, wherein:
said second circuit component includes a bipolar transistor having an emitter and a base, and
said emitter and said base having the second voltage developed thereacross.
5. The bias current generator of claim 4, wherein:
said first circuit component includes a first field effect transistor having a first source and a first gate, and
said first source and said first gate having the first voltage developed thereacross.
6. The bias current generator of claim 5, further comprising a third circuit component having a third voltage developed across a pair of terminals thereof, said third voltage decreasing as an operating temperature of said third circuit component increases, wherein:
said third circuit component includes a second field effect transistor having a second source and a second gate, and
said second source and said second gate having the third voltage developed thereacross.
7. The bias current generator of claim 6, wherein:
said bipolar transistor is a PNP transistor,
said first field effect transistor is a P-channel metal oxide semiconductor field effect transistor, and
said second field effect transistor is a P-channel metal oxide semiconductor field effect transistor.
8. The bias current generator of claim 6, wherein:
said bipolar transistor is a NPN transistor,
said first field effect transistor is a N-channel metal oxide semiconductor field effect transistor, and
said second field effect transistor is a N-channel metal oxide semiconductor field effect transistor.
9. The bias current generator of claim 6, wherein:
said mirroring circuit includes a third field effect transistor having a third gate and a third source,
said third field effect transistor generates the second current,
said first gate is coupled to said third gate, and
said first source is coupled to said third source.
10. The bias current generator of claim 9, wherein:
said mirroring circuit further includes a fourth field effect transistor having a fourth gate and a fourth source,
said fourth field effect transistor generates a third current,
said first gate is coupled to said fourth gate, and
said first source is coupled to said fourth source.
11. The bias current generator of claim 4, wherein the second voltage decreases at a rate of about 2.0 millivolts per Kelvin.
12. The bias current generator of claim 6, wherein said first voltage and said third voltage each decrease at a rate of about 2.6 millivolts per Kelvin.
13. The bias current generator of claim 12, wherein said impedance element has a temperature coefficient between about 200 parts per million per Kelvin (PPM/K) and about 10000 parts per million per Kelvin (PPM/K).
14. The bias current generator of claim 1, wherein said impedance element is a diffused resistor.
15. A bias current generator, comprising:
a first circuit component having a first voltage developed across a pair of terminals thereof, said first voltage decreasing as an operating temperature of said first circuit component increases;
a second circuit component having a second voltage developed across a pair of terminals thereof, said second voltage decreasing as an operating temperature of said second circuit component increases;
a third circuit component having a third voltage developed across a pair of terminals thereof, said third voltage decreasing as an operating temperature of said third circuit component increases; and
an impedance element connected to said first circuit component, said second circuit component and said third circuit component, said impedance element (1) having an impedance which increases as an operating temperature of said impedance element increases, and (2) having a first current flowing therethrough,
wherein (1) a decrease in said first voltage causes a corresponding increase in said first current, (2) a decrease in said second voltage causes a corresponding increase in said first current, and (3) a decrease in said third voltage causes a corresponding increase in said first current.
16. The bias current generator of claim 15, further comprising a mirroring circuit for generating a second current which mirrors the first current flowing through said impedance element.
17. The bias current generator of claim 16, wherein:
said first circuit component includes a first field effect transistor having a first source and a first gate,
said first source and said first gate having the first voltage developed thereacross,
said second circuit component includes a bipolar transistor having an emitter and a base,
said emitter and said base having the second voltage developed thereacross,
said third circuit component includes a second field effect transistor having a second source and a second gate, and
said second source and said second gate having the third voltage developed thereacross.
18. A method for generating a bias current, comprising the steps of:
developing a voltage across an impedance element so as to generate a first current; and
mirroring the first current so as to generate a second current,
wherein (1) said voltage increases at a first rate as an operating temperature of said impedance element increases, and (2) said impedance element has an impedance which increases at a second rate as an operating temperature of said impedance element increases, and (3) said first rate is greater than said second rate,
wherein said developing step includes the steps of (1) developing a first component voltage across a pair of terminals of a first circuit component, said first voltage decreasing as an operating temperature of the first circuit component increases, and (2) developing a second component voltage across a pair of terminals of a second circuit component, said second voltage decreasing as an operating temperature of said second circuit component increases, and
wherein (1) a decrease in said first component voltage causes a corresponding increase in said first current, and (2) a decrease in said second component voltage causes a corresponding increase in said first current.
19. The method of claim 18, wherein:
said developing step of a voltage across an impedance element further includes the step of developing a third component voltage across a pair of terminals of a third circuit component, said third voltage decreasing as an operating temperature of the third circuit component increases, and
wherein a decrease in said third component voltage causes a corresponding increase in said first current.
20. The method of claim 19, wherein:
said first circuit component includes a first field effect transistor having a first source and a first gate,
said first source and said first gate having the first voltage developed thereacross,
said second circuit component includes a bipolar transistor having an emitter and a base,
said emitter and said base having the second voltage developed thereacross,
said third circuit component includes a second field effect transistor having a second source and a second gate, and
said second source and said second gate having the third voltage developed thereacross.
Description
BACKGROUND OF THE INVENTION

The present invention relates generally to electrical current regulation, and more specifically to a bias generator for generating a bias current that counteracts the effect that temperature has upon electron and hole mobility.

In complementary metal oxide semiconductor (CMOS) integrated circuits both P-channel Metal Oxide Semiconductor Field Effect Transistor (PMOSFET) devices and N-channel Metal Oxide Semiconductor Field Effect Transistor (NMOSFET) devices are incorporated into a common substrate. Transconductance (gfs), as measured in micromhos, is the extent to which drain current (ID) changes in response to a change in gate-to-source voltage (Vgs); that is, gfs =dID /dVgs.

It is well known that PMOSFET and NMOSFET devices have a transconductance characteristic that has a negative temperature coefficient (i.e. a transconductance that increases with a decrease in temperature and decreases with an increase in temperature). A negative temperature coefficient transconductance characteristic causes a decrease in the switching speeds of PMOSFET and NMOSFET devices as temperature increases. The decrease in switching speeds of PMOSFET and NMOSFET devices is a direct result of a decrease in the electron and hole mobility associated with an increase in temperature. To offset the effects of a negative temperature coefficient transconductance characteristic, it is known to inject a proportional to absolute temperature bias current into the circuit.

In CMOS circuits, bipolar transistors are commonly regarded as parasitic vertical devices because bipolar transistors cause a vertical current to flow through the substrate whereas essentially the rest of the CMOS elements cause a horizontal current to flow across the surface of the substrate. However, when desired in a CMOS circuit bipolar PNP transistors may be implemented in an Nwell CMOS process, wherein a transistor base is formed from an Nwell diffusion, a transistor collector is formed from a P-type substrate, and a transistor emitter is formed from P+ of a P-channel drain/source diffusion. Likewise, bipolar NPN transistors may be implemented in a Pwell CMOS process, wherein a transistor base is formed from an Pwell diffusion, a transistor collector is formed from am N-type substrate, and a transistor emitter is formed from N+ of an N-channel drain/source diffusion. In both cases, the emitter-base voltage (VEB) has a large negative temperature coefficient whose value is a function of fabrication.

One of the best known ways of obtaining a proportional to absolute bias current is to take the difference in the VEB values of two bipolar devices operating at different current densities. This difference in VEB values is developed across a resistor to obtain the proportional to absolute temperature bias current. However, the bias current in known bias current generators does not adequately compensate for the decrease of electron and hole mobility associated with an increase of temperature. That is, known bias current generators are not able to generate a high enough bias current to compensate for the decrease in electron and hole mobility caused by a negative temperature coefficient transconductance characteristic of CMOS devices, when temperature increases.

For the foregoing reasons, there is a need for a bias current generator which sufficiently increases bias current as temperature increases in order to effectively counteract the negative effect that temperature has upon electron and hole mobility of CMOS devices.

SUMMARY OF THE INVENTION

The present invention is directed to a bias generator that satisfies this need for a bias current that counteracts the effect that temperature has upon electron and hole mobility.

In accordance with one embodiment of the present invention, there is a bias current generator which includes a first circuit component having a first voltage developed across a pair of terminals thereof, said first voltage decreasing as an operating temperature of the first circuit component increases. The bias current generator further includes a second circuit component having a second voltage developed across a pair of terminals thereof, said second voltage decreasing as an operating temperature of the second circuit component increases. In addition, the bias current generator includes an impedance element connected to said first circuit component and said second component, said impedance element (1) having an impedance which increases as an operating temperature of said impedance element increases, and (2) having a first current flowing therethrough, wherein a decrease in said first voltage causes a corresponding increase in said first current, and a decrease in said second voltage causes a corresponding increase in said first current. Moreover, the bias current generator includes a mirroring circuit for generating a second current which mirrors the first current flowing through the impedance element.

Pursuant to another embodiment of the present invention, there is provided a bias current generator which includes a first circuit component having a first voltage developed across a pair of terminals thereof, said first voltage decreasing as an operating temperature of the first circuit component increases. The bias current generator further includes a second circuit component having a second voltage developed across a pair of terminals thereof, said second voltage decreasing as an operating temperature of the second circuit component increases. In addition, the bias current generator includes a third circuit component having a third voltage developed across a pair of terminals thereof, said third voltage decreasing as an operating temperature of the third circuit component increases. Moreover, the bias current generator includes an impedance element connected to said first circuit component, said second circuit component and said third circuit component, said impedance element (1) having an impedance which increases as an operating temperature of said impedance element increases, and (2) having a first current flowing therethrough, and wherein (1) a decrease in said first voltage causes a corresponding increase in said first current, (2) a decrease in said second voltage causes a corresponding increase in said first current, and (3) a decrease in said third voltage causes a corresponding increase in said first current.

In accordance with yet another embodiment of the present invention, there is provided a method for generating a bias current. The method includes the steps of (1) developing a voltage across an impedance element so as to generate a first current; and (2) mirroring the first current so as to generate a second current. In the above method, (1) said voltage increases at a first rate as an operating temperature of said impedance element increases, and (2) said impedance element has an impedance which increases at a second rate as an operating temperature of said impedance element increases, and (3) said first rate is greater than said second rate. Further in the above method, said developing step includes the steps of (1) developing a first component voltage across a pair of terminals of a first circuit component, said first voltage decreasing as an operating temperature of the first circuit component increases, and (2) developing a second component voltage across a pair of terminals of a second circuit component, said second voltage decreasing as an operating temperature of the second circuit component increases. Additionally, in the above method, (1) a decrease in said first component voltage causes a corresponding increase in said first current, and (2) a decrease in said second component voltage causes a corresponding increase in said first current.

It is therefore an object of the present invention to provide a new and useful bias current generator.

It is another object of the present invention to provide an improved bias current generator.

It is still another object of the present invention to provide a new and useful method of generating a bias current.

It is another object of the present invention to provide an improved method of generating a bias current.

It is yet another object of the present invention to provide a bias current generator that counteracts the effect that temperature has upon electron and hole mobility.

It is yet another object of the present invention to provide a new and useful bias generator which can be implemented in the standard CMOS process.

It is a further object of the present invention to provide a bias current generator that counteracts the effect that temperature has on the switching speeds of PMOSFET and NMOSFET devices.

It is yet another object of the present invention to provide a new and useful method for generating a bias current that counteracts the effect that temperature has upon electron and hole mobility.

It is yet a further object of the present invention to provide a new and useful method which can be implemented in the standard CMOS process.

These and other features, aspects, and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a known bias current generator that generates a bias current with a positive temperature coefficient;

FIG. 2 is a schematic diagram of a first embodiment of a bias current generator which incorporates the features of the present invention therein;

FIG. 3 is a simplified block diagram of the bias current generator shown in FIG. 2;

FIG. 4 is a graph comparing the effect of temperature upon the bias currents generated by the bias current generators shown in FIGS. 1 and 2; and

FIG. 5 is a schematic diagram of a second embodiment of a bias current generator which incorporates the features of the present invention therein.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description is to be considered as exemplary and not restrictive in character, it being understood that only a preferred embodiments have been shown and described and that all changes and modifications that come within the spirit of the invention are desired to be protected.

Referring now to FIG. 1, there is shown a schematic diagram of a known bias current generator 2 that generates a bias current with a positive temperature coefficient. That is, bias current generator 2 generates a bias current IOUT1 with a small positive temperature coefficient. The bias generator 2 uses two transistors Q1 and Q2 with a resistor R1 to generate the bias current IOUT1. The metal oxide semiconductor (MOS) devices MPA and MPB serve as a current mirror which forces the two currents I1 and I2 flowing through the transistor Q1 and device Q2 respectively to be substantially equal. The transistors MNA and MNB with their respective gate-source voltages form a voltage loop with the transistors Q1 and Q2 and the resistor R1. This voltage loop may be represented by equation (1):

VGS (MNA)+I1 R1 +VEB (Q1)=VGS (MNB)+VEB (Q2)                             (1)

where VGS (MNA) represents the gate-source voltage of the transistor MNA expressed in Volts (V), I1 represents the current flowing through the transistor Q1 expressed in Amperes (A), R1 represents the resistance of the resistor R1 expressed in Ohms (Ω), VEB (Q1) represents the emitter-base voltage of the transistor Q1 expressed in Volts (V), VGS (MNB) represents the gate-source voltage of the transistor MNA expressed in Volts (V), and VEB (Q2) represents the emitter-base voltage of the transistor Q2 expressed in Volts (V).

The emitter-base voltage VEB (QN) of a transistor QN may be determined from equation (2): ##EQU1## where VEB (QN) represents the emitter-base voltage of the transistor QN expressed in Volts (V), k represents Boltzmann's constant of approximately 1.3810-23 Joules per Kelvin (J/K), T represents the absolute temperature expressed in Kelvin (K), q represents the charge of an electron which is approximately 1.6010-19 Coulombs (C), IN represents the current expressed in Amperes (A) flowing through the emitter of the transistor QN, ISN represents the reverse saturation current of the emitter-base diode of the transistor QN expressed in Amperes per square centimeter (A/cm2), and AEN represents the emitter area of the transistor QN expressed in square centimeters (cm2).

Substituting the right hand expression of equation (2) into equation (1) yields equation (3): ##EQU2## where IS1 represents the reverse saturation current of the emitter-base diode of the transistor Q1 expressed in Amperes per square centimeter (A/cm2), AE1 represents the emitter area of the transistor Q1 expressed in square centimeters (cm2), I2 represents the current expressed in Amperes (A) flowing through the transistor Q2, IS2 represents the reverse saturation current of the emitter-base diode of the transistor Q2 expressed in Amperes per square centimeter (A/cm2), and AE2 represents the emitter area of the transistor Q2 expressed in square centimeters (cm2).

The currents I1 and I2 are substantially equal because the transistors MPA and MPB are matched devices and their source-gate voltages VSG (MPA) and VSG (MPB) are the same. Therefore, the transistors MPA and MPB form a current mirror and force the current I1 to be substantially equal to the current I2. Furthermore, because the transistors Q1 and Q2 are matched devices except for the emitter areas AE1 and AE2 respectively, the reverse saturation currents Is, and IS2 of the transistors Q1 and Q2 are substantially equal. Furthermore, because the transistors MNA and MNB are matched devices and the currents I1 and I2 are substantially equal, the gate-source voltages VGS (MNA) and VGS (MNB) are substantially equal (see equation (9) below, substituting VGS (MNA) for VSG (MPN)). Therefore, after noting that the current I1 substantially equals the current I2, that the reverse saturation current IS1 substantially equals the reverse saturation current IS2, and that the gate-source voltage VGS (MNA) substantially equals the gate-source voltage VGS (MNB), equation (9) may be simplified to equation (4): ##EQU3##

Because the transistor MPC and the transistors MPA are matched devices and share the same source-gate voltage, the drain current IOUT1 of the transistor MPc mirrors the current I1 flowing through the transistor Q1 and substantially through the transistor MPA. As a result, the collection of like terms of equation (4) and the realization that the bias current IOUT1 is substantially equal to I1 yields equation (5): ##EQU4## where IOUT1 represents the bias current in Amperes (A) flowing through the transistor MPc. Therefore, at a given temperature T, the emitter area AE1 of the transistor Q1, the emitter area AE2 of the transistor Q2, and the resistance of the resistor R1 are the circuit design elements which control the bias current IOUT1.

As stated above, the bias current IOUT1 has a slight positive temperature coefficient. As can be seen from equation (5), if the terms other than the temperature T were substantially constant as temperature increases, the bias current IOUT1 would have a positive temperature coefficient. However, the resistance of the resistor R1 is not substantially constant as temperature increases. Diffused resistors like the resistor R1 increase over temperature and therefore have a positive temperature coefficient. The positive temperature coefficient of diffused resistors are dependent upon the material used to fabricate the resistor. For example heavier doped diffusions such as P+ and N+ yield resistors with lower temperature coefficients than resistors made with the typical NWELL or PWELL diffusion process. The rate of change in the resistance of diffused resistors like the resistor R1, however, is slower than the rate of the increase in the temperature T. Therefore, as can be seen from equation (5), the bias current IOUT1 increases with an increase in the temperature T because the value of T/R1 increases despite the positive temperature coefficient of the resistor R1.

The temperature T, however, has an exponential effect upon electron and hole mobility in the standard CMOS process. This effect upon electron and hole mobility may be represented by equation (6): ##EQU5## where T represents the temperature in Kelvin (K), μ(T) represents the mobility of electrons or holes at the temperature T, To represents room temperature in Kelvin (K) which is about 300 K, μ(To) represents the mobility of electrons or holes at the room temperature To. Because the bias current IOUT1 of FIG. 1 increases at a rate of approximately the change in the temperature (ΔT) over the change in the resistance (ΔR1) of the resistor R1 (ΔT/ΔR1), the bias current IOUT1 does not adequately increase in order to compensate for the exponential decrease of electron and hole mobility as shown in equation (3).

Now referring to FIG. 2, there is shown a schematic diagram of a first embodiment of a bias generator 10 which incorporates the features of the present invention therein. The bias current generator 10 may be fabricated using an Nwell CMOS process. In the preferred embodiment the transistors MPA, MPB, MP1, MP2, MP3, and MP4 are P-channel metal oxide semiconductor field effect transistors (PMOSFET). Likewise, the transistors MNA and MNB are N-channel metal oxide semiconductor field effect transistors (NMOSFET). The transistors Q1 and Q2 are parasitic PNP bipolar junction transistors (PNP BJT), and the resistors R1 and R2 are diffused resistors.

The transistor MPA is matched with the transistor MPB (i.e. the transistors are manufactured such that they have quite similar operating characteristics). Likewise, the transistor MP2 is matched with the transistors MP3 and MP4, the transistor MNA is matched with the transistor MNB, and the transistor Q1 is matched with the transistor Q2, except that the emitter area AE2 of the transistor Q2 is smaller than the emitter area AE1 of the transistor Q1. It should be appreciated by those skilled in the art that the above devices are matched only to simplify the design process and that non-matched devices could be used. It should further be appreciated by those skilled in the art that if transistors Q1 and Q2 are not matched devices, or if the current I1 is not substantially equal to the current I2 then the emitter area AE2 need not be smaller than the emitter area AE1. Furthermore, it should be appreciated by those skilled in the art that the use of non-matched devices will result in a bias generator 10 that generates a bias current IOUT1 that does not track temperature as well as the bias generator 10 would with matched devices.

The source and the substrate of the transistor MPA and the source and the substrate of the transistor MPB are connected to the reference voltage VDD. The gate of the transistor MPA is connected to the gate of the transistor MPB thereby forming a first current mirror. Likewise, the source and the substrate of the transistor MP2, the source and the substrate of the transistor MP3, and the source and the substrate of the transistor MP4 are connected to the reference voltage VDD. The gate of the transistor MP2 is connected at the node N3 to the gate of the transistor MP3, and to the gate of the transistor MP4 thereby forming a second current mirror.

The drain of the transistor MPA is connected to the gate of the transistor MPA and to the drain of the transistor MNA. The drain of the transistor MPB is connected to the drain of the transistor MNB, and the drain of the transistor MNB is connected to the gate of the transistor MNB. The gate of the transistor MNB is connected to the gate of the transistor MNA. The substrate of the transistor MNB and the substrate of the transistor MNA are connected to the reference voltage VSS. The resistor R1 is connected between the source of the transistor MNA and the emitter of the transistor Q1. The emitter of the transistor Q2 is connected to the source of the transistor MNB at the node N1. The base of the transistor Q2 is connected to the base of the transistor Q1. The base and the collector of the transistor Q1, and the base and the collector of the transistor Q2 are connected to the reference voltage VSS which is ground.

The gate of the transistor MP1 is connected at the node N1 to the source of the transistor MNB and to the emitter of the transistor Q2. The drain of the transistor MP1 is connected to the reference voltage VSS, and the substrate of the transistor MP1 is connected at the node N2 to the source of the transistor MP1. Finally, the resistor R2 is connected between the node N2 and the node N3.

The reference current IREF flows through the resistor R2. The bias current IOUT1 flowing out of the drain of the transistor MP3 mirrors the reference current IREF that flows out of the drain of the transistor MP2 and through the resistor R2. Likewise, the bias current IOUT2 flowing out of the drain of the transistor MP4 mirrors the reference current IREF that flows out of the drain of the transistor MP2 and through the resistor R2.

The operation of the first embodiment depicted in FIG. 2 will now be discussed in detail. As can be seen by comparing the bias current generator 2 shown in FIG. 1 to the bias current generator 10 shown in FIG. 2, the transistors MPA, MPB, MNA, MNB, Q1, and Q2 as well as the resistor R1 function in the same manner. As a result the currents I1 and I2 of FIG. 2 may be represented by equation (5) as set forth above.

As a result of the standard CMOS process, the resistor R1 has a positive temperature coefficient typically in the range from a few hundred to a few thousand parts per million per Kelvin (PPM/K). The positive temperature coefficient for the resistor R1 changes at a rate that is slower than the change in temperature. Therefore, as shown in equation (5), the current I1 has a positive temperature coefficient despite the positive temperature coefficient of the resistor R1. Referring now to equation (2), an increase in the current I1 would result in a small increase in the emitter-base voltage VEB (Q1) of the transistor Q1 if everything remained constant. However, because the reverse saturation current IS1 increases exponentially with an increase in the temperature T, a smaller emitter-base voltage VEB (Q1) of the transistor Q1 can drive the same current I1 that a larger emitter-base voltage VEB (Q1) drove at a lower temperature T. The net effect is that even though the currents I1 and I2 are increasing as temperature increases, the emitter-base voltages VEB (Q1) and VEB (Q2) are decreasing as temperature increases. Therefore, VEB (Q1) and VEB (Q2) have a negative temperature coefficient typically of about -2 millivolts per Kelvin (mV/K) which does not substantially change with process variation or operating conditions.

The path between the reference voltages VDD and VSS that goes through the source-gate voltage VSG (MP2) of the transistor MP2, the voltage VR2 across the resistor R2, the source-gate voltage VSG (MP1) of the transistor MP1, and the emitter-base voltage VEB (Q2) of the transistor Q2, can be expressed by equation (7): ##EQU6## where VR2 represents the voltage across the resistor R2 as a result of the reference current IREF flowing through the resistor R2. Equation (7) solved for the reference current IREF yields equation (8): ##EQU7##

The reference voltages VDD and VSS are usually predetermined by design criteria. For example, VSS is typically ground and VDD is typically between 3.3 volts and 5.0 volts but is likely to fall below 3 volts in the future for deep submicron CMOS devices (i.e. devices with a channel length of less than 0.3 microns). Furthermore, for a given current I2 the emitter-base voltage VEB (Q2) can be determined from equation (2) and at room temperature is typically about 700 millivolts (mV).

The source-gate voltages VSG (MP1) and VSG (MP2) are dependent upon their respective drain currents ID1 and ID2 which are both substantially equal to the reference current IREF and are also dependent upon other parameters which are usually set by the manufacturing process. Assuming the design criteria requires a predetermined bias current IOUT1 for a given temperature T, the reference current IREF is substantially equal to the bias current IOUT1 due to the current mirror formed by the transistors MP2 and MP3. Furthermore, the drain current ID1 of the transistor MP1 and the drain current ID2 of transistors MP2 are substantially equal to the reference current IREF because the gate currents of MOS transistors are usually negligible compared to the drain currents, the source-emitter voltages VSG (MP1) and VSG (MP2) may be determined from equation (9): ##EQU8## where μp represents the mobility of holes expressed in square centimeters per Volt second (cm2 / V sec), εo represents the permitivity of free space expressed in Farads per centimeter (F/cm), εr represents the relative dielectric constant of the semiconductor and is dimensionless, tox represents the thickness of the gate oxide expressed in centimeters (cm), VT represents the threshold voltage of the transistor MPN expressed in Volts (V), ID represents the drain current of the transistor MPN expressed in Amperes (A), W represents the width of the channel of the transistor MPN expressed in centimeters (cm), and L represents the length of the channel of the transistor MPN expressed in centimeters (cm).

An inherent quality of the standard CMOS process is that the threshold voltage VT of a MOS transistor has a negative temperature coefficient typically of about -2.6 mV. As shown in equation (9), the source-gate voltage VSG is directly dependent upon the threshold voltage VT. Therefore, the source-gate voltages VSG (MP1) and VSG (MP2) have a negative temperature coefficient because as temperature increases, the threshold voltage VT decreases and causes a decrease in the source-gate voltages VSG (MP1) and VSG (MP2).

Referring now to FIG. 3, there is shown a simplified block diagram of the bias current generator 10 shown in FIG. 2. The elements of FIG. 2 correspond to the blocks of FIG. 3 in the following manner: the source-gate voltage VSG (MP2) of the transistor MP2 corresponds with the output voltage of the voltage source VS1 ; the gate-source voltage VSG (MP1) of the transistor MP1 corresponds with the output voltage of the voltage source VS2 ; the emitter-base voltage VEB (Q2) of the transistor Q2 corresponds with the output voltage of the voltage source VS3 ; the resistor R2 corresponds with the impedance element Z2 ; the reference voltage VDD corresponds with the reference voltage VREF1 ; and the reference voltage VSS corresponds with the reference voltage VREF2. Therefore as can be seen from FIG. 3, the voltage sources VS1, VS2, and VS3 along with the reference voltages VREF1 and VREF2 generate a voltage VZ2 across the impedance element Z2 which may be represented by equation (10):

VZ2 =VREF1 -VS1 -VS2 -VS3 -VREF2 (10)

The reference voltages VREF1 and VREF2 remain substantially constant with a change in temperature. However, the output voltages of the voltage sources VS1, VS2, and VS3 decrease with an increase in temperature. Therefore, as can be seen from equation (10), the voltage VR2 across the impedance element Z2 increases with an increase in temperature and causes a reference current IREF to flow through the impedance element Z2. The reference current IREF that flows through the impedance element Z2 can be determined from the equation (11): ##EQU9## where VZ2 represents the voltage expressed in Volts (V) across the impedance element Z2, and Z2 represents the impedance expressed in Ohms (Ω) of the impedance element Z2. As discussed above, the impedance of impedance element Z2 increases with an increase in temperature but at a rate slower than the increase in the voltage VZ2 across the impedance element Z2. Therefore, as can be seen from equation (11), the reference current IREF has a positive temperature coefficient because the reference current IREF increases with an increase in temperature.

Referring now to FIG. 4, there is shown a graph comparing the effect of temperature upon the bias current IBIAS generated by the known bias current generator 2 (FIG. 1), and by the bias current generator 10 (FIG. 2) of the present invention. As can be seen from FIG. 4, the bias current generator 10 of the present invention has a more dramatic increase in bias current IBIAS as temperature increases than the known bias current generator 2. This more dramatic increase in the bias current IBIAS is a direct result of using three voltage sources having a negative temperature coefficient to drive the resistor R2. Furthermore, this more dramatic increase in the bias current IBIAS is the reason that the bias current generator 10 counteracts more effectively the effect that increased temperature has upon electron and hole mobility, than the known bias generator 2.

Now referring to FIG. 5, there is shown a schematic diagram of a second embodiment of a bias current generator 20 which incorporates the features of the present invention therein. As previously mentioned, the bias current generator 10 (FIG. 2) may be fabricated using an Nwell CMOS process. The bias current generator 20 (FIG. 5) is a Pwell CMOS representation of the bias current generator 10 (FIG. 2). In particular, the bias current generator 20 includes transistors MNA, MNB, MN1, MN2, MN3, and MN4 which are N-channel metal oxide semiconductor field effect transistors (NMOSFET). The bias current generator also includes transistors MPA and MPB which are P-channel metal oxide semiconductor field effect transistors (PMOSFET), transistors Q1 and Q2 which are parasitic NPN bipolar junction transistors (NPN BJT), and the resistor R1 and R2 which are diffused resistors.

The transistor MNA is matched with the transistor MNB (i.e. the transistors are manufactured such that they have quite similar operating characteristics). Likewise, the transistor MN2 is matched with the transistor MN3 and the transistor MN4, the transistor MPA is matched with the transistor MPB, and the transistor Q1 is matched with the transistor Q2 except that the emitter area AE2 of the transistor Q2 is smaller than the emitter area AE1 of the transistor Q1. It should be appreciated by those skilled in the art that the above devices are matched only to simplify the design process and that non-matched devices could be used. It should further be appreciated by those skilled in the art that if the transistors Q1 and Q2 are not matched devices or if the current I1 is not substantially equal to the current I2 then the emitter area AE2 need not be smaller than the emitter area AE1. Furthermore, it should be appreciated by those skilled in the art that the use of non-matched devices will result in a bias generator 20 that generates a bias current IOUT1 that does not track temperature as effectively as the bias generator 20 would with matched devices.

The source and the substrate of the transistor MNA and the source and the substrate of the transistor MNB are connected to the reference voltage VSS which is ground. The gate of the transistor MNA is connected to the gate of the transistor MNB thereby forming a first current mirror. Likewise, the source and the substrate of the transistor MN2, the source and the substrate of the transistor MN3, and the source and the substrate of the transistor MN4 are connected to the reference voltage VSS. The gate of the transistor MN2 is connected at the node N3 to the gate of the transistor MN3, and to the gate of the transistor MN4 thereby forming a second current mirror.

The drain of the transistor MNA is connected to the gate of the transistor MNA and to the drain of the transistor MPA. The drain of the transistor MNB is connected to the drain of the transistor MPB, and the drain of the transistor MPB is connected to the gate of the transistor MPB. The gate of the transistor MPB is connected to the gate of the transistor MPA. The substrate of the transistor MPB and the substrate of the transistor MPA are connected to the reference voltage VSS. The resistor R1 is connected between the source of the transistor MPA and the emitter of the transistor Q1. The emitter of the transistor Q2 is connected to the source of the transistor MPB at the node N1. The base of the transistor Q2 is connected to the base of the transistor Q1. The base and the collector of the transistor Q1, and the base and the collector of the transistor Q2 are connected to the reference voltage VDD.

The gate of the transistor MN1 is connected at the node N1 to the source of the transistor MPB and to the emitter of the transistor Q2. The drain of the transistor MN1 is connected to the reference voltage VDD, and the substrate of the transistor MN1 is connected at the node N2 to the source of the transistor MN1. Finally, the resistor R2 is connected between the node N2 and the node N3.

The reference current IREF flows through the resistor R2. The bias current IOUT1 flowing into the drain of the transistor MN3 mirrors the reference current IREF that flows into the drain of the transistor MN2 and through the resistor R2. Likewise, the bias current IOUT2 flowing into the drain of the transistor MN4 mirrors the reference current IREF that flows into the drain of the transistor MN2 and through the resistor R2.

Since the bias current generator 20 (FIG. 5) is simply a Pwell CMOS representation of the bias current generator 10 (FIG. 2), a detailed discussion regarding the operation of the bias current generator 20 is not warranted. Referring again to FIG. 3, the elements of the bias current generator 20 correspond to the blocks shown in FIG. 3 in the following manner: the gate-source voltage VGS (MN2) of the transistor MN2 corresponds with the output voltage of the voltage source VS1 ; the gate-source voltage VGS (MN1) of the transistor MN1 corresponds with the output voltage of the voltage source VS2 ; the base-emitter voltage VBE (Q2) corresponds with the output voltage of the voltage source VS3 ; the resistor R2 corresponds with the impedance element Z2 ; the reference voltage VDD corresponds with the reference voltage VREF2 ; and the reference voltage VSS corresponds with the reference voltage VREF1. Therefore, as can be seen from FIG. 3, the voltage sources VS1, VS2, and VS3 along with the reference voltages VREF1 and VREF2 generate a voltage VR2 across the impedance element Z2 which may be represented by equation (10) hereinabove.

The reference voltages VREF1 and VREF2 remain substantially constant with a change in temperature. However, the output voltages of the voltage sources VS1, VS2, and VS3 decrease with an increase in temperature. Therefore, as can be seen from equation (10), the voltage VZ2 across the impedance element Z2 increases with an increase in temperature and causes a reference current IREF to flow through the impedance element Z2. The reference current IREF that flows through the impedance element Z2 can be determined from the equation (11) hereinabove.

Furthermore, the impedance of impedance element Z2 increases with an increase in temperature but at a rate slower than the increase in the voltage VZ2 across the impedance element Z2. Therefore, as can be seen from equation (11), the reference current IREF has a positive temperature coefficient because the reference current IREF increases with an increase in temperature.

While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description is to be considered as exemplary and not restrictive in character, it being understood that only the preferred embodiment has been shown and described and that all changes and modifications that come within the spirit of the invention are desired to be protected.

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Classifications
U.S. Classification327/542, 327/539, 327/543, 323/312, 323/315, 327/538
International ClassificationG05F3/26
Cooperative ClassificationG05F3/267
European ClassificationG05F3/26C
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