|Publication number||US5781791 A|
|Application number||US 08/636,996|
|Publication date||Jul 14, 1998|
|Filing date||Apr 16, 1996|
|Priority date||Apr 16, 1996|
|Publication number||08636996, 636996, US 5781791 A, US 5781791A, US-A-5781791, US5781791 A, US5781791A|
|Inventors||Michael A. Dukes, Kenneth J. Keyes, Jr., Gerald T. Michael|
|Original Assignee||The United States Of America As Represented By The Secretary Of The Army|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (11), Non-Patent Citations (6), Classifications (13), Legal Events (7)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The invention described herein may be manufactured, used, imported and licensed by or for the Government for the United States of America without the payment to us of any royalty thereon.
The invention relates in general to digital microelectronic circuits, and in particular to a circuit package for integrated circuit replacement parts.
Programmable devices and memories bought off-the-shelf have generally had limited pin voltage application. Further, the delay and impedance of a chosen programmable device or memory are relatively fixed to a given range. As the development of electronic systems has progressed, supply voltages have typically dropped and chip speed has increased. Therefore, a chip manufactured from a process line today may not function reliably in a system from several years ago.
These incompatibilities have been especially problematic in the areas of reverse-engineered electronics and maintaining/sustaining systems in the field. In the case of a failed system, replacing a digital microelectronic circuit may be all that is required to make the system function again. However, a digital microelectronic circuit from an old system may no longer be available from an original or replacement-parts manufacturer. Primarily, this occurs when the original system has application-specific integrated circuits (ASICs) for a system which is 5 to 10 years of age, or has other digital microelectronic circuits for a system 5 to 20 years of age.
Where the digital microelectronic circuit is no longer available, the system's PC board or subsystem must be altered or redesigned to accommodate an on-board programmable device or memory and on-board voltage/impedance/delay-matching buffers so that the programmable device or memory will function properly. This process incurs greater cost and possible resupply delays, since an entire board must be redesigned and tested to ensure no errors were introduced from the board redesign. Further, a new board or subsystem is introduced into the supply system.
It is therefore an object of the invention to provide a microelectronic circuit package with improved compatibility characteristics.
The invention provides a digital microelectronic circuit replacement package which matches the form, fit, and function of the original part by employing at least one buffer die in combination with a programmable device or memory. The buffer die performs the functions of impedance-matching, delay-matching, and voltage-matching, while the programmable device or memory can be used to emulate the logic and/or storage functions of the original digital microelectronic circuit; the package of the invention can be used as a direct replacement for a digital microelectronic circuit without the requirement that the original circuit board be redesigned to accommodate modern voltage, impedance, and delay specifications associated with the programmable device or memory.
These and other objects, features, and details of the invention will become apparent in light of the ensuing detailed disclosure, and particularly in light of the drawings wherein:
FIG. 1 illustrates a schematic view of the invention according to a preferred embodiment.
With reference to FIG. 1, a package 1 includes a substrate 3 having mounted thereon buffers 5, 7, and a Digital Microelectronic Circuit (DMC) 9. According to preferred embodiments of the invention, the DMC 9 is either a programmable device or a memory, depending upon the specific application. The classes of programmable devices which are preferably used include, but are not limited to, programmable logic devices, field-programmable gate arrays, and synthesized circuits. The classes of memories which are preferably used include, but are not limited to, random-access memories, read-only memories, and programmable read-only memories.
Pins 11 are provided on the package and are wired to the internal buffer dies via wiring 13. The pins 11 function as an interface from a board or DMC mount to the internal buffer dies. The internal buffer dies are in turn wired to the DMC 9.
The buffer dies are preferably designed to perform the functions of impedance-matching, delay-matching, and voltage-matching. However, it should be noted that, in applications where one or more of those functions is not required, the buffer dies of the invention need not perform that function. Further, although one DMC 9 is shown in the embodiment of FIG. 1, more than one DMC may be used for the space provided. And, although a dual in-line package (DIP) is shown, a pin-grid array (PGA) package could also be modified in a manner similar to that shown in FIG. 1 without departing from the spirit and scope of the invention. Any packaging that contains a cavity for the mounting of a die can be used in the manner described herein.
The invention provides a mechanism for fast production of replacement parts, on demand, that can be programmed for any application and mounted in a chip package conforming to the appropriate application's voltage, impedance, and delay characteristics. The invention permits use of developments in multi-chip module (MCM) manufacturing processes, and allows systems to take advantage of developments in low-power designs and reliability by providing a replacement part that uses less power and has a greater mean-time between failure. By replacing a single DMC with another DMC which has the form, fit, and function of the original DMC, a major board redesign effort is avoided, permitting more obsolete part problems to be addressed.
The number of gates that can be handled by the package of the invention is limited by the capacity of the programmable device or memory employed. However, in most cases, the number of gates required by the old technology will fall within the capacity of the available programmable devices and memories.
The invention provides significant advantages to companies with an investment in expensive, durable-item goods that contain systems made up of DMCs integrated with other equipment. Examples of such equipment include, e.g., aircraft, construction, and other factory-equipment.
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|1||*||Glasser, Lance A. and Daniel W. Dobberpuhl. The Design and Analysis of VLSI Circuits. Reading: Addison Wesley Publishing Company. 1985.|
|2||Glasser, Lance A. and Daniel W. Dobberpuhl. The Design and Analysis of VLSIircuits. Reading: Addison-Wesley Publishing Company. 1985.|
|3||*||Keys, Kenneth J. and Michael A. Dukes. A VHDL to Altera FPGA Translator for Obsolete Integrated Circuit Emulation, in Proceedings of Advances in Modeling and Simulation Conference , Redstone Arsenal, Alabama, 26 28 Apr., 1994.|
|4||Keys, Kenneth J. and Michael A. Dukes. A VHDL to Altera FPGA Translator for Obsolete Integrated Circuit Emulation, in Proceedings of Advances in Modeling and Simulation Conference, Redstone Arsenal, Alabama, 26-28 Apr., 1994.|
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|U.S. Classification||712/32, 361/736|
|International Classification||H05K1/18, H01L25/18, H05K1/00, H05K1/14|
|Cooperative Classification||H05K1/18, H01L25/18, H05K1/141, H01L2924/0002, H05K1/0286, H01L2924/3011|
|May 11, 1998||AS||Assignment|
Owner name: ARMY, GOVERNMENT OF THE UNITED STATES OF AMERICA,
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KEYES, KENNETH J.;VITRONICS;REEL/FRAME:009225/0672;SIGNING DATES FROM 19960220 TO 19960228
Owner name: ARMY, UNITED STATES OF AMERICA, THE, AS REPRESENTE
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DUKES, MICHAEL A.;MICHAEL, GERALD T.;REEL/FRAME:009225/0814;SIGNING DATES FROM 19960220 TO 19960405
|Feb 6, 2002||REMI||Maintenance fee reminder mailed|
|Jun 13, 2002||SULP||Surcharge for late payment|
|Jun 13, 2002||FPAY||Fee payment|
Year of fee payment: 4
|Feb 1, 2006||REMI||Maintenance fee reminder mailed|
|Jul 14, 2006||LAPS||Lapse for failure to pay maintenance fees|
|Sep 12, 2006||FP||Expired due to failure to pay maintenance fee|
Effective date: 20060714