|Publication number||US5861719 A|
|Application number||US 08/878,165|
|Publication date||Jan 19, 1999|
|Filing date||Jun 18, 1997|
|Priority date||Jun 18, 1997|
|Publication number||08878165, 878165, US 5861719 A, US 5861719A, US-A-5861719, US5861719 A, US5861719A|
|Inventors||Gregory N. Koskowich, W. Latham II Paul|
|Original Assignee||Imp, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (31), Non-Patent Citations (8), Referenced by (19), Classifications (10), Legal Events (8)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention relates generally to power supplies and voltage converters, and, in a specific implementation, to circuits that drive electroluminescent lamps with a high alternating polarity voltage from a low voltage battery supply.
A type of electroluminescent lamp that is widely used in numerous applications is a thin structure formed of a layer of electroluminescent material sandwiched between two conductive electrode layers. One of the electrodes is optically transparent to the resulting luminescence. When a sufficiently high voltage is applied across the two electrodes, a resulting electric field causes the intermediate electroluminescent layer to emit light that is visible through the transparent electrode. The brightness of the emission depends upon the magnitude of the voltage applied. Very little current is consumed in the process. The polarity of the supply voltage is alternated at a sufficiently high rate to prevent a build up of charge that causes the intensity of the luminescence to significantly diminish. A power supply especially designed for driving electroluminescent lamps is generally used.
Applications of this type of lamp include the back lighting of portable electronic devices such as watches, telephones, pagers, and the like. Such lamps are also used in automobile dashboards to provide back lighting of various displays. Included among other applications are displays where the lamps are either shaped or masked to form some symbol, letter or number. In most applications, the power supply to the lamp is required to convert a low direct current battery voltage, such as 1.5, 3.0 or 12 volts, into a voltage across the electrodes of the lamp that is 100 volts or more, and having an alternating polarity. A frequency in a range of about 100-1000 Hz. is generally used. Too high a frequency diminishes the life of the lamp and too low a frequency causes visible flicker.
A typical electroluminescent lamp driver uses the fact that this type of lamp has the electrical characteristics of a capacitor. An inductor is connected to a low voltage battery through a transistor switch. This switch is repetitively turned on, to store energy from the battery in the inductor, and then quickly and sharply turned off to generate a high voltage spike or pulse. A series of such pulses applied to the lamp causes a charge to build up in its equivalent capacitor and thus increase the voltage across its electrodes. The high voltage causes the lamp's electroluminescent material dielectric to emit light. The polarity of the charge accumulation in the lamp capacitor is periodically reversed by alternating the polarity of the voltage applied to the lamp, through use of a bridge switching circuit or the like.
It is a primary object of the present invention to provide such a power supply for electroluminescent lamps that regulates and controls the maximum voltage that results from the accumulated charge.
It is another object of the present invention to provide such a voltage controlled power supply that itself consumes little power, thus extending battery life.
It is a further object of the present invention to provide such a power supply on a single integrated circuit chip with only the battery and inductor outside of the circuit chip.
It is a more general object of the present invention to provide an integrated circuit voltage converting techniques of a general application.
These and additional objects are accomplished by the present invention, wherein, briefly and generally, according to one aspect embodied in an electroluminescent lamp driver, a voltage proportional to the build up of charge across the inherent capacitance of the lamp, resulting from switched inductor voltage pulses being applied to the lamp, is monitored. Application of voltage pulses to the lamp is terminated when that monitored voltage reaches a predetermined magnitude, this being accomplished in a preferred form by ceasing to switch the inductor. Voltage pulses are again applied to the lamp after their polarity is switched, preferably by commencing the switching of the inductor. This limiting circuit technique protects integrated circuit elements and components from the damage that can result from an excessive voltage being applied internally on a circuit chip. The brightness of the electroluminescent lamp emission is also maintained more uniform.
An appropriate voltage within the driver circuit, either that applied to the lamp or some other related voltage, is monitored by a non-resistive voltage divider formed of multiple capacitors on the integrated circuit chip and connected in series across the voltage. The voltages generated in the driving circuit are then maintained within desired operating ranges of integrated circuit components and the lamp itself, without need for the extensive integrated circuit chip space, increased power consumption and heat that result when a voltage divider of resistors is used. A voltage control circuit, formed of standard circuit components, receives a voltage drop across one of the capacitors that is proportional to the voltage being monitored. Multiple additional capacitors are preferably included as part of the voltage divider. The voltage drop across each of the capacitors is then small, and this allows each of the capacitors to be formed with a thin dielectric by standard processing techniques. The amount of chip space consumed by such a voltage divider is very small.
According to another aspect of the present invention, the potential of electromagnetic interference resulting from the on chip switching circuits is minimized. In a preferred form, capacitors are formed on the chip and connected across both the switched inductor and the polarity switching bridge.
Additional objects, features and advantages of the various aspects of the present invention are included in the following description of its preferred embodiments, which description should be taken in conjunction with the accompanying drawings.
FIG. 1 is a circuit diagram of a first embodiment of the present invention;
FIG. 2A-F show voltage waveforms at various nodes of the circuit of FIG. 1; and
FIG. 3 is a circuit diagram of a second embodiment of the present invention.
Referring to the circuit diagram embodiment of FIG. 1, nearly all of the power supply converter is contained on an integrated circuit chip 11. Only an inductor L is required off-chip, being connected to the chip at terminals 13 and 15. A battery 17, also provided off-chip, is connected to the chip at terminals 13 (positive d.c. supply voltage VDD) and 19 (negative d.c. supply voltage VSS). A load in the form of an electroluminescent lamp 21 of the type described above, which exhibits a significant capacitance across its two terminals, is connected to terminals 23 and 25 of the chip 11. The circuit chip 11 and external inductor L convert a low d.c. battery voltage, such as 1.5, 3.0 or 12.0 volts, across the chip's input terminals 13 and 19, into a much higher voltage at the chip's output terminals 23 and 25, such as 100 volts or more, with a relative polarity that alternates therebetween.
The input battery voltage is initially increased by alternately connecting and rapidly disconnecting the inductor L from the battery 17. This is accomplished by a field effect transistor M1 connected between one side of the inductor L and the supply voltage VSS. The transistor M1 is turned on and off by a clock signal fg (FIG. 2F) applied to its gate. The clock signal fg originates from an output fi (FIG. 2A) of an oscillator 27. Alternatively, the clock signal fi could be supplied from outside the chip 11 through another terminal. In order to obtain the signal fg, the signal fi is selectively blocked by an AND-gate 29 having as inputs the clock signal fi and an output of a comparator 31, to be explained below. In response to the transistor M1 being turned off, at each trailing edge of the clock signal pulses fg, a voltage spike occurs at a circuit node 33 that is much higher that the voltage across the battery 17.
It is these voltage spikes at the circuit node 33 that causes charge to be accumulated in the inherent capacitance of the lamp 21. The node 33 is connected by a diode D1 to the lamp 21 through an H-bridge circuit 35 connected across an inductively spiked voltage v3 and the reference voltage VSS with the lamp terminals 23 and 25 connected in its middle. The H-bridge alternates the polarity of the voltage v3 applied across the lamp 21 in response to a second clock signal fc (FIG. 2B). The clock signal fc is derived from a divider 36 connected to receive the clock signal fi. The H-bridge 35 includes transistors M2 and M5 that are turned on and off by the clock signal fc, and transistors M3 and M4 that are switched by an inverted form of the clock fc, obtained from an inverter 37. As the charge in the lamp capacitance from the inductive voltage spikes accumulates in one polarity, the voltage across the lamp 21 continues to increase. When the polarity across the lamp is switched, its inherent capacitance is discharged and the voltage build-up in the opposite polarity begins.
The voltage across the capacitance is not allowed by the circuit of FIG. 1 to build up to whatever level it can achieve for the number of trailing edges of the clock signal fi that occur during each one-half period of the clock fc. This number would be equal to a ratio of fc /fi if some further control is not imposed. In order to better control, the voltage rise across the lamp terminals 23 and 25, or a related voltage within the power supply, is monitored within the power supply of FIG. 1 by a closed loop system that maintains the monitored voltage below a desired maximum.
In the embodiment of FIG. 1, the internal voltage v1 is monitored by a capacitive voltage divider 39 connected between the node 33 and the supply potential VSS. The voltage divider 39 is formed of a number, in this case seven, capacitors C1-C7 connected in series. A voltage v2 (FIG. 2C) across the capacitor C7 is applied to an inverting input of the comparator 31. A non-inverting input of the comparator 31 receives a reference voltage VREF from a voltage reference source 41 connected across the supply voltages VDD and VSS. When the voltage v2 is less than VREF, the output of the comparator 31 (FIG. 2E) is high and thus causes the AND-gate 29 to apply the clock signal fi to the gate of the transistor M1 as signal fg (FIG. 2F). Conversely, when the voltage v2 exceeds VREF, the output of the comparator 31 goes low, with the result of the AND-gate 29 blocking the clock signal fi from reaching the transistor M1. During the interval when the transistor M1 is not being switched by an absence of the clock signal fg, no inductive voltage spikes are generated and the build up of the voltage v1 is maintained below a maximum value that is VREF multiplied by some constant. That constant depends upon the relative capacitance of the voltage divider capacitors C1-C7. In the specific example being described, this constant is a ratio of the sum of the values of the capacitances C1-C6, divided by the value of the capacitor C7.
The voltage divider 39 could alternatively be implemented with just two series connected capacitors, a relatively small capacitor C7 and another much larger capacitor in place of capacitors C1-C6. These relative values are dictated by this circuit where the maximum voltage of v1 is in the neighborhood of 100 volts for an electroluminescent lamp load, and a maximum voltage VREF that the comparator 31 wants to see across the capacitor C7 is only a few volts, such as 3.0 or 5.0 volts, that is typical of current integrated circuit implementations. A difficulty in using only two capacitors is that the one capacitor in place of C1-C6 would need to have many times the area of the capacitor C7, and its dielectric layer would need to be much thicker in order to withstand the higher voltage. Therefore, the use of multiple individual capacitors, C1-C6 being shown as an example, instead of just one, is generally preferable since this form of voltage divider 39 is easier to implement with standard integrated circuit techniques.
The capacitors of the voltage divider 39 are periodically discharged simultaneously with the H-bridge 35 changing the polarity of the voltage being applied across the lamp 21. In the implementation shown, each of the capacitors C1-C7 has connected across it one of switching transistors M6-M12. The gates of all the transistors M6-M12 are connected to an output of an edge triggered one-shot multivibrator 43. The one-shot 43 emits a short pulse (FIG. 2D) at each edge of its input signal, which is the clock signal fc. Thus, at each of both positive and negative going edges of the clock signal fc, all of the capacitors C1-C7 are discharged. After discharge, they are then in a condition to operate during a new cycle of being charged by the inductive voltage spikes applied across the voltage divider C1-C7.
As an alternative to the use of switching transistors M6-M12, a number of diodes may be used. Each such diode is connected between individual ones of the capacitors and the reference potential VSS in a manner to be reversed biased by the inductive voltage spikes being generated, so as not to be conducting then, while discharging the individual capacitors when such voltage drops at the end of each such spike below the thresholds of the individual diodes.
Two additional capacitors C8 and C9 are employed to reduce any electromagnetic interference (emi) that might result from use of the power supply. The capacitor C8 is connected across the inductor L and sized to provide a low impedance short circuit to very high frequencies that can be generated from alternately connecting the inductor L to and disconnecting the inductor L from the battery 17. Similarly, the capacitor C9 is connected across the H-bridge 35 to suppress any such very high frequency components that might result from alternately connecting the voltage v3 to the lamp terminals 23 and 25.
Another embodiment is shown in FIG. 3, wherein much of the circuit on a chip 11' is the same as that of the chip 11 in the embodiment of FIG. 1, common elements being given the same reference numbers. The difference is in the feedback maximum voltage control. Instead of monitoring the voltage v1, lamp voltages v4 and v5 are monitored by separate capacitive voltage dividers 51 and 53 that are individually substantially the same as the voltage divider 39 of the FIG. 1 embodiment. The voltage dividers 51 and 53 generate reduced voltages v2a and v2b across their capacitors C16 and C23, respectively. A multiplexer 55 connects one of the voltages v2a or v2b to the inverting input of the comparator, in response to the clock signal fc. While the H-bridge 35 is connecting the lamp terminal 23 to the voltage v3 and the terminal 25 to VSS, the multiplexer 55 connects the voltage v2a of the divider 51 to the comparator 31. Conversely, while the H-bridge 35 is connecting the lamp terminal 25 to the voltage v3 and the terminal 23 to VSS, the multiplexer 55 connects the voltage v2b of the divider 53 to the comparator 31.
In yet another embodiment, the voltages at the lamp terminals 23 and 25 are monitored with use of a single capacitive voltage divider. This is done by locating the multiplexer ahead of the voltage divider in a manner to alternately connect the single voltage divider to the voltages v4 or v5, depending upon which one is receiving the voltage v3. An advantage of this other embodiment is that only one voltage divider is required, but a disadvantage is that the multiplexer needs to withstand the high voltages of the lamp output. In the embodiment of FIG. 3, the multiplexer 55 operates at the low voltage of the comparator 31.
Although the present invention has been described with respect to its preferred embodiments, it will be understood that the invention is entitled to protection within the full scope of the appended claims.
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|U.S. Classification||315/209.00R, 363/98|
|International Classification||H02M3/156, H05B33/08|
|Cooperative Classification||H02M3/156, Y02B20/325, H02M2001/007, H05B33/08|
|European Classification||H05B33/08, H02M3/156|
|Jun 18, 1997||AS||Assignment|
Owner name: IMP, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KOSKOWICH, GREGORY N.;LATHAM, PAUL W. II;REEL/FRAME:008615/0343;SIGNING DATES FROM 19970521 TO 19970610
|May 6, 1999||AS||Assignment|
Owner name: CIT GROUP/CREDIT FINANCE, INC., THE, CALIFORNIA
Free format text: SECURITY INTEREST;ASSIGNOR:IMP, INC., A DELAWARE CORPORATION;REEL/FRAME:009968/0007
Effective date: 19990430
|Aug 6, 2002||REMI||Maintenance fee reminder mailed|
|Jan 15, 2003||FPAY||Fee payment|
Year of fee payment: 4
|Jan 15, 2003||SULP||Surcharge for late payment|
|Aug 9, 2006||REMI||Maintenance fee reminder mailed|
|Jan 19, 2007||LAPS||Lapse for failure to pay maintenance fees|
|Mar 20, 2007||FP||Expired due to failure to pay maintenance fee|
Effective date: 20070119